CN114625194A - Reference voltage generating circuit and generating method thereof - Google Patents
Reference voltage generating circuit and generating method thereof Download PDFInfo
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Abstract
The invention discloses a reference voltage generating circuit and a generating method thereof, wherein the circuit comprises: a frequency divider for dividing an initial clock signal to generate a plurality of sub-clock signals having different clock periods; the selection module is used for selecting and outputting one of the plurality of sub-clock signals based on a plurality of selection signals; a counter for generating a plurality of count clocks based on an output signal of the selection module; and the digital-to-analog converter is used for performing digital-to-analog conversion on the count values represented by the plurality of counting clocks based on the first reference voltage and the second reference voltage to generate reference voltage, wherein the level state of the last-stage selection signal in the plurality of selection signals has at least one jump in the same counting period of the counter. The reference voltage generating circuit and the generating method thereof can change the generating slope of the reference voltage, realize the nonlinear increase of the reference voltage along with time, and improve the applicability of the circuit to different application scenes.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a reference voltage generating circuit and a generating method thereof.
Background
The common application field of the circuit often requires a reference voltage supply, and the common solution is shown in fig. 1a, where fig. 1a shows a schematic circuit structure diagram of a conventional reference voltage generating circuit, and a reference voltage Vref is obtained at an intermediate node between a current source i and a capacitor C by serially connecting the current source i and the capacitor C between a power source terminal VDD and a reference ground.
However, as shown in fig. 1b, fig. 1b shows a schematic diagram of a time-varying reference voltage curve in fig. 1a, and the time-varying reference voltage Vref generated by the circuit is linear, which cannot meet the application requirements of different slopes. Meanwhile, based on the circuit configuration, if the reference voltage Vref is used for a long period of time, the current supplied by the current source i needs to be extremely small, or the capacitance value of the capacitor C needs to be extremely large, which is not easy to implement.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a reference voltage generating circuit and a generating method thereof, which can change the generating slope of the reference voltage, realize the non-linear increase of the reference voltage along with time and improve the applicability of the circuit to different application scenes.
In a first aspect, the present invention provides a reference voltage generating circuit, including: a frequency divider for dividing an initial clock signal to generate a plurality of sub-clock signals having different clock periods;
the selection module is connected with the frequency divider and used for selecting and outputting one of the plurality of sub-clock signals based on a plurality of selection signals;
the counter is connected with the selection module and used for generating a plurality of counting clocks based on the output signal of the selection module;
a digital-to-analog converter connected to the counter and receiving a first reference voltage and a second reference voltage for performing digital-to-analog conversion on the count values represented by the plurality of count clocks based on the first reference voltage and the second reference voltage to generate a reference voltage,
and in the same counting period of the counter, the level state of the last stage of selection signals in the plurality of selection signals can be adjusted.
Optionally, the number of selection signals is a fraction of the plurality of count clocks.
Optionally, the selection module comprises:
the input end of the first selector receives a first part of sub-clock signals in the plurality of sub-clock signals, and the output end of the first selector selects and outputs one of the first part of sub-clock signals based on a first selection signal in the plurality of selection signals;
a second selector, the input end receives a second part of sub-clock signals in the plurality of sub-clock signals and the output signal of the first selector, the output end selects and outputs one of the second part of sub-clock signals or the output signal of the first selector based on a second selection signal in the plurality of selection signals,
wherein the second selection signal is a last stage selection signal among the plurality of selection signals.
Optionally, the level state of each of the plurality of selection signals is adjustable in the same counting period of the counter.
Optionally, the digital-to-analog converter comprises:
the first branch circuit comprises a plurality of second resistors and a plurality of first resistors which are connected in series between a first reference voltage input end and a reference voltage output end;
a plurality of second branches, each second branch comprising:
the first input end of the selection switch is connected with the first reference voltage input end, and the second input end of the selection switch is connected with the second reference voltage input end;
a plurality of second resistors connected between the first branch and the output terminal of the selection switch,
the plurality of selection switches on the plurality of second branches correspondingly receive the plurality of counting clocks, and a first resistor is arranged between the connection nodes of any two adjacent second branches and the first branch.
Optionally, each second branch includes a second resistor, and a resistance value of each second resistor is twice a resistance value of the first resistor.
Optionally, each second branch includes two second resistors connected in series, and a resistance value of each second resistor is equal to a resistance value of the first resistor.
In a second aspect, a method for generating a reference voltage according to the present invention includes:
generating a plurality of count clocks based on an initial clock signal and a number of select signals;
performing digital-to-analog conversion on the count values represented by the plurality of count clocks based on a first reference voltage and a second reference voltage to generate a reference voltage,
and in the same counting period corresponding to the plurality of counting clocks, the level state of the last stage of selection signals in the plurality of selection signals can be adjusted.
Optionally, generating a plurality of count clocks based on the initial clock signal and the number of select signals comprises:
generating a plurality of sub-clock signals having different clock periods based on an initial clock;
selecting and outputting one of the plurality of sub-clock signals based on the plurality of selection signals;
and counting based on the sub-clock signals which are selectively output, and generating the plurality of counting clocks.
Optionally, the level state of each of the plurality of selection signals is adjustable in the same counting period corresponding to the plurality of counting clocks.
The invention has the beneficial effects that: the present disclosure relates to a reference voltage generating circuit and a generating method thereof, which uses a counter and a digital-to-analog converter to generate a reference voltage with different slopes in different time periods. In the process of generating the reference voltage, because the level state of the last stage of selection signals in a plurality of selection signals in the same counting period of the counter is adjustable, and further, by adjusting the level state of the selection signals, the clock period of a basic clock when the counter counts in different time periods of a counting period can be changed, and the adjustment of the clock periods of a plurality of counting clocks output by the counter is realized, so that the time required by the counter when a unit counting value in the same counting period is stepped is changed, a reference voltage curve with adjustable slope is finally obtained, the nonlinear increase of the reference voltage along with the time is realized, and the reference voltages with different slopes in different time periods in the same counting period are also generated. On the other hand, if the level state of the last stage selection signal in the plurality of selection signals is not adjusted in the same counting period of the counter, the linear increase of the reference voltage along with the time can be realized. The function of the reference voltage generating circuit is enhanced, and the applicability of the reference voltage generating circuit to different application scenes is improved. Meanwhile, devices adopted by the reference voltage generating circuit are conventional, the characteristics are good, and long-time utilization of the reference voltage is easy to realize.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
FIG. 1a is a schematic diagram of a conventional reference voltage generating circuit;
FIG. 1b is a schematic diagram showing the time dependence of the reference voltage in FIG. 1 a;
FIG. 2 is a schematic diagram of a reference voltage generation circuit provided in accordance with an embodiment of the present disclosure;
fig. 3 shows a schematic diagram of an internal circuit configuration of the digital-to-analog converter of fig. 2;
FIG. 4 is a graph illustrating a time dependence of a reference voltage provided in accordance with an embodiment of the present disclosure;
fig. 5 shows a block flow diagram of a method for generating a reference voltage provided according to an embodiment of the present disclosure.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 2 shows a schematic structural diagram of a reference voltage generation circuit provided according to an embodiment of the present disclosure.
As shown in fig. 2, in the embodiment of the present disclosure, the reference voltage generating circuit includes: divider 100, selection module 200, counter 300 and digital-to-analog converter 400. The input end of the frequency divider 100 receives an initial clock signal CLK, and the output end of the frequency divider 100 is connected to the input end of the selection module 200. The selection module 200 also receives a number of selection signals, while the output of the selection module 200 is connected to the input of the counter 300. The output of the counter 300 is connected to a first input of a digital-to-analog converter 400. The second input terminal and the third input terminal of the digital-to-analog converter 400 respectively receive the first reference voltage VA and the second reference voltage VB, and the output terminal of the digital-to-analog converter 300 outputs the reference voltage Vref.
In the present embodiment, the frequency divider 100 is used for dividing the initial clock signal CLK to generate a plurality of sub-clock signals with different clock periods. The selection module 200 is configured to select one of the plurality of sub-clock signals to be output based on a plurality of selection signals. The counter 300 is used to generate a plurality of count clocks based on the output signal of the selection module 200. The digital-to-analog converter 400 is configured to perform digital-to-analog conversion on the count values represented by the plurality of count clocks based on the first reference voltage VA and the second reference voltage VB to generate the reference voltage.
Further, the level state of the last stage selection signal of the plurality of selection signals received by the counter 300 is adjustable in each counting period of the counter 300 (i.e., the counter 300 completes one counting turn).
Further, the level state of each of the plurality of selection signals received by the counter 300 is adjustable in each counting period (i.e., the counter 300 completes one counting round).
In this embodiment, the selection module 200 is constructed by a plurality of cascaded selectors. The selection end of each selector in the cascaded selectors receives a corresponding selection signal, the input end of the first-stage selector receives part of the sub-clock signals, the input ends of the second-stage selector to the last-stage selector respectively receive at least one of the other part of the sub-clock signals and the output signal of the previous-stage selector, and further, the selection output of the sub-clock signals is realized based on the selection signals, wherein the output end of the last-stage selector is the output end of the selection module 200. At this time, the selection signal received by the last selector in the cascaded selectors corresponds to the last selection signal.
Alternatively, the selection signals received by the selection module 200 may be externally and separately provided signals, so as to enhance the gating effect on the plurality of sub-clock signals. While also serving as a portion of the multiple count clocks provided by subsequent counters 300 to achieve adaptive adjustment.
On the other hand, in other embodiments of the present invention, an entire one-out-of-many selection switch having a plurality of inputs (the number of inputs is greater than or equal to the number of sub-clock signals generated by the frequency divider 100) and communicating one of the outputs and the plurality of inputs based on one or more selection signals may be used as the selection module 200. Then each of the one or more select signals received by the one-out-of-many select switch may be the last stage select signal at this time.
In this embodiment, the input end of the counter 300 is connected to the output end of the selection module 200, and further receives one of the plurality of sub-clock signals selected and output by the selection module 200 as a basic clock for counting, and finally generates a plurality of counting clocks based on the basic clock, so as to count according to different level states of the plurality of counting clocks.
Accordingly, it can be understood that the change amplitude of the count value of the counter 300 during stepping, i.e. the time required for each increment of the count value by one unit, corresponds to the clock period of the basic clock received by the counter 300, i.e. the sub-clock signals selected and output by the selection module 200 are different, and the change amplitude of the count value of the counter 300 during stepping is also different. Therefore, by adjusting the clock period of the sub-clock signal selected and output by the selection module 200, the adjustment of the change amplitude of the count value of the counter 300 can be correspondingly achieved.
It should be noted that, the number of the output terminals of the counter 300, i.e. the number of the generated counting clocks, is directly proportional to the stepping precision of the reference voltage Vref along with the time, that is, if the precision requirement of the corresponding reference voltage Vref is high, the counter 300 with a large number of output terminals can be selected to meet the requirement of high precision; if the accuracy requirement of the corresponding reference voltage Vref is low, the counter 300 with relatively less output terminals can be selected to save circuit area and cost. And correspondingly, the counter with more output ends can be directly selected, and the number of the output ends which are actually and effectively connected into the circuit is selected as required only when the circuit is connected. The present disclosure does not specifically limit this, and actually, the corresponding selection may be performed according to different application scenarios.
In this embodiment, the digital-to-analog converter 400 performs digital-to-analog conversion on the count value of the counter 300 based on the first reference voltage VA and the second reference voltage VB, and when the counter 300 continuously counts within a counting period based on the base clock, the digital-to-analog converter 400 may perform digital-to-analog conversion on the continuous count value to obtain a continuous voltage curve (a curve described herein includes a straight line and a broken line) that changes with time, where the voltage curve is a voltage curve of the reference voltage Vref with time.
The digital-to-analog converter 400 includes: a first branch and a plurality of second branches. The first branch circuit comprises a plurality of second resistors and a plurality of first resistors which are connected between the input end of the first reference voltage VA and the output end of the reference voltage Vref in series. Each of the plurality of second branches includes: the first input end of the selection switch is connected with the input end of a first reference voltage VA, and the second input end of the selection switch is connected with the input end of a second reference voltage VB; and the second resistors are connected between the first branch circuit and the output end of the selection switch. A plurality of selection switches (each of the second branches includes a selection switch) on the plurality of second branches correspond to a plurality of counting clocks output by the receiving counter 300 (that is, each of the selection switches corresponds to receiving one counting clock), and a first resistor is included between connection nodes of any two adjacent second branches and the first branch.
It is understood that the number of the second branches in the digital-to-analog converter 400 is equal to the number of the counting clocks output by the counter 300, and the number of the selection switches.
Optionally, the selection switch on each second branch includes, but is not limited to, an alternative selection switch or a relay, etc.
Optionally, in the first embodiment of the present disclosure, each second branch includes one second resistor, and the resistance value of the second resistor on each second branch is twice the resistance value of the first resistor. At this time, if the resistance value of the first resistor is R, the resistance value of the second resistor is 2R. Therefore, only one resistor needs to be connected in series on each second branch, which is beneficial to saving the area of the step map.
Optionally, in the first embodiment of the present disclosure, each second branch includes two second resistors connected in series, and a resistance value of each second resistor on each second branch is equal to a resistance value of the first resistor. At this time, if the resistance value of the first resistor is R, the resistance value of the second resistor is also R. Thus, since the resistors with the same resistance are adopted in the digital-to-analog converter 400, the specifications of the resistors can be unified, and the influence of the resistance difference of the resistors with different specifications on the performance of the digital-to-analog converter 400 is avoided.
Based on the operating principle of the digital-to-analog converter, it can be known that the purpose of changing the slope of the output voltage curve can be achieved by changing the variation range and/or the reference value (corresponding to the voltage values of the first reference voltage VA and the second reference voltage VB herein) of the value to be converted (corresponding to the count value output by the counter 300 herein) received by the digital-to-analog converter 400. Furthermore, in the present disclosure, in different time periods in one counting period of the counter 300, or the level states of a plurality of selection signals received by the selection module 200 are set to be adjustable, so as to adjust the clock period of the sub-clock signal selected and output by the selection module 200, thereby achieving adjustment of the variation amplitude of the counting value of the counter 300, and further finally generating a reference voltage Vref curve with an adjustable slope, thereby achieving non-linear increase of the reference voltage Vref with time in one counting period of the counter 300.
For example, only the divider 100 generates three sub-clock signals (including the first sub-clock signal C <0>, the second sub-clock signal C <1>, and the third sub-clock signal C <2>), the cascaded selectors in the selection module 200 are two-out-of-one selectors, and the counter 300 is selected to output 9 counting clocks. It is assumed that the clock period Tclk of the initial clock signal CLK is 1us, the clock periods of the three sub-clock signals generated after frequency division are TC <0> -Tclk-1 us, TC <1> -2 us, and TC <2> -4 us, respectively.
Further, in this example, since all the selectors cascaded in the selection module 200 are either an alternative selector, the selection module 200 may be configured to include the first selector 210 and the second selector 220. Wherein the input terminal of the first selector 210 receives a first part of the sub-clock signals, and the output terminal of the first selector 210 selects and outputs one of the first part of the sub-clock signals based on a first selection signal D <7> of the plurality of selection signals. The input terminal of the second selector 220 receives a second part of the sub-clock signals of the plurality of sub-clock signals and the output signal of the first selector 210, and the output terminal of the second selector 220 selects one of the second part of the sub-clock signals to be output or the output signal of the first selector 210 to be output based on a second selection signal D <8> of the plurality of selection signals. Wherein the second selection signal D <8> is the last stage selection signal of the plurality of selection signals. Specifically, the first input terminal a of the first selector 210 receives the first sub-clock signal C <0>, the second input terminal B of the first selector 210 receives the second sub-clock signal C <1>, and the select terminal sel of the first selector 210 receives the first select signal D <7 >. Meanwhile, the first input terminal a of the second selector 220 receives the output signal of the first selector 210, the second input terminal B of the second selector 220 receives the third sub-clock signal C <2>, and the select terminal sel of the second selector 220 receives the second select signal D <8 >.
In this example, the plurality of count clocks (denoted as D <0:8>) output by the counter 300 includes, for example: the clock signal generator comprises a first counting clock D <0>, a second counting clock D <1>, a third counting clock D <2>, a fourth counting clock D <3>, a fifth counting clock D <4>, a sixth counting clock D <5>, a seventh counting clock D <6>, an eighth counting clock D <7> and a ninth counting clock D <8 >. Further, 512 groups of control signals within 111111111-000000000 can be output. Meanwhile, the eighth counting clock D <7> and the ninth counting clock D <8> are selected as the selection signals of the first selection switch 210 and the second selection switch 220 in the selection module 200, respectively.
In this example, referring to fig. 3, fig. 3 shows a schematic diagram of an internal circuit structure of the digital-to-analog converter in fig. 2, wherein the digital-to-analog converter 400 has 9 second branches, and a plurality of selection switches (e.g. including S0, S1, S2,. -, S8) in the 9 second branches respectively correspond to the first count clock D <0>, the second count clock D <1>, the third count clock D <2>, the fourth count clock D <3>, the fifth count clock D <4>, the sixth count clock D <5>, the seventh count clock D <6>, the eighth count clock D <7> and the ninth count clock D <8> output by the receiving counter 300 as respective control signals, so as to control the reference voltage Vref 512 to change from VA to VB in steps. It is understood that the sub-clock signals selected by the counter 300 are different, and the clock periods of the plurality of corresponding counting clocks D <0> to D <8> are also different.
It is assumed in this example that the first selector 210 and the second selector 220 each select a signal transmission path communicating between the first input terminal a and the output terminal when the received selection signal is high (or corresponding to logic 1), and select a signal transmission path communicating between the second input terminal B and the output terminal when the received selection signal is low (or corresponding to logic 0). Then, in different time periods, when D <7> is high and D <8> is high, the selection module 200 selects to output the first sub-clock signal C <0> to the input terminal of the counter 300, and at this time, the clock period TD <0> -TC <0> -1 us of the first counting clock D <0> output by the counter 300. When D <7> is low and D <8> is high, the selection module 200 selects to output the second sub-clock signal C <1> to the input terminal of the counter 300, and at this time, the clock period TD <0> -TC <1> -2 us of the first counting clock D <0> output by the counter 300. When D <8> is low, the selection module 200 selects to output the third sub-clock signal C <2> to the input terminal of the counter 300, and at this time, the clock period TD <0> -TC <2> -4 us of the first counting clock D <0> output by the counter 300. Further, the clock cycles of the other count clocks outputted from the counter 300 are different from each other in different periods corresponding to different level states of D <7> and D <8 >.
Meanwhile, in this example, it is assumed that each of the selection switches in the digital-to-analog converter 400 selects to output the first reference voltage VA to the corresponding node of the first branch when the received control signal is at a high level (or corresponds to a logic 1), and selects to output the second reference voltage VB to the corresponding node of the first branch when the received control signal is at a low level (or corresponds to a logic 0). Further, as can be seen from FIG. 3:
in the initial state of the counter 300 (corresponding to time t ═ 0 us): d <8:0> -111111111, Vref-VA.
In the next state of the counter 300 (corresponding to time t ═ 0.5 us): d <8:0> -111111110, Vref-VA + VB + 1/2^ 9.
In the final state of the counter 300 (corresponding to time t ═ 704 us): d <8:0> -0000000000 and Vref-VB.
If VA is 0V and VB is 2V, the corresponding:
in the initial state of the counter 300 (corresponding to time t ═ 0 us): d <8:0> -111111111, Vref-0V.
In the next state of the counter 300 (corresponding to time t ═ 0.5 us): d <8:0> -111111110, Vref-2 x 1/2^ 9V.
In the final state of the counter 300 (corresponding to time t ═ 704 us): d <8:0> -0000000000 and Vref-2V.
Further, a graph of the reference voltage with time is obtained as shown in fig. 4. It should be noted that the waveform diagrams of the count clocks D <0> to D <8> are basic counter output waveforms, and in fig. 4, only some of the waveform diagrams of the count clocks, for example, D <6> to D <8>, are shown for the sake of easy understanding, but this does not affect the understanding of the present embodiment.
Referring to fig. 4, based on the level state changes of the eighth counting clock D <7> and the ninth counting clock D <8> during the counting process, the process of the reference voltage Vref changing from VA to VB, i.e., one counting period of the counter 300, may be divided into a plurality of different time periods. In each period, the slope of the rise of the reference voltage Vref is different depending on the level state change of the ninth count clock D <8>, or the level state change of the eighth count clock D <7> and the ninth count clock D <8 >. If in the first time period, the selection module 200 selects to output the first sub-clock signal C <0>, and further the basic timing period of the counter 300 is 1us, and the corresponding time t is 0-64 us, the reference voltage Vref will rise from 0V to 0.5V (the variation of the reference voltage Vref is 2 x 2 a 6/2 a 9), and at this time, the slope K1 is 0.5/64 (V/us); in the second time period, the selection module 200 selects to output the second sub-clock signal C <1>, the basic timing period of the counter 300 is 2us, the corresponding time t is 64-192 us, the reference voltage Vref rises from 0.5V to 1V (the variation of the reference voltage Vref is 2 x 2 a 7/2 a 9), and the slope K1 is 0.5/128 (V/us); in the third time period, the selection module 200 selects the third sub-clock signal C <2>, the basic timing period of the counter 300 is 4us, the corresponding time t is 192-704 us, the reference voltage Vref increases from 1V to 2V (the variation of the reference voltage Vref is 2 × 2 8/2^9), and the slope K1 is 1/512 (V/us).
As can be seen from the above data, the base timing period of the counter 300 is different for different time periods, and the rising slope of the reference voltage Vref is different, for example, K1-2 × K2-4 × K3. Thus, in the present disclosure, by adjusting the control timing of the selection signal received by the selection module 200, different sub-clock signals are output, and the non-linear increase of the reference voltage with time can be realized.
It should be understood that the number of sub-clock signals generated by the divider 100 and the corresponding clock period of each sub-clock signal are not limited herein, which is only an exemplary illustration. In different application scenarios, a suitable initial clock signal can be selected according to the actual waveform requirement for the reference voltage Vref to perform different frequency division, and a plurality of sub-clock signals with different periods are correspondingly generated. Correspondingly, when the number of the sub-clock signals generated by the frequency divider 100 is greater than 3, the number of the cascaded two-out selection switches included in the selection module 200 should be correspondingly increased to meet the design requirement of the frequency divider 100, and each two-out selection switch receives a selection signal. On the other hand, in other embodiments of the present invention, if a whole one-of-many selection switch having a plurality of input terminals (the number of input terminals is greater than or equal to the number of sub-clock signals generated by the frequency divider 100) that can communicate the output terminal thereof with one of the plurality of input terminals based on one or more selection signals is selected as the selection module 200, it is within the scope of the present disclosure. On the other hand, the control timing of the selection signal received by the selection module 200 and/or the number of the counting clocks output by the counter 300 may also be selected according to actual requirements, so as to meet the requirements for different rising slopes of the reference voltage, which is not limited in this disclosure.
Fig. 5 shows a block flow diagram of a method for generating a reference voltage provided according to an embodiment of the present disclosure.
As shown in fig. 5, in the present embodiment, the method for generating the reference voltage includes performing steps S1 to S2.
In step S1, a plurality of counting clocks are generated based on the initial clock signal and a plurality of selection signals.
In this embodiment, generating a plurality of count clocks based on the initial clock signal and the plurality of selection signals includes: generating a plurality of sub-clock signals having different clock periods based on an initial clock; selecting and outputting one of a plurality of sub-clock signals based on a plurality of selection signals; counting is performed based on the sub-clock signals selectively output, and a plurality of count clocks are generated.
In step S2, count values represented by the plurality of count clocks are digital-to-analog converted based on the first reference voltage and the second reference voltage, and a reference voltage is generated.
Further, in this embodiment, in the same counting period corresponding to the plurality of counting clocks, the level state of the last stage selection signal in the plurality of selection signals is adjustable.
Furthermore, the level state of each of the plurality of selection signals is adjustable in the same counting period corresponding to the plurality of counting clocks.
That is, in the same counting period corresponding to a plurality of counting clocks (wherein, one counting period corresponds to one change process of the reference voltage from the first reference voltage to the second reference voltage), the level states of a plurality of selection signals are adjusted as required in different time periods of the same counting period, and then the time required by the rising unit voltage value in the rising process of the reference voltage in different time periods is adjusted, so that the control of the rising slope of the reference voltage can be realized, and the nonlinear increase of the reference voltage along with the time can be realized.
In summary, in the process of generating the reference voltage, since the level state of the last stage selection signal in the plurality of selection signals in the same counting period of the counter is adjustable, and further by adjusting the level state of the selection signal, the clock period of the basic clock when the counter counts in different time periods of a counting period can be changed, so as to adjust the clock periods of the plurality of counting clocks output by the counter, thereby changing the time required by the counter for stepping the unit counting value in the counting period, and finally obtaining the reference voltage curve with adjustable slope, thereby realizing the nonlinear increase of the reference voltage along with time. On the other hand, if the level state of the last stage selection signal in the plurality of selection signals is not adjusted in the same counting period of the counter, the linear increase of the reference voltage along with the time can be realized. The function of the reference voltage generating circuit is enhanced, and the applicability of the reference voltage generating circuit to different application scenes is improved. Meanwhile, devices adopted by the reference voltage generating circuit are conventional, the characteristics are good, and long-time utilization of the reference voltage is easy to realize.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (10)
1. A reference voltage generating circuit, comprising:
a frequency divider for dividing an initial clock signal to generate a plurality of sub-clock signals having different clock periods;
a selection module, connected to the frequency divider, for selecting one of the plurality of sub-clock signals based on a plurality of selection signals;
the counter is connected with the selection module and used for generating a plurality of counting clocks based on the output signal of the selection module;
a digital-to-analog converter connected to the counter and receiving a first reference voltage and a second reference voltage for performing digital-to-analog conversion on the count values represented by the plurality of count clocks based on the first reference voltage and the second reference voltage to generate a reference voltage,
and in the same counting period of the counter, the level state of the last stage of selection signals in the plurality of selection signals is adjustable.
2. The reference voltage generation circuit of claim 1 wherein the number of select signals is a fraction of the plurality of count clocks.
3. The reference voltage generation circuit of claim 2 wherein the selection module comprises:
the input end of the first selector receives a first part of sub-clock signals in the plurality of sub-clock signals, and the output end of the first selector selects and outputs one of the first part of sub-clock signals based on a first selection signal in the plurality of selection signals;
a second selector, the input end receives a second part of sub-clock signals in the plurality of sub-clock signals and the output signal of the first selector, the output end selects and outputs one of the second part of sub-clock signals or the output signal of the first selector based on a second selection signal in the plurality of selection signals,
wherein the second selection signal is a last stage selection signal among the plurality of selection signals.
4. The reference voltage generating circuit according to claim 1, wherein a level state of each of the plurality of selection signals is adjustable in a same counting period of the counter.
5. The reference voltage generating circuit of claim 1, wherein the digital-to-analog converter comprises:
the first branch circuit comprises a plurality of second resistors and a plurality of first resistors which are connected in series between a first reference voltage input end and a reference voltage output end;
a plurality of second branches, each second branch comprising:
the first input end of the selection switch is connected with the first reference voltage input end, and the second input end of the selection switch is connected with the second reference voltage input end;
a plurality of second resistors connected between the first branch and the output end of the selection switch,
the plurality of selection switches on the plurality of second branches correspondingly receive the plurality of counting clocks, and a first resistor is arranged between the connection nodes of any two adjacent second branches and the first branch.
6. The reference voltage generating circuit according to claim 5, wherein each second branch comprises a second resistor, and each second resistor has a resistance value twice that of the first resistor.
7. The reference voltage generating circuit according to claim 5, wherein each second branch includes two second resistors connected in series, and each of the second resistors has a resistance equal to that of the first resistor.
8. A method for generating a reference voltage, comprising:
generating a plurality of count clocks based on an initial clock signal and a number of select signals;
performing digital-to-analog conversion on the count values represented by the plurality of count clocks based on a first reference voltage and a second reference voltage to generate a reference voltage,
and in the same counting period corresponding to the plurality of counting clocks, the level state of the last stage of selection signals in the plurality of selection signals can be adjusted.
9. The reference voltage generation method of claim 8, wherein generating a plurality of count clocks based on an initial clock signal and a number of selection signals comprises:
generating a plurality of sub-clock signals having different clock periods based on an initial clock;
selecting one of the plurality of sub-clock signals to be output based on the plurality of selection signals;
and counting based on the sub-clock signals which are selectively output, and generating the plurality of counting clocks.
10. The method according to claim 8, wherein the level state of each of the plurality of selection signals is adjustable in the same counting period corresponding to the plurality of counting clocks.
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