CN114625194B - Reference voltage generating circuit and generating method thereof - Google Patents
Reference voltage generating circuit and generating method thereof Download PDFInfo
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- CN114625194B CN114625194B CN202011455243.6A CN202011455243A CN114625194B CN 114625194 B CN114625194 B CN 114625194B CN 202011455243 A CN202011455243 A CN 202011455243A CN 114625194 B CN114625194 B CN 114625194B
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
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Abstract
The invention discloses a reference voltage generating circuit and a generating method thereof, wherein the circuit comprises: a divider for dividing the initial clock signal to generate a plurality of sub-clock signals having different clock cycles; a selection module for selecting one of the plurality of sub-clock signals based on a plurality of selection signals; a counter for generating a plurality of count clocks based on an output signal of the selection module; the digital-to-analog converter is used for carrying out digital-to-analog conversion on count values represented by a plurality of count clocks based on the first reference voltage and the second reference voltage to generate reference voltages, wherein the level state of the last stage of selection signals in the plurality of selection signals has at least one jump in the same counting period of the counter. The reference voltage generating circuit and the reference voltage generating method can change the generation slope of the reference voltage, realize the nonlinear increase of the reference voltage along with time and improve the applicability of the circuit to different application scenes.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a reference voltage generating circuit and a method for generating the same.
Background
In the circuit application field, there is a need for reference voltage supply, and a common solution is shown in fig. 1a, fig. 1a shows a schematic circuit structure of a conventional reference voltage generating circuit, and a reference voltage Vref is obtained at an intermediate node between a current source i and a capacitor C by connecting the current source i and the capacitor C in series between a power source terminal VDD and a reference ground.
However, as shown in fig. 1b, fig. 1b shows a schematic diagram of the reference voltage of fig. 1a with time, and the reference voltage Vref generated by the circuit is linear with time, which cannot meet the application requirement of different slopes. Meanwhile, based on the circuit structure, if the reference voltage Vref is to be utilized for a long period of time, the current provided by the current source i is required to be particularly small, or the capacitance value of the capacitor C is particularly large, which is not easy to realize.
Accordingly, there is a need to provide an improved solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a reference voltage generating circuit and a generating method thereof, which can change the generating slope of the reference voltage, realize the nonlinear increase of the reference voltage along with time and improve the applicability of the circuit to different application scenes.
According to a first aspect, the present invention provides a reference voltage generating circuit, comprising: a divider for dividing the initial clock signal to generate a plurality of sub-clock signals having different clock cycles;
a selection module connected with the frequency divider and used for selecting and outputting one of the plurality of sub-clock signals based on a plurality of selection signals;
the counter is connected with the selection module and used for generating a plurality of counting clocks based on the output signals of the selection module;
A digital-to-analog converter connected with the counter and receiving a first reference voltage and a second reference voltage for performing digital-to-analog conversion on count values characterized by the plurality of count clocks based on the first reference voltage and the second reference voltage to generate a reference voltage,
And in the same counting period of the counter, the level state of the last stage of selection signals in the plurality of selection signals is adjustable.
Optionally, the number of selection signals are part of the plurality of count clocks.
Optionally, the selecting module includes:
A first selector, the input end of which receives a first part of the sub-clock signals, and the output end of which selects and outputs one of the first part of the sub-clock signals based on a first selection signal of the plurality of selection signals;
A second selector, the input end of which receives a second part of the sub-clock signals and the output signals of the first selector, the output end selects one of the second part of the sub-clock signals to be output or selects the output signals of the first selector to be output based on the second selection signals of the plurality of selection signals,
Wherein the second selection signal is the last stage selection signal in the plurality of selection signals.
Optionally, the level state of each of the plurality of selection signals is adjustable within the same counting period of the counter.
Optionally, the digital-to-analog converter includes:
the first branch circuit comprises a plurality of second resistors and a plurality of first resistors which are connected in series between a first reference voltage input end and a reference voltage output end;
A plurality of second branches, each second branch comprising:
the first input end of the selection switch is connected with the first reference voltage input end, and the second input end of the selection switch is connected with the second reference voltage input end;
a plurality of second resistors connected between the first branch and the output end of the selection switch,
The plurality of selection switches on the plurality of second branches correspondingly receive the plurality of counting clocks, and a first resistor is arranged between any two adjacent second branches and the connection node of the first branch.
Optionally, each second branch includes a second resistor, and a resistance value of each second resistor is twice that of the first resistor.
Optionally, each second branch circuit includes two second resistors connected in series, and a resistance value of each second resistor is equal to a resistance value of the first resistor.
In a second aspect, the present invention provides a method for generating a reference voltage, including:
Generating a plurality of count clocks based on the initial clock signal and the plurality of select signals;
Performing digital-to-analog conversion on count values characterized by the plurality of count clocks based on the first reference voltage and the second reference voltage to generate reference voltages,
And in the same counting period corresponding to the counting clocks, the level state of the last stage of the selecting signals in the plurality of selecting signals is adjustable.
Optionally, generating the plurality of count clocks based on the initial clock signal and the plurality of select signals includes:
generating a plurality of sub-clock signals having different clock cycles based on an initial clock;
selecting one of the plurality of sub-clock signals to output based on the plurality of selection signals;
the plurality of count clocks are generated based on counting the sub-clock signals selected to be output.
Optionally, in the same counting period corresponding to the plurality of counting clocks, a level state of each of the plurality of selection signals is adjustable.
The beneficial effects of the invention are as follows: the present disclosure relates to a reference voltage generating circuit and a method thereof, which employ a counter and a digital-to-analog converter to generate one reference voltage having different slopes in different time periods. In the process of generating the reference voltage, the level state of the last stage of selection signals in a plurality of selection signals in the same counting period of the counter is adjustable, so that the clock period of a time-based clock in the counting of the counter in different time periods of one counting period can be changed by adjusting the level state of the selection signals, the adjustment of the clock periods of a plurality of counting clocks output by the counter is realized, the time required by the counter when the unit counting value in the same counting period is stepped is changed, a reference voltage curve with adjustable slope is finally obtained, the nonlinear increase of the reference voltage along with time is realized, and the reference voltage with different slopes in different time periods of the same counting period is generated. On the other hand, if the level state of the last stage of the selection signals in the plurality of selection signals is not adjusted in the same counting period of the counter, the linear increase of the reference voltage along with the time can be realized. The function of the reference voltage generating circuit is enhanced, and the applicability of the reference voltage generating circuit to different application scenes is also improved. Meanwhile, the devices adopted by the reference voltage generating circuit are conventional, have good characteristics and are easy to realize long-time utilization of the reference voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.
FIG. 1a is a schematic diagram showing a circuit configuration of a conventional reference voltage generating circuit;
FIG. 1b is a graph showing the reference voltage of FIG. 1a as a function of time;
fig. 2 illustrates a schematic diagram of a reference voltage generation circuit provided according to an embodiment of the present disclosure;
FIG. 3 shows a schematic diagram of the internal circuit structure of the digital-to-analog converter of FIG. 2;
FIG. 4 is a graph showing reference voltage versus time provided in accordance with an embodiment of the present disclosure;
Fig. 5 shows a flow chart diagram of a method of generating a reference voltage provided in accordance with an embodiment of the present disclosure.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail with reference to the accompanying drawings.
Fig. 2 illustrates a schematic diagram of a reference voltage generation circuit provided according to an embodiment of the present disclosure.
As shown in fig. 2, in the embodiment of the present disclosure, a reference voltage generating circuit includes: divider 100, selection module 200, counter 300, and digital-to-analog converter 400. The input end of the frequency divider 100 receives the initial clock signal CLK, and the output end of the frequency divider 100 is connected to the input end of the selection module 200. The selection module 200 also receives a number of selection signals, and the output of the selection module 200 is connected to the input of the counter 300. An output of the counter 300 is connected to a first input of the digital-to-analog converter 400. The second input terminal and the third input terminal of the digital-to-analog converter 400 respectively receive the first reference voltage VA and the second reference voltage VB, and the output terminal of the digital-to-analog converter 300 outputs the reference voltage Vref.
In the present embodiment, the frequency divider 100 is configured to divide the initial clock signal CLK to generate a plurality of sub-clock signals having different clock cycles. The selection module 200 is configured to select one of the plurality of sub-clock signals based on a plurality of selection signals. The counter 300 is used to generate a plurality of count clocks based on the output signal of the selection module 200. And the digital-to-analog converter 400 is configured to perform digital-to-analog conversion on count values characterized by the plurality of count clocks based on the first reference voltage VA and the second reference voltage VB, so as to generate a reference voltage.
Further, the level state of the last stage of the selection signals in the plurality of selection signals received by the counter 300 is adjustable in each counting period of the counter 300 (i.e. the counter 300 completes one counting round).
Further, the level state of each of the plurality of selection signals received by the counter 300 is adjustable during each counting period of the counter 300 (i.e. the counter 300 completes one counting cycle).
In this embodiment, the selection module 200 is constructed from a plurality of cascaded selectors. The selection end of each selector in the plurality of cascaded selectors receives a corresponding selection signal, while the input end of the first-stage selector receives part of sub-clock signals in the plurality of sub-clock signals, the input ends of the second-stage selector to the last-stage selector respectively receive at least one of the other sub-clock signals in the plurality of sub-clock signals, and the output signal of the previous-stage selector, so that the selection output of the plurality of sub-clock signals is realized based on the plurality of selection signals, wherein the output end of the last-stage selector is the output end of the selection module 200. At this time, the selection signal received by the last selector in the plurality of cascaded selectors corresponds to the last selection signal.
Alternatively, the plurality of selection signals received by the selection module 200 may be signals separately provided from the outside, so as to enhance the gating effect on the plurality of sub-clock signals. While also serving as part of the multiple count clocks provided by the subsequent counter 300 to enable adaptive adjustment.
Alternatively, in other embodiments of the present invention, a plurality of inputs (the number of inputs is greater than or equal to the number of sub-clock signals generated by the frequency divider 100) may be used as the selection module 200, and an entire one-out-of-multiple selection switch may be used to connect the output thereof to one of the plurality of inputs based on one or more selection signals. Then each of the one or more select signals received by the one-to-many select switch may be the last stage select signal.
In this embodiment, the input end of the counter 300 is connected to the output end of the selection module 200, so as to receive one of the plurality of sub-clock signals selected and output by the selection module 200 as a base clock during counting, and finally generate a plurality of counting clocks based on the base clock, so as to count according to different level states of the plurality of counting clocks.
It will be understood that the change width of the count value of the counter 300 during stepping, that is, the time required for increasing the count value by one unit corresponds to the clock period of the base clock received by the counter 300, that is, the sub-clock signal selected by the selection module 200 to be output is different, and the change width of the count value of the counter 300 during stepping is also different. Therefore, by adjusting the clock period of the sub-clock signal selected and outputted by the selection module 200, the adjustment of the variation amplitude of the count value of the counter 300 can be correspondingly achieved.
It should be noted that, the number of output ends of the counter 300, that is, the number of count clocks generated by the counter is proportional to the step precision of the reference voltage Vref along with time, that is, if the precision requirement of the corresponding reference voltage Vref is higher, the counter 300 with a larger number of output ends can be selected to meet the requirement of high precision; if the accuracy requirement for the reference voltage Vref is low, a counter 300 with a relatively small number of outputs can be selected to save circuit area and cost. And correspondingly, the counter with more output ends can be directly selected, and the number of the output ends in the actually effective access circuit is selected according to the requirement only when circuit connection is carried out. The present disclosure does not specifically limit this, and in practice, the selection may be performed according to different application scenarios.
In this embodiment, the digital-to-analog converter 400 performs digital-to-analog conversion on the count value of the counter 300 based on the first reference voltage VA and the second reference voltage VB, and when the counter 300 continuously counts in a counting period based on the base clock, the digital-to-analog converter 400 can obtain a continuous voltage curve (the curve described herein includes a special curve such as a straight line and a broken line) that changes with time after performing digital-to-analog conversion on the continuous count value, and the voltage curve is a voltage change curve of the reference voltage Vref with time.
The digital-to-analog converter 400 includes: a first leg and a plurality of second legs. The first branch circuit comprises a plurality of second resistors and a plurality of first resistors which are connected in series between the input end of the first reference voltage VA and the output end of the reference voltage Vref. Each of the plurality of second branches includes: the first input end of the selection switch is connected with the input end of the first reference voltage VA, and the second input end of the selection switch is connected with the input end of the second reference voltage VB; the second resistors are connected between the first branch and the output end of the selection switch. The plurality of selection switches on the plurality of second branches (each of the second branches includes a selection switch) corresponds to a plurality of counting clocks output by the receiving counter 300 (i.e., each of the selection switches corresponds to receiving a counting clock), and a first resistor is included between any two adjacent connection nodes between the second branches and the first branch.
It will be appreciated that the number of second branches in the digital-to-analog converter 400 is equal to the number of counting clocks output by the counter 300 and the number of selection switches.
Optionally, the selection switch on each second branch includes, but is not limited to, a two-out selection switch or a relay, etc.
Optionally, in a first embodiment of the present disclosure, each second branch includes a second resistor, and a resistance value of the second resistor on each second branch is twice a resistance value of the first resistor. At this time, if the resistance of the first resistor is R, the resistance of the second resistor is 2R. Therefore, only one resistor is connected in series on each second branch, so that the area of the step diagram is saved.
Optionally, in the first embodiment of the present disclosure, each second branch includes two second resistors connected in series, and a resistance value of each second resistor on each second branch is equal to a resistance value of the first resistor. At this time, if the resistance of the first resistor is R, the resistance of the second resistor is R. In this way, the digital-to-analog converter 400 adopts the resistors with the same resistance value, so that the specifications of the resistors can be unified, and the influence of the resistance differences of the resistors with different specifications on the performance of the digital-to-analog converter 400 is avoided.
Based on the working principle of the digital-to-analog converter, it can be known that the purpose of changing the slope of the voltage curve output by the digital-to-analog converter 400 can be achieved by changing the variation amplitude and/or the reference value (the voltage value corresponding to the first reference voltage VA and the second reference voltage VB) of the value to be converted (corresponding to the count value output by the counter 300). Furthermore, in the present disclosure, in different time periods in one counting period of the counter 300, or the level states of a plurality of selection signals received by the selection module 200 are set to be adjustable, so as to adjust the clock period of the sub-clock signal selected and output by the selection module 200, thereby adjusting the variation amplitude of the count value of the counter 300, and further generating a reference voltage Vref curve with an adjustable slope, so as to achieve nonlinear increase of the reference voltage Vref with time in one counting period of the counter 300.
For example, only three sub-clock signals (including the first sub-clock signal C <0>, the second sub-clock signal C <1> and the third sub-clock signal C <2 >) generated by the frequency divider 100, and the cascaded selector in the selection module 200 are two-out-of-one selectors, and the counter 300 is selected to output 9 count clocks are described herein. Here, assume that the clock period tclk=1us of the initial clock signal CLK, the clock periods of the three sub-clock signals generated after frequency division are TC <0> =tclk=1us, TC <1> =2us, TC <2> =4us, respectively.
Further, in this example, since the selectors cascaded in the selection module 200 are both one-out-of-two selectors, the selection module 200 may be configured to include the first selector 210 and the second selector 220. The input terminal of the first selector 210 receives a first partial sub-clock signal of the plurality of sub-clock signals, and the output terminal of the first selector 210 selects and outputs one of the first partial sub-clock signals based on a first selection signal D <7> of the plurality of selection signals. The input terminal of the second selector 220 receives a second partial sub-clock signal of the plurality of sub-clock signals and the output signal of the first selector 210, and the output terminal of the second selector 220 selects one of the second partial sub-clock signals to be output or selects the output signal of the first selector 210 to be output based on a second selection signal D <8> of the plurality of selection signals. The second selection signal D <8> is the last stage selection signal in a plurality of selection signals. Specifically, the first input terminal A of the first selector 210 receives the first sub-clock signal C <0>, the second input terminal B of the first selector 210 receives the second sub-clock signal C <1>, and the select terminal sel of the first selector 210 receives the first select signal D <7>. Meanwhile, the first input terminal a of the second selector 220 receives the output signal of the first selector 210, the second input terminal B of the second selector 220 receives the third sub-clock signal C <2>, and the select terminal sel of the second selector 220 receives the second select signal D <8>.
In this example, the plurality of count clocks (denoted as D <0:8 >) output by the counter 300 include: the first count clock D <0>, the second count clock D <1>, the third count clock D <2>, the fourth count clock D <3>, the fifth count clock D <4>, the sixth count clock D <5>, the seventh count clock D <6>, the eighth count clock D <7> and the ninth count clock D <8>. And further, 512 groups of control signals in 111111111 ～ 000000000 can be output. Meanwhile, the eighth count clock D <7> and the ninth count clock D <8> are selected as the selection signals of the first selection switch 210 and the second selection switch 220 in the selection module 200, respectively.
In this example, referring to fig. 3, fig. 3 shows a schematic internal circuit structure of the digital-to-analog converter in fig. 2, wherein the digital-to-analog converter 400 has 9 second branches, and a plurality of selection switches (e.g., including S0, S1, S2, and S8) in the 9 second branches correspond to the first count clock D <0>, the second count clock D <1>, the third count clock D <2>, the fourth count clock D <3>, the fifth count clock D <4>, the sixth count clock D <5>, the seventh count clock D <6>, the eighth count clock D <7>, and the ninth count clock D <8>, respectively, outputted from the reception counter 300, as respective control signals, so that the reference voltage Vref can be controlled to be changed from VA to VB in 512 steps. It is understood that the sub-clock signals selected by the counter 300 are different, and the clock periods of the corresponding counting clocks D <0> to D <8> are also different.
Assume in this example that the first selector 210 and the second selector 220 are both selecting a signal transmission path between the first input terminal a and the output terminal when the corresponding received selection signal is high (or corresponding to logic 1), and selecting a signal transmission path between the second input terminal B and the output terminal when the corresponding received selection signal is low (or corresponding to logic 0). Then, in a different period of time, when D <7> is high and D <8> is high, the selection module 200 selects to output the first sub-clock signal C <0> to the input terminal of the counter 300, and at this time, the clock period TD <0> =tc <0> =1us of the first count clock D <0> output by the counter 300. When D <7> is low and D <8> is high, the selection module 200 selects to output the second sub-clock signal C <1> to the input terminal of the counter 300, and the clock period TD <0> =tc <1> =2us of the first count clock D <0> output by the counter 300. When D <8> is at a low level, the selection module 200 selects and outputs the third sub-clock signal C <2> to the input terminal of the counter 300, and at this time, the clock period TD <0> =tc <2> =4us of the first count clock D <0> output by the counter 300. Further, the clock cycles of the other count clocks outputted from the counter 300 in different periods corresponding to different level states of D <7> and D <8> are also different from each other.
Meanwhile, it is assumed that in this example, each of the selection switches in the digital-to-analog converter 400 selects to output the first reference voltage VA to the corresponding node of the first branch when the corresponding received control signal is high (or corresponding to logic 1), and selects to output the second reference voltage VB to the corresponding node of the first branch when the corresponding received control signal is low (or corresponding to logic 0). Further, as can be seen from fig. 3:
In the initial state of the counter 300 (corresponding to time t=0us): d <8:0> =111111111, vref=va.
In the next state of the counter 300 (corresponding time t=0.5 us): d <8:0> =111111110, vref=va+vb×1/2^9.
At the final state of the counter 300 (corresponding time t=704 us): d <8:0> =0000000000, vref=vb.
If va=0v and vb=2v are assumed, then the corresponding:
in the initial state of the counter 300 (corresponding to time t=0us): d <8:0> =111111111, vref=0v.
In the next state of the counter 300 (corresponding time t=0.5 us): d <8:0> =111111110, vref= 2*1/2≡9v.
At the final state of the counter 300 (corresponding time t=704 us): d <8:0> =0000000000, vref=2v.
Further, a graph showing the reference voltage change with time as shown in fig. 4 was obtained. Note that, the waveforms of the count clocks D <0> to D <8> are basic counter output waveforms, and only a part of the waveforms of the count clocks D <6> to D <8> are shown in fig. 4 for the sake of understanding, but this does not affect the understanding of the present embodiment.
Referring to fig. 4, it can be seen that the process of changing the reference voltage Vref from VA to VB, i.e., one counting period of the counter 300, can be divided into a plurality of different time periods based on the level state change of the eighth counting clock D <7> and the ninth counting clock D <8> in the counting process. In each period, the slope of the rise of the reference voltage Vref is different based on the level state change of the ninth count clock D <8>, or based on the level state changes of the eighth count clock D <7> and the ninth count clock D <8 >. If the selection module 200 selects and outputs the first sub-clock signal C <0> in the first period, and the basic timing period of the counter 300 is 1us, corresponding to the time t=0-64 us, the reference voltage Vref will rise from 0V to 0.5V (the variation of the reference voltage vref=2×2≡6/2^9), and the slope k1=0.5/64 (V/us); in the second period, the selection module 200 selects and outputs the second sub-clock signal C <1>, and the basic timing period of the counter 300 is 2us, corresponding to time t=64-192 us), the reference voltage Vref will rise from 0.5V to 1V (the variation of the reference voltage vref=2×2++7/2^9), and the slope k1=0.5/128 (V/us); in the third period, the selection module 200 selects and outputs the third sub-clock signal C <2>, and the basic timing period of the counter 300 is 4us, corresponding to time t=192-704 us), the reference voltage Vref increases from 1V to 2V (the variation of the reference voltage vref=2x2ζ8/2^9), and the slope k1=1/512 (V/us).
As can be seen from the above data, the basic timing periods of the counter 300 corresponding to the different time periods are different, and thus the rising slopes of the reference voltage Vref are different, for example k1=2xk2=4xk3. Thus, in the present disclosure, by adjusting the control timing of the selection signal received by the selection module 200, different sub-clock signal outputs are realized, and nonlinear increase of the reference voltage with time can be realized.
It should be understood that the number of sub-clock signals generated by divider 100 and the clock period corresponding to each sub-clock signal are not limited in this context by way of example only. In different application scenarios, a proper initial clock signal can be selected to carry out different frequency division according to the actual waveform requirement of the reference voltage Vref, and a plurality of sub-clock signals with different periods are correspondingly generated. Correspondingly, when the number of sub-clock signals generated by the frequency divider 100 is greater than 3, the number of cascaded one-out-of-two selection switches included in the selection module 200 should be correspondingly increased to meet the design requirement of the frequency divider 100, and each one-out-of-two selection switch receives one selection signal. On the other hand, in other embodiments of the present invention, if a selection module 200 having a plurality of inputs (the number of inputs is greater than or equal to the number of sub-clock signals generated by the frequency divider 100) is selected, it is within the scope of the present disclosure to connect one or more selection switches with one of the plurality of inputs and one entire one-to-one selection switch based on one or more selection signals. In still another aspect, the control timing of the selection signal received by the selection module 200 and/or the number of counting clocks output by the counter 300 can be selected according to the actual requirement, so as to meet the different rising slope requirements of the reference voltage, which is not limited in the disclosure.
Fig. 5 shows a flow chart diagram of a method of generating a reference voltage provided in accordance with an embodiment of the present disclosure.
As shown in fig. 5, in the present embodiment, the reference voltage generating method includes performing steps S1 to S2.
In step S1, a plurality of count clocks are generated based on the initial clock signal and a plurality of selection signals.
In this embodiment, generating a plurality of count clocks based on an initial clock signal and a plurality of selection signals includes: generating a plurality of sub-clock signals having different clock cycles based on an initial clock; selecting one of the plurality of sub-clock signals to output based on a plurality of selection signals; a plurality of count clocks are generated by counting based on the sub-clock signals selected to be output.
In step S2, digital-to-analog conversion is performed on count values characterized by the plurality of count clocks based on the first reference voltage and the second reference voltage, and a reference voltage is generated.
Further, in this embodiment, in the same counting period corresponding to the plurality of counting clocks, the level state of the last stage of the plurality of selection signals is adjustable.
Furthermore, in the same counting period corresponding to the counting clocks, the level state of each of the plurality of selection signals is adjustable.
That is, in the same counting period corresponding to the plurality of counting clocks (wherein one counting period corresponds to one change process of the reference voltage from the first reference voltage to the second reference voltage), the level states of the plurality of selection signals are adjusted as required in different time periods of the same counting period, so that the time required for increasing the unit voltage value in the process of increasing the reference voltage in different time periods is adjusted, the control of the rising slope of the reference voltage can be realized, and the nonlinear increase of the reference voltage along with the time is realized.
In summary, in the process of generating the reference voltage, since the level state of the last stage of selection signals in a plurality of selection signals in the same counting period of the counter is adjustable, the clock period of the base clock during counting in different time periods of the counting period of the counter can be changed by adjusting the level state of the selection signals, and the adjustment of the clock periods of a plurality of counting clocks output by the counter is realized, so that the time required by the counter during stepping of the unit counting value in one counting period is changed, and finally, the reference voltage curve with adjustable slope is obtained, and the nonlinear increase of the reference voltage along with the time is realized. On the other hand, if the level state of the last stage of the selection signals in the plurality of selection signals is not adjusted in the same counting period of the counter, the linear increase of the reference voltage along with the time can be realized. The function of the reference voltage generating circuit is enhanced, and the applicability of the reference voltage generating circuit to different application scenes is also improved. Meanwhile, the devices adopted by the reference voltage generating circuit are conventional, have good characteristics and are easy to realize long-time utilization of the reference voltage.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it is apparent that the above examples are only illustrative of the present invention and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.
Claims (9)
1. A reference voltage generating circuit, comprising:
A divider for dividing the initial clock signal to generate a plurality of sub-clock signals having different clock cycles;
a selection module connected with the frequency divider and used for selecting and outputting one of the plurality of sub-clock signals based on a plurality of selection signals;
the counter is connected with the selection module and used for generating a plurality of counting clocks based on the output signals of the selection module, and the output signals of the selection module are used as a basic clock when the counter counts;
A digital-to-analog converter connected with the counter and receiving a first reference voltage and a second reference voltage for performing digital-to-analog conversion on count values characterized by the plurality of count clocks based on the first reference voltage and the second reference voltage to generate a reference voltage,
And in the same counting period of the counter, setting the level state of the last stage of selection signals in the plurality of selection signals to be adjustable so as to realize the adjustment of the clock period of the sub-clock signals selected and output by the selection module, thereby achieving the adjustment of the variation amplitude of the count value of the counter and generating a reference voltage curve with adjustable slope.
2. The reference voltage generation circuit of claim 1 wherein the number of select signals are part of the plurality of count clocks.
3. The reference voltage generation circuit of claim 2, wherein the selection module comprises:
A first selector, the input end of which receives a first part of the sub-clock signals, and the output end of which selects and outputs one of the first part of the sub-clock signals based on a first selection signal of the plurality of selection signals;
A second selector, the input end of which receives a second part of the sub-clock signals and the output signals of the first selector, the output end selects one of the second part of the sub-clock signals to be output or selects the output signals of the first selector to be output based on the second selection signals of the plurality of selection signals,
Wherein the second selection signal is the last stage selection signal in the plurality of selection signals.
4. The reference voltage generation circuit of claim 1 wherein the level state of each of the plurality of selection signals is adjustable within a same count period of the counter.
5. The reference voltage generation circuit of claim 1 wherein the digital-to-analog converter comprises:
the first branch circuit comprises a plurality of second resistors and a plurality of first resistors which are connected in series between a first reference voltage input end and a reference voltage output end;
A plurality of second branches, each second branch comprising:
the first input end of the selection switch is connected with the first reference voltage input end, and the second input end of the selection switch is connected with the second reference voltage input end;
a plurality of second resistors connected between the first branch and the output end of the selection switch,
The plurality of selection switches on the plurality of second branches correspondingly receive the plurality of counting clocks, and a first resistor is arranged between any two adjacent second branches and the connection node of the first branch.
6. The reference voltage generating circuit according to claim 5, wherein each of the second branches includes a second resistor, and a resistance value of each of the second resistors is twice a resistance value of the first resistor.
7. The reference voltage generation circuit of claim 5 wherein each second branch comprises two second resistors connected in series, each second resistor having a value equal to the value of the first resistor.
8. A method for generating a reference voltage, comprising:
Generating a plurality of count clocks based on the initial clock signal and the plurality of select signals;
Performing digital-to-analog conversion on count values characterized by the plurality of count clocks based on the first reference voltage and the second reference voltage to generate reference voltages,
Wherein generating a plurality of count clocks based on the initial clock signal and the plurality of select signals comprises:
generating a plurality of sub-clock signals having different clock cycles based on an initial clock;
selecting one of the plurality of sub-clock signals to output based on the plurality of selection signals;
Counting the selected output sub-clock signals as a base clock in counting, and generating a plurality of counting clocks;
and in the same counting period corresponding to the counting clocks, setting the level state of the last stage of the selection signals in the plurality of selection signals to be adjustable so as to realize the adjustment of the clock period of the sub-clock signal selected and output by the selection module, thereby achieving the adjustment of the variation amplitude of the counting value of the counter and generating a reference voltage curve with adjustable slope.
9. The method for generating a reference voltage according to claim 8, wherein a level state of each of the plurality of selection signals is adjustable in a same count period corresponding to the plurality of count clocks.
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