CN114582840A - MOM capacitor - Google Patents

Abstract

A MOM capacitor is disclosed, comprising: a substrate; a first conductive layer on the substrate, the first conductive layer is a conductive electrode plate; a second conductive layer on the first conductive layer, the second conductive layer includes a plurality of a first electrode strip and a second electrode strip separated from each other; a third conductive layer located on the second conductive layer, the third conductive layer being a conductive electrode plate; and a plurality of through holes for electrically connecting the first electrode strips to the first conductive layer and the third conductive layer to form a first electrode, a plurality of second electrode strips are electrically connected to form a second electrode, and the second electrode is opposite in polarity to the first electrode ; wherein, the first electrode strips and the second electrode strips are alternately arranged in a surrounding shape on the plane where the second conductive layer is located; the center of the plane where the second conductive layer is located is a plurality of second electrode strips. One, located at the edge of the plane where the second conductive layer is located is one of the plurality of first electrode strips.

Description

A MOM capacitor

technical field

The present invention relates to the technical field of semiconductors, in particular to a MOM capacitor.

Background technique

In the field of capacitor array structure, capacitor is a very important basic element. Metal-Oxide-Metal (MOM) capacitors and Metal-Insulator-Metal (MIM) capacitors are two common capacitor structures. MIM capacitors use metal patterns on the same layer or on different layers to form the same electrode, and the capacitance value is mainly composed of capacitors formed by different conductor layers. The MOM capacitor adopts the metal pattern of the same layer to form two electrodes with opposite polarities at the same time, so its capacitance value can include the capacitance formed by the same conductor layer.

Referring to FIG. 1, the MOM capacitor 100 includes a substrate 101 and a conductor layer M1. The conductor layer M1 includes two comb-shaped first electrodes 102 and second electrodes 103. The first electrodes and the second electrodes have opposite polarities. The electrode strips included in each of the comb-shaped structures are alternately arranged so that a capacitance is formed between the electrode strips of different electrodes, and the capacitance value of the capacitor 100 is equal to the sum of the capacitances formed by these electrode strips. This design of the MOM capacitor helps to increase the capacitance per unit area, thereby helping to reduce the area occupied by the MOM capacitor, which in turn helps improve the integration level of the semiconductor circuit. In order to increase the capacitance value, the MOM capacitor shown in Figure 1 can also be designed with a stacked layer, so that the total capacitance is mainly equal to the sum of the capacitance of the same layer, the capacitance between different layers, and the capacitance between each electrode strip and the through hole.

However, for a capacitor array with a large number of capacitors, the volume of the capacitor array is huge, so the MOM capacitor shown in FIG. 1 needs to be further improved to further reduce the volume of the capacitor.

SUMMARY OF THE INVENTION

In view of the above problems, the purpose of the present invention is to provide a MOM capacitor to improve the utilization rate of the capacitor area.

The present invention provides a MOM capacitor, comprising:

substrate;

a first conductive layer located on the substrate, the first conductive layer is a conductive electrode plate;

a second conductive layer on the first conductive layer, the second conductive layer including a plurality of first electrode strips and second electrode strips spaced apart from each other;

a third conductive layer on the second conductive layer, the third conductive layer is a conductive electrode plate; and

a plurality of through holes for electrically connecting the first electrode strips to the first conductive layer and the third conductive layer to form a first electrode, and the plurality of second electrode strips are electrically connected, forming a second electrode opposite in polarity to the first electrode; and

Wherein, the first electrode strips and the second electrode strips are alternately arranged in a surrounding shape on the plane where the second conductive layer is located; the center of the plane where the second conductive layer is located is among the plurality of second electrode strips One of the plurality of first electrode strips is located at the edge of the plane where the second conductive layer is located.

Preferably, the shapes of the first electrode strips and the second electrode strips are one or more of rectangles, circles, polygons or irregular shapes, so as to form a surrounding shape on the plane where the second conductive layer is located And the first electrode strips and the second electrode strips are alternately distributed.

Preferably, the second conductive layer further comprises third electrode strips for connecting the second electrode strips spaced apart from each other together;

the third electrode strip is isolated from the first electrode strip;

The second electrode strip and the third electrode strip connected to the second electrode strip form a second electrode.

Preferably, the third electrode strip is a straight strip, one end is connected to the innermost second electrode strip; the other end passes through the opening of the first electrode strip and extends to the outermost second electrode strip.

Preferably, the first conductive layer, the second conductive layer and the third conductive layer are made of metal.

Preferably, the MOM capacitor comprises the second conductive layer arranged in multiple layers, and the plurality of through holes are also used to electrically connect the first electrode strips of the second conductive layers of the adjacent layers together, and second electrode strips for electrically connecting together the second conductive layers of adjacent layers.

Preferably, the first conductive layer and the third conductive layer at least shield the second electrode strips.

Preferably, it also includes a dummy layer located between the substrate and the first conductive layer, the dummy layer sequentially includes a well layer, an active layer, a dummy active layer and a dummy gate layer from bottom to top, wherein , the well layer and the active layer are connected through contact holes.

Preferably, the projections of the first conductive layer and the second conductive layer on the substrate fall into the region where the well layer is located.

In the MOM capacitor provided by the present invention, the electrode strips serving as the first electrodes and the electrode strips serving as the second electrodes in the second conductive layer are spaced around and alternately arranged, and the innermost layer is the second electrode, and the outermost layer is the first electrode. electrodes; the electrode strips serving as the first electrodes in the second conductive layer and the electrode strips serving as the second electrodes radiate outward from the center of the layer in a circle-in-a-circle manner, so that the arrangement between the electrode strips is compact, and Compared with the electrode distribution in the prior art, the embodiment of the present invention obtains the same capacitance value, the required line width and spacing value of the first electrode and the second electrode are smaller, and further the required area is smaller, that is, the same area In this embodiment, the density is higher, the utilization rate is higher, and the cost is lower.

Further, since each second electrode strip is surrounded by the first electrode strip, and the second electrode strip does not face the power ground, it is possible to flexibly adjust the size of the MOM capacitance value (for example, under the condition that the area and the capacitance to the ground remain unchanged) Directly delete the second electrode strip in the middle), and it is convenient for layout work.

Further, since each second electrode strip is surrounded by the first electrode strip, and the second electrode strip does not face the power ground, it can be achieved that the area and the capacitance to the ground remain unchanged, by adjusting the line width of the first electrode and the The size of the capacitance can be easily adjusted by the distance between the second electrode and the second electrode, which makes the layout design work easier.

Further, in the MOM capacitor provided by the embodiment of the present invention, the electrode strip of the first electrode is used to protect the electrode strip of the second electrode, thereby only introducing parasitic capacitance between the power supply ground and the first electrode, and between the second electrode and the power supply ground. The parasitic capacitance is basically negligible.

In a preferred embodiment, the overall capacitance value of the MOM capacitor is increased by the stacked design of the fourth conductive layer and the second conductive layer.

In a preferred embodiment, a well layer, an active layer, a dummy active layer and a dummy gate layer are provided in the semiconductor substrate to block noise from the semiconductor substrate, thereby preventing noise from entering MOM capacitors.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1 shows the structure schematic diagram of MOM capacitor in the prior art;

Fig. 2 shows the three-dimensional schematic diagram of the MOM capacitor of the first embodiment of the present invention;

FIG. 3 shows a schematic top view of the structure of the second conductive layer according to the first embodiment of the present invention;

FIG. 4 shows a schematic three-dimensional structure diagram of the MOM capacitor according to the second embodiment of the present invention;

Fig. 5 shows the top view of the conductor layer of the second embodiment of the present invention;

6 is a schematic diagram showing the projection of the second through hole between the conductor layer and the first conductive layer on the first conductive layer according to the second embodiment of the present invention;

7 shows a schematic diagram of the projection of the first through hole between the second conductive layer and the third conductive layer on the third conductive layer according to the second embodiment of the present invention;

FIG. 8 shows a schematic diagram of the projection structure of the third through hole and the fourth through hole on the conductor layer according to the second embodiment of the present invention;

9 shows a cross-sectional view of a MOM capacitor of a third embodiment of the present invention.

Detailed ways

The present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are designated by like reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale. Additionally, some well-known parts may not be shown.

The invention may be embodied in various forms, some examples of which will be described below.

FIG. 2 shows a schematic three-dimensional structure of the MOM capacitor 200 according to the first embodiment of the present invention; as shown in FIG. 2 , the MOM capacitor 200 includes a substrate 201 , a multi-layer conductive layer 202 located on the substrate 201 and a An insulating layer (not shown in the figure) between the conductive layers 202 of each layer and between the electrode strips of the same conductive layer 202 . The conductive layer 202 includes a first conductive layer 21 , a second conductive layer 22 and a third conductive layer 23 .

Each of the first conductive layer 21 to the third conductive layer 23 can be made of various metals. The first conductive layer 21 is located over the substrate 201 . The first conductive layer 21 and the third conductive layer 23 are metal plates without any openings or hollows. A second conductive layer 22 is formed over the first conductive layer 21 . A third conductive layer 23 is formed over the second conductive layer 22 . The second conductive layer 22 includes a plurality of electrode strips. A part of the electrode strips of the second conductive layer 22 are electrically connected to the first conductive layer 21 and the third conductive layer 23 through the through holes 203 to form the first electrodes, and the remaining part of the electrode strips of the second conductive layer 22 form the second electrodes, so The first electrode and the second electrode have opposite polarities.

FIG. 3 shows a schematic top view of the second conductive layer according to the first embodiment of the present invention. As shown in FIG. 3 , the second conductive layer 22 includes a plurality of first electrode strips 221 and second electrodes spaced apart from each other. strips 222, a plurality of first electrode strips 221 and second electrode strips 222 spaced apart from each other are surrounded and alternately arranged on the plane where the second conductive layer 22 is located, and are located on the second conductive layer 22 The center of the plane is one of the plurality of second electrode strips 222, and the edge of the plane where the second conductive layer 22 is located is one of the plurality of first electrode strips 221, so as to ensure that each of the Each of the second electrode strips 222 is surrounded by a first electrode strip 221 . The plurality of second electrode strips 222 are electrically connected through third electrode strips 223 .

In this embodiment, the first electrode strips 221 and the second electrode strips 222 are spaced and alternately arranged in a "back" shape on the plane where the second conductive layer 22 is located. The layer 22 includes two first electrode strips 221 and two second electrode strips 222, which are the first electrode strips 2211, the first electrode strips 2212, the second electrode strips 2221 and the second electrode strips 2222, respectively. On the plane where the two conductive layers 22 are located, the second electrode strips 2221 , the first electrode strips 2211 , the second electrode strips 2222 , and the first electrode strips 2212 are in a “back” shape and are arranged in order from the inside to the outside.

Specifically, the second electrode strips 2221 are rectangular and are located at the center of the plane where the entire second conductive layer 22 is located. The first electrode strips 2211 are rectangular frames surrounding the second electrode strips 2221 and are connected to the second electrode The strips 2221 are isolated, the first electrode strips 2211 have openings for the third electrode strips 223 to pass through; the second electrode strips 2222 are rectangular frames surrounding the first electrode strips 2211 and are connected to the The first electrode strip 2211 is isolated; the first electrode strip 2212 is a rectangular frame surrounding the second electrode strip 2222 and is isolated from the second electrode strip 2222, the first electrode strip 2212 has openings for The third electrode strips 223 pass through. The third electrode bar 223 is a straight line, one end is connected to the second electrode bar 2221, and the other end extends outward through the openings of the first electrode bar 2211 and the first electrode bar 2212, so as to realize the first electrode bar 2212. The connection between the two electrode strips 2221 and the second electrode strip 2222 and the electrical connection between adjacent MOM capacitors.

In the MOM capacitor 200 , the first conductive layer 21 , the third conductive layer 23 , and a part of the electrode strips (first electrode strips) that are electrically connected to the first conductive layer 21 , the third conductive layer 23 and the second conductive layer 22 and the first conductive layer 21 and the third electrode layer 23 are used as the first electrodes , and another part of the electrode strips (the second electrode strip and the third electrode strip) remaining in the second conductive layer 22 are used as the second electrodes. The first electrode and the second electrode have opposite polarities, thereby forming a capacitance between the first electrode and the second electrode.

In this embodiment, the electrode strips serving as the first electrodes and the electrode strips serving as the second electrodes in the second conductive layer are spaced and alternately arranged in a "back" shape, and the innermost layer is the second electrode, and the outermost layer is The first electrode; the electrode strips as the first electrode and the electrode strips as the second electrode in the second conductive layer radiate outwards from the center of the layer in a circle-in-a-circle manner, so that the arrangement between the electrode strips is compact , compared with the distribution between electrodes in the prior art (as shown in FIG. 1 ), in this embodiment, within the same area, the total space between the first electrode and the second electrode is larger, so the first The capacitance value between the first electrode and the second electrode is larger, and a larger capacitance value can be obtained with the same area. In other words, this embodiment obtains the same capacitance value as the prior art (as shown in FIG. 1 ), the required line width and spacing value of the first electrode and the second electrode are smaller, and the further required area is smaller, that is, Within the same area, the density of this embodiment is higher, the utilization rate is higher, and the cost is lower.

Further, in this embodiment, since the first conductive layer and the third conductive layer have a planar shape and are used as the first electrode, only the first electrode faces the power ground, so only the power ground is opposite to the power ground. Parasitic capacitance is introduced between one electrode, and the electrode strip used as the second electrode is surrounded by the electrode strip used as the first electrode, so the parasitic capacitance between the second electrode and the power ground can be basically ignored. Therefore, in this embodiment, the parasitic capacitance between the second electrode and the power supply ground can be significantly reduced. Furthermore, by increasing the surface area of the first conductive layer, although the parasitic capacitance between the first electrode and the power supply ground is also increased, the parasitic capacitance between the second electrode and the power supply ground can be further reduced.

Of course, the surface area of the first conductive layer can also be appropriately reduced to further reduce the cost. For example, the surface area of the first conductive layer can be reduced to just enough to shield each end of the electrode strip in the second conductive layer serving as the second electrode, so although the parasitic capacitance between the second electrode and power ground may increase , but the increase is within a tolerable range. In general, the parasitic capacitance should be less than 5% of the capacitance value between the first electrode and the second electrode. To sum up, although the MOM capacitor provided in this embodiment has a parasitic capacitance between the first electrode and the power supply ground, since the second electrode is almost completely protected by the first electrode, the connection between the second electrode and the power supply ground is reduced. The parasitic capacitance is very small, even close to zero.

For the convenience of description, FIG. 3 shows a specific layout design, but the implementation of the present invention is not limited to this layout design. For example, the layout design shown in Figure 3 is used to illustrate that "the electrode strips serving as the first electrodes and the electrode strips serving as the second electrodes in the second conductive layer are spaced and alternately arranged in a "back" shape, and the innermost layer The core idea is the second electrode, and the outermost layer is the first electrode. In other layout designs, the first electrode strips and the second electrode strips with any number of turns can be provided; in other layout designs, the shapes of the plurality of first electrode strips 221 and the second electrode strips 222 spaced apart from each other are also The first electrode strips 221 and the second electrode strips 222 with circular, polygonal or irregular shapes are spaced and alternately arranged on the plane where the second conductive layer 22 is located. As long as the above-mentioned core ideas are satisfied, the same or similar effects can be produced.

In the embodiment of the present invention, since each second electrode strip is surrounded by the first electrode strip, and the second electrode strip does not face the power supply ground, it is possible to flexibly adjust the capacitance value of the MOM capacitor under the condition that the area and the capacitance to the ground remain unchanged. Especially when the layout work of the capacitor array has been completed, the second electrode strip in the middle can be directly deleted to adjust the size of the MOM capacitance value, which is convenient for the layout work.

Further, since each second electrode strip is surrounded by the first electrode strip, and the second electrode strip does not face the power ground, it can be achieved that the area and the capacitance to the ground remain unchanged, by adjusting the line width of the first electrode and the The size of the capacitance can be easily adjusted by the distance between the second electrode and the second electrode, which makes the layout design work easier.

FIG. 4 shows a schematic three-dimensional structure of the MOM capacitor according to the second embodiment of the present invention; as shown in FIG. 4 , compared with the first embodiment, a fourth conductive layer 301 is added to the MOM capacitor of this embodiment.

FIG. 5 shows a top view of the fourth conductive layer 301 according to the second embodiment of the present invention. As shown in FIG. 5 , the layout design of the fourth conductive layer 301 is substantially the same as that of the second conductive layer 22 .

Specifically, the fourth conductive layer 301 includes a plurality of fourth electrode strips 321 and fifth electrode strips 322 spaced apart from each other, and the plurality of fourth electrode strips 321 and fifth electrode strips 322 spaced apart from each other are in the On the plane where the four conductive layers 301 are located, they are spaced and alternately arranged in a "back" shape, and located in the center of the plane where the fourth conductive layer 301 is located is one of the plurality of fifth electrode strips 322, located in the The edge of the plane where the fourth conductive layer 301 is located is one of the plurality of fourth electrode strips 321 , so as to ensure that each of the fifth electrode strips 322 is surrounded by a fourth electrode strip 321 . The plurality of fifth electrode strips 322 are electrically connected through sixth electrode strips 623 .

The number of the fourth electrode strips 321 on the fourth conductive layer 301 is the same as the number of the first electrode strips 221 on the second conductive layer 22 , and the projection of the fourth electrode strips 321 on the second conductive layer 22 It is substantially coincident with the projection of the first electrode strips 221 on the second conductive layer 22 on the second conductive layer 22 . The number of the fifth electrode strips 322 on the third conductive layer 23 is the same as the number of the second electrode strips 222 on the second conductive layer 22 , and the projection of the fifth electrode strips 322 on the second conductive layer 22 is the same as that of all the fifth electrode strips 322 on the second conductive layer 22 . The projections of the second electrode strips 222 on the second conductive layer 22 on the second conductive layer 22 are substantially overlapped.

The fourth conductive layer 301 includes fourth electrode strips 3211 , fourth electrode strips 3212 , fifth electrode strips 3221 and fifth electrode strips 3222 respectively, wherein, on the plane where the entire fourth conductive layer 301 is located, the fifth electrode strips The strips 3221, the fourth electrode strips 3211, the fifth electrode strips 3222, and the fourth electrode strips 3212 are in the shape of a "return" and are arranged in order from the inside to the outside. The plurality of fifth electrode strips 322 are connected through sixth electrode strips 323 , and the sixth electrode strips 323 are arranged in isolation from the fourth electrode strips 321 .

The fifth electrode strip 3221 is located at the center of the plane where the entire fourth conductive layer 301 is located. The fourth electrode strip 3211 is arranged around the fifth electrode strip 3221 and is isolated from the fifth electrode strip 3221; the fifth electrode The strips 3222 are arranged around the fourth electrode strips 3211 and are isolated from the fourth electrode strips 3211 ; the fourth electrode strips 3212 are arranged around the fifth electrode strips 3222 and are isolated from the fifth electrode strips 3222 .

Different from the second conductive layer 22, only the fourth electrode strip 3212 has openings, the fourth electrode strip 3212 in the outermost layer has no openings, and the sixth electrode strip 323 only passes through the fourth electrode strip 3212 in the inner layer. Stop at the fifth electrode layer 3222 .

In this embodiment, the first electrode strips 221 of the second conductive layer 22 are electrically connected to the third conductive layer 23 through the first through holes 331 ; the fourth electrode strips 321 of the fourth conductive layer 301 are electrically connected to the third conductive layer 23 through the second through holes 332 . A conductive layer 21 is connected; FIG. 6 shows a schematic diagram of the projection of the second through hole 332 between the fourth conductive layer 301 and the first conductive layer 21 on the first conductive layer 21 according to the second embodiment of the present invention; FIG. 7 shows a schematic diagram of the projection of the first through hole 331 between the second conductive layer 22 and the third conductive layer 23 on the third conductive layer 23 according to the second embodiment of the present invention.

The first electrode strips 221 in the second conductive layer 22 and the corresponding fourth electrode strips 321 in the fourth conductive layer 301 , and the second electrode strips 222 in the second conductive layer 22 and the corresponding fourth electrode strips 321 in the fourth conductive layer 301 The five electrode bars 322 are connected through the third through holes 333 and the fourth through holes 334 respectively. FIG. 8 is a schematic diagram showing the projection structure of the third through hole and the fourth through hole on the fourth conductive layer 301 according to the second embodiment of the present invention.

In this embodiment, the overall capacitance value of the MOM capacitor is increased through the stacked design of the fourth conductive layer 301 and the second conductive layer 22 .

In other embodiments, a three-layer or more stacked structure can also be used to increase the overall capacitance value of the capacitor, for example, to increase the number of conductor layers. But in essence, the core idea of such a layout design is the same as the previous layout design.

9 shows a cross-sectional view of a MOM capacitor of a third embodiment of the present invention. As shown in FIG. 9, compared with the second embodiment, the MOM capacitor shown in this embodiment further includes a dummy layer located between the substrate 201 and the first conductive layer 21. The dummy layer From bottom to top, it includes a well layer 401 , an active layer 402 , a dummy active layer 403 and a dummy gate layer 404 , wherein the well layer 401 and the active layer 402 are connected through a contact hole 405 .

For the semiconductor device of the embodiment of the present invention, the well layer 401 and the active layer 402 can block the noise from the semiconductor substrate 201, thereby preventing the noise from entering the MOM capacitor.

Wherein, the projection of the MOM capacitor on the upper surface of the semiconductor substrate 201 can completely fall into the region where the well layer 401 is located by adjusting the design scheme. This design can better prevent noise from the semiconductor substrate 201 from entering the MOM capacitor.

Embodiments in accordance with the present invention are described above, but these embodiments do not exhaust all the details and do not limit the invention to only the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. These embodiments are selected and described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and modifications based on the present invention. The present invention is to be limited only by the claims and their full scope and equivalents.

Claims (9)

1. a MOM capacitor, is characterized in that, comprises: substrate; a first conductive layer located on the substrate, the first conductive layer is a conductive electrode plate; a second conductive layer on the first conductive layer, the second conductive layer including a plurality of first electrode strips and second electrode strips spaced apart from each other; a third conductive layer on the second conductive layer, the third conductive layer is a conductive electrode plate; and a plurality of through holes for electrically connecting the first electrode strips to the first conductive layer and the third conductive layer to form a first electrode, and the plurality of second electrode strips are electrically connected, forming a second electrode, the second electrode is opposite in polarity to the first electrode; Wherein, the first electrode strips and the second electrode strips are alternately arranged in a surrounding shape on the plane where the second conductive layer is located; the center of the plane where the second conductive layer is located is among the plurality of second electrode strips One of the plurality of first electrode strips is located at the edge of the plane where the second conductive layer is located. 2. The MOM capacitor according to claim 1, wherein the shape of the first electrode strip and the second electrode strip is one or more of a rectangle, a circle, a polygon or an irregular figure, so as to On the plane where the second conductive layer is located, first electrode strips and second electrode strips that are surrounded and distributed alternately at intervals are formed. 3. The MOM capacitor according to claim 1, wherein the second conductive layer further comprises a third electrode strip for connecting the second electrode strips separated from each other together; the third electrode strip is isolated from the first electrode strip; The second electrode strip and the third electrode strip connected to the second electrode strip form a second electrode. 4 . The MOM capacitor according to claim 3 , wherein the third electrode strip is a straight line, and one end is connected to the second electrode strip in the innermost layer; the other end passes through the opening of the first electrode strip and is always extending to the outermost second electrode strip. 5 . The MOM capacitor according to claim 1 , wherein the first conductive layer, the second conductive layer and the third conductive layer are made of metal. 6 . 6 . The MOM capacitor according to claim 1 , wherein the MOM capacitor comprises the second conductive layer arranged in multiple layers, and the plurality of through holes are also used for connecting the first conductive layers of adjacent layers. 7 . The first electrode strips of the two conductive layers are electrically connected together, and the second electrode strips of the second conductive layer of adjacent layers are electrically connected together. 7 . The MOM capacitor according to claim 1 , wherein the first conductive layer and the third conductive layer at least shield the second electrode strips. 8 . 8 . The MOM capacitor according to claim 1 , further comprising a dummy layer located between the substrate and the first conductive layer, the dummy layer including a well layer, an active layer and an active layer in sequence from bottom to top. 9 . layer, a dummy active layer and a dummy gate layer, wherein the well layer and the active layer are connected through contact holes. 9 . The MOM capacitor according to claim 8 , wherein the projections of the first conductive layer and the second conductive layer on the substrate fall into the region where the well layer is located. 10 .

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