CN114582841A - MOM capacitor - Google Patents

Abstract

A MOM capacitor is disclosed, comprising: a substrate; a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked on the substrate, the first conductive layer and the fourth conductive layer are respectively A polar plate, the second conductive layer includes a plurality of first electrode strips and second electrode strips spaced apart from each other, and the third conductive layer includes a plurality of third electrode strips and fourth electrode strips spaced apart from each other; A hole is used to electrically connect the first conductive layer, the first electrode strip of the second conductive layer and the third electrode strip of the third conductive layer and the fourth conductive layer to form a first electrode, and is used to connect the second conductive layer The second electrode strip is electrically connected with the fourth electrode strip of the third conductive layer to form a second electrode; wherein, a plurality of second electrode strips are distributed along the same direction, and each second electrode strip surrounds the first electrode strip; The fourth electrode strip is a pole plate, and a plurality of third electrode strips surround the fourth electrode strip.

Description

A MOM capacitor

technical field

The present invention relates to the technical field of semiconductors, in particular to a MOM capacitor.

Background technique

In the field of capacitor array structure, capacitor is a very important basic element. Metal-Oxide-Metal (MOM) capacitors and Metal-Insulator-Metal (MIM) capacitors are two common capacitor structures. MIM capacitors use metal patterns on the same layer or on different layers to form the same electrode, and the capacitance value is mainly composed of capacitors formed by different conductor layers. The MOM capacitor adopts the metal pattern of the same layer to form two electrodes with opposite polarities at the same time, so its capacitance value can include the capacitance formed by the same conductor layer.

Referring to FIG. 1, the MOM capacitor 100 includes a substrate 101 and a conductor layer M1. The conductor layer M1 includes two comb-shaped first electrodes 102 and second electrodes 103. The first electrodes and the second electrodes have opposite polarities. The electrode strips included in each of the comb-shaped structures are alternately arranged so that a capacitance is formed between the electrode strips of different electrodes, and the capacitance value of the capacitor 100 is equal to the sum of the capacitances formed by these electrode strips. This design of the MOM capacitor helps to increase the capacitance per unit area, thereby helping to reduce the area occupied by the MOM capacitor, which in turn helps improve the integration level of the semiconductor circuit. In order to increase the capacitance value, the MOM capacitor shown in Figure 1 can also be designed with a stacked layer, so that the total capacitance is mainly equal to the sum of the capacitance of the same layer, the capacitance between different layers, and the capacitance between each electrode strip and the through hole.

However, due to the limitation of design rules, the spacing between the horizontal traces of the electrode strips and the spacing between the vertical traces are different, which will limit the routing of the electrode strips.

SUMMARY OF THE INVENTION

In view of the above problems, the purpose of the present invention is to provide a MOM capacitor to improve the utilization rate of the capacitor area.

The present invention provides a MOM capacitor, comprising:

substrate;

A first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer are stacked on the substrate, the first conductive layer and the fourth conductive layer are respectively a pole plate, and the The second conductive layer includes a plurality of first and second electrode strips spaced apart from each other, the third conductive layer including a plurality of third electrode strips and fourth electrode strips spaced apart from each other; and

a plurality of through holes for electrically connecting the first conductive layer, the first electrode strips of the second conductive layer, the third electrode strips of the third conductive layer and the fourth conductive layer to form a first electrode, and a second electrode for electrically connecting the second electrode strip of the second conductive layer and the fourth electrode strip of the third conductive layer to form a second electrode;

Wherein, the plurality of second electrode strips are distributed in the same direction, and each second electrode strip surrounds the first electrode strip; the fourth electrode strip is a pole plate, and the plurality of third electrode strips surround the fourth electrode strip.

Preferably, the plurality of second electrode strips are mutually independent finger electrodes.

Preferably, the plurality of first electrode strips are a plurality of rectangular frames connected together, and each rectangular frame has a second electrode strip spaced from the rectangular frame.

Preferably, the fourth electrode strip further comprises finger-shaped electrode strips connected to the electrode plate around the electrode plate.

Preferably, the electrode plate is rectangular, and the finger-shaped electrode strips are located on four sides of the electrode plate, are perpendicular to the four sides of the electrode plate, and are connected to the four sides of the electrode plate.

Preferably, the third electrode strip is a rectangular frame, and four sides of the rectangular frame have openings.

Preferably, the projection of the second electrode strip on the third conductive layer is located in the area of the fourth electrode strip.

Preferably, the second conductive layer includes any number of layers, and the second conductive layers of any number of layers are stacked and located between the first conductive layer and the third conductive layer.

Preferably, the second electrode strips in each second conductive layer are arranged in the same first direction.

Preferably, the second electrode strips in the same second conductive layer are arranged in the same direction, and the second electrode strips in different second conductive layers are arranged in different directions.

Preferably, the first electrode strips of adjacent second conductive layers are electrically connected; and the second electrode strips of adjacent second conductive layers are electrically connected.

Preferably, the second conductive layer and the third conductive layer in any number of layers are included, and the number of layers of the second conductive layer and the third conductive layer in any layer is the same, and the second conductive layer and the third conductive layer are perpendicular to each other. The directions of the substrates are alternately stacked.

Preferably, it also includes a dummy layer located between the substrate and the first conductive layer, the dummy layer sequentially includes a well layer, an active layer, a dummy active layer and a dummy gate layer from bottom to top, wherein , the well layer and the active layer are connected through contact holes.

Preferably, the projections of the first conductive layer and the second conductive layer on the substrate fall into the region where the well layer is located.

In the MOM capacitor provided by the present invention, through the cooperation of two conductive layers, one of the conductive layers includes a plurality of electrodes distributed in the same direction, and the electrode strips in the other conductive layer are a whole electrode plate, and the electrodes distributed in the same direction are arranged in the same direction. The electrodes are covered; the electrodes are distributed in the same direction, which relieves the limitation of the crisscross wiring, making the wiring of the electrodes relatively simple; at the same time, a whole electrode plate is used as the electrode to increase the capacitance area.

Further, in the MOM capacitor provided by the embodiment of the present invention, the electrode strip of the first electrode is used to protect the electrode strip of the second electrode, thereby only introducing parasitic capacitance between the power supply ground and the first electrode, and between the second electrode and the power supply ground. The parasitic capacitance is basically negligible.

In a preferred embodiment, the overall capacitance value of the MOM capacitor is increased by the stacked design of the fourth conductive layer and the second conductive layer.

In a preferred embodiment, a well layer, an active layer, a dummy active layer and a dummy gate layer are provided in the semiconductor substrate to block noise from the semiconductor substrate, thereby preventing noise from entering MOM capacitors.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1 shows the three-dimensional structure schematic diagram of the MOM capacitor of the prior art;

Fig. 2 shows the three-dimensional schematic diagram of the MOM capacitor of the first embodiment of the present invention;

FIG. 3 shows a schematic top view of the structure of the second conductive layer according to the first embodiment of the present invention;

FIG. 4 shows a schematic top view of the structure of the third conductive layer according to the first embodiment of the present invention;

Fig. 5 shows the three-dimensional schematic diagram of the MOM capacitor of the second embodiment of the present invention;

Fig. 6 shows the three-dimensional structure schematic diagram of the MOM capacitor of the third embodiment of the present invention;

FIG. 7 shows a cross-sectional view of a MOM capacitor of a fourth embodiment of the present invention.

Detailed ways

The present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are designated by like reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale. Additionally, some well-known parts may not be shown.

The invention may be embodied in various forms, some examples of which will be described below.

FIG. 2 shows a schematic three-dimensional structure of the MOM capacitor 200 according to the first embodiment of the present invention; as shown in FIG. 2 , the MOM capacitor 200 includes a substrate 201 , a multi-layer conductive layer 202 located on the substrate 201 and a The insulating layer between the conductive layers 202 of each layer and between the electrode strips of the same conductive layer 202 . The conductive layer 202 includes a first conductive layer 21 , a second conductive layer 22 , a third conductive layer 23 and a fourth conductive layer 24 .

Each of the first to fourth conductive layers 21 to 24 can be made of various metals. The first conductive layer 21 is located over the substrate 201 . The first conductive layer 21 and the fourth conductive layer 24 are metal plates without any openings or hollows. A second conductive layer 22 is formed above the first conductive layer 21 , a third conductive layer 23 is formed above the second conductive layer 22 , and a fourth conductive layer 24 is formed above the third conductive layer 23 . The second conductive layer 22 and the third conductive layer 23 include a plurality of electrode strips; a part of the electrode strips of the second conductive layer 22 are electrically connected to the first conductive layer 21 through the through holes 25; a part of the third conductive layer 23 The electrode strips are electrically connected to the fourth conductive layer 24 via the through holes 25 ; the other part of the electrode strips remaining in the second conductive layer 22 is electrically connected to the other part of the electrode strips remaining in the third conductive layer 23 . In the MOM capacitor 200 , the first conductive layer 21 , the fourth conductive layer 24 , a part of the electrode strips of the second conductive layer 22 electrically connected to the first conductive layer 21 , and the third conductive layer 23 electrically connected to the fourth conductive layer 24 A part of the electrode strips are used as the first electrodes, and the other part of the electrode strips remaining in the second conductive layer and the other part of the electrode strips remaining in the third conductive layer are used as the second electrodes. The first electrode and the second electrode have opposite polarities, thereby forming a capacitance between the first electrode and the second electrode.

FIG. 3 shows a schematic top view of the second conductive layer according to the first embodiment of the present invention. As shown in FIG. 3 , the second conductive layer 22 includes a first electrode strip 221 and a second electrode strip 222 that are spaced apart from each other. , the second electrode strip 222 is a plurality of mutually independent finger electrodes, and a plurality of mutually independent finger electrodes are distributed along the same direction in the plane where the second conductive layer 22 is located; each of the second electrodes The peripheries of the strips 222 surround the first electrode strips 221 .

In this embodiment, the second conductive layer 22 includes two finger-shaped second electrode strips 222 , and the finger-shaped second electrode strips 222 are distributed along the first direction on the plane where the second conductive layer 22 is located. Inside. The first electrode strips 221 are a plurality of rectangular frames connected together, and a second electrode strip 222 is distributed inside the first electrode strips 221 of each rectangular frame, so as to realize the surrounding of each second electrode strip 222 All surround the first electrode strips 221 .

FIG. 4 shows a schematic top view of the structure of the third conductive layer according to the first embodiment of the present invention. As shown in FIG. 4 , the third conductive layer 23 includes a third electrode strip 231 and a fourth electrode strip 232 that are spaced apart from each other. . The fourth electrode strip 232 is an integral metal plate, and the third electrode strip 231 surrounds the fourth electrode strip 232 .

In this embodiment, the fourth electrode strips 232 include a rectangular fourth electrode strip 2321 and a plurality of finger-shaped fourth electrode strips 2322; wherein the plurality of finger-shaped fourth electrode strips 2322 are located on the rectangular fourth electrode strips The four sides of the strip 2321 are perpendicular to the four sides of the rectangular fourth electrode strip 2321, and are connected to the four sides of the rectangular fourth electrode strip 2321, and the plurality of finger-shaped fourth electrode strips 2322 are respectively It extends from the four sides of the rectangular fourth electrode strips 2321 in a direction away from the rectangular fourth electrode strips 2321 .

The third electrode strip 231 is a rectangular frame surrounding the fourth electrode strip 232 , four sides of the rectangular frame have openings 2311 , and the finger-shaped fourth electrode strips 2322 pass through the opening 2311 , which extends to the outside of the third electrode strip 231 and is connected to the adjacent MOM capacitors.

The projection of the second electrode strip 222 on the third conductive layer 23 is located in the area of the fourth electrode strip 232 , that is, the fourth electrode strip 232 covers all the second electrode strip 122 in the third electrode strip 232 . Projection of the conductive layer 23 .

The first electrode strips 221 of the second conductive layer 22 are connected to the first conductive layer 21 through the first through holes 251 , and the third electrode strips 231 of the third conductive layer 23 are connected to the first conductive layer 21 through the second through holes 252 . The fourth conductive layer 24 is connected, and each second electrode bar 222 of the second conductive layer 22 is connected to the fourth electrode bar 232 of the third conductive layer through a third through hole 253; the second conductive layer The first electrode strips 221 of 22 are connected to the third electrode strips 231 of the third conductive layer through fourth through holes 254 .

In the MOM capacitor 200 , the first conductive layer 21 , the fourth conductive layer 24 , the first electrode strips 221 of the second conductive layer 22 and the first conductive layer 21 are electrically connected to the first conductive layer 21 , and the third conductive layer 23 is electrically connected to the fourth conductive layer 24 The third electrode strips 231 are used as the first electrodes, the second electrode strips 222 remaining in the second conductive layer 22 and the fourth electrode strips 232 remaining in the third conductive layer 23 are used as the second electrodes. The first electrode and the second electrode have opposite polarities, thereby forming a capacitance between the first electrode and the second electrode.

For the convenience of description, FIG. 3 and FIG. 4 show a specific layout design, but the implementation of the present invention is not limited to this layout design. For example, the layout design shown in Figure 3 is used to illustrate that "the electrode strips used as the second electrode in the second conductive layer are distributed in the same direction, and the electrode strips used as the second electrode in the third conductive layer are the whole electrode plate" this core idea. In other layout designs, any number of first electrode strips and second electrode strips can be provided, as long as the above-mentioned core idea is satisfied, the same or similar effects can be produced.

In this embodiment, the first electrode and the second electrode are formed in cooperation between two conductive layers, wherein one conductive layer includes a plurality of electrodes distributed in the same direction, and the electrode strips in the other conductive layer are a whole electrode plate, And the electrodes distributed in the same direction are covered; the electrodes are distributed in the same direction, which relieves the limitation of crisscross wiring and makes the wiring of the electrodes relatively simple; at the same time, a whole electrode plate is used as the electrode to increase the capacitance area.

Further, in this embodiment, since the first conductive layer and the third conductive layer have a planar shape and are used as the first electrode, only the first electrode faces the power ground, so only the power ground is opposite to the power ground. Parasitic capacitance is introduced between one electrode, and the electrode strip used as the second electrode is surrounded by the electrode strip used as the first electrode, so the parasitic capacitance between the second electrode and the power ground can be basically ignored. Therefore, in this embodiment, the parasitic capacitance between the second electrode and the power supply ground can be significantly reduced. Furthermore, by increasing the surface area of the first conductive layer, although the parasitic capacitance between the first electrode and the power supply ground is also increased, the parasitic capacitance between the second electrode and the power supply ground can be further reduced.

Of course, the surface area of the first conductive layer can also be appropriately reduced to further reduce the cost. For example, the surface area of the first conductive layer can be reduced to just enough to shield each end of the electrode strip in the second conductive layer serving as the second electrode, so although the parasitic capacitance between the second electrode and power ground may increase , but the increase is within a tolerable range. In general, the parasitic capacitance should be less than 5% of the capacitance value between the first electrode and the second electrode. To sum up, although the MOM capacitor provided in this embodiment has parasitic capacitance between the first electrode and the power supply ground, since the second electrode is almost completely protected by the first electrode, the connection between the second electrode and the power supply ground is reduced. The parasitic capacitance is very small, even close to zero.

FIG. 5 shows a schematic three-dimensional structure of the MOM capacitor according to the second embodiment of the present invention; as shown in FIG. 5 , compared with the first embodiment, the conductive layer 202 of the MOM capacitor of this embodiment is provided with a second arbitrary number of layers. For the conductive layer 22 , the second conductive layer 22 with any number of layers is stacked and disposed between the first conductive layer 21 and the third conductive layer 23 . In this embodiment, the overall capacitance value of the MOM capacitor is increased by the second conductive layer 22 designed by stacking. But in essence, the core idea of such a layout design is the same as the previous layout design.

Specifically, the shapes of the first electrode strips 221 and the second electrode strips 222 in each second conductive layer 22 are the same, and the distribution directions of the second electrode strips 222 in different second conductive layers 22 may be the same or different; For example, in this embodiment, the second electrode strips 222 in each second conductive layer 22 are arranged in the same first direction. In other embodiments, the second electrode strips 222 in the same second conductive layer 22 are arranged in the same first direction. The arrangement direction is the same, and the second electrode strips 222 in different second conductive layers 22 may be arranged in different directions (for example, mutually perpendicular directions).

The first electrode strips 221 of the adjacent second conductive layers 22 are electrically connected, and the first electrode strips 221 of the second conductive layer adjacent to the first conductive layer 21 are electrically connected to the first conductive layer 21 and electrically connected to the third conductive layer 21 . The first electrode strips 221 of the second conductive layer 22 adjacent to the conductive layer 23 are electrically connected to the third electrode strips 231 of the third conductive layer 23 ; the second electrode strips 222 of the adjacent second conductive layers 22 are electrically connected , the second electrode strips 222 of the second conductive layer 22 adjacent to the third conductive layer 23 are electrically connected to the fourth electrode strips 232 of the third conductive layer 23 .

FIG. 6 shows a schematic three-dimensional structure of the MOM capacitor according to the third embodiment of the present invention; as shown in FIG. 6 , compared with the first embodiment, the conductive layer 202 of the MOM capacitor of the present embodiment can be provided with any number of layers. Two conductive layers 22 and third conductive layers 23, the number of layers of the second conductive layer 22 and the third conductive layer 23 in any layer is the same, and the second conductive layer 22 and the third conductive layer 23 are along the vertical direction of the substrate. The directions are alternately stacked.

In FIG. 6, two sets of second conductive layers 22 and third conductive layers 23 are arranged in the direction perpendicular to the substrate, and the second conductive layers and the third conductive layers 23 are alternately stacked along the direction perpendicular to the substrate set up. In this embodiment, the overall capacitance value of the MOM capacitor is increased by stacking multiple sets of the second conductive layer 22 and the third conductive layer 23 . But in essence, the core idea of such a layout design is the same as the previous layout design.

FIG. 7 shows a cross-sectional view of a MOM capacitor of a fourth embodiment of the present invention. As shown in FIG. 7 , compared with the first embodiment, the MOM capacitor shown in this embodiment further includes a dummy layer located between the substrate 201 and the first conductive layer 21 , and the dummy layer From bottom to top, it includes a well layer 401 , an active layer 402 , a dummy active layer 403 and a dummy gate layer 404 , wherein the well layer 401 and the active layer 402 are connected through a contact hole 405 .

For the semiconductor device of the embodiment of the present invention, the well layer 401 and the active layer 402 can block the noise from the semiconductor substrate 201, thereby preventing the noise from entering the MOM capacitor.

Wherein, the projection of the MOM capacitor on the upper surface of the semiconductor substrate 201 can completely fall into the region where the well layer 401 is located by adjusting the design scheme. This design can better prevent noise from the semiconductor substrate 201 from entering the MOM capacitor.

Embodiments in accordance with the present invention are described above, but these embodiments do not exhaust all the details and do not limit the invention to only the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. These embodiments are selected and described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and modifications based on the present invention. The present invention is to be limited only by the claims and their full scope and equivalents.

Claims (14)

1. a MOM capacitor, is characterized in that, comprises: substrate; A first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer are stacked on the substrate, the first conductive layer and the fourth conductive layer are respectively a pole plate, and the The second conductive layer includes a plurality of first and second electrode strips spaced apart from each other, the third conductive layer including a plurality of third electrode strips and fourth electrode strips spaced apart from each other; and a plurality of through holes for electrically connecting the first conductive layer, the first electrode strips of the second conductive layer, the third electrode strips of the third conductive layer and the fourth conductive layer to form a first electrode, and a second electrode for electrically connecting the second electrode strip of the second conductive layer and the fourth electrode strip of the third conductive layer to form a second electrode; Wherein, the plurality of second electrode strips are distributed in the same direction, and each second electrode strip surrounds the first electrode strip; the fourth electrode strip is a pole plate, and the plurality of third electrode strips surround the fourth electrode strip. 2 . The MOM capacitor according to claim 1 , wherein the plurality of second electrode strips are mutually independent finger electrodes. 3 . 3 . The MOM capacitor according to claim 1 , wherein the plurality of first electrode strips are a plurality of rectangular frames connected together, and each rectangular frame has a second electrode strip spaced from the rectangular frame. 4 . 4 . The MOM capacitor according to claim 1 , wherein the fourth electrode strip further comprises finger-shaped electrode strips connected to the electrode plate around the electrode plate. 5 . 5. MOM capacitor according to claim 4, is characterized in that, described polar plate is rectangular, and finger-shaped electrode strip is positioned at the four sides of polar plate, is perpendicular to the four sides of polar plate, and is with polar plate the four sides of the connection. 6 . The MOM capacitor according to claim 1 , wherein the third electrode strip is a rectangular frame, and four sides of the rectangular frame have openings. 7 . 7 . The MOM capacitor according to claim 1 , wherein the projection of the second electrode strip on the third conductive layer is located in the region of the fourth electrode strip. 8 . 8 . The MOM capacitor according to claim 1 , wherein the second conductive layer of any number of layers is included, and the second conductive layers of any number of layers are stacked and disposed in the first conductive layer and the third conductive layer. 9 . between. 9 . The MOM capacitor according to claim 8 , wherein the second electrode strips in each second conductive layer are arranged in the same first direction. 10 . 10 . The MOM capacitor according to claim 8 , wherein the second electrode strips in the same second conductive layer are arranged in the same direction, and the second electrode strips in different second conductive layers are arranged in different directions. 11 . 11 . The MOM capacitor according to claim 8 , wherein the first electrode strips of adjacent second conductive layers are electrically connected; and the second electrode strips of adjacent second conductive layers are electrically connected. 12 . 12. The MOM capacitor according to claim 1, wherein the second conductive layer and the third conductive layer of any number of layers are included, and the number of layers of the second conductive layer and the third conductive layer in any layer is the same, and The second conductive layers and the third conductive layers are alternately stacked along a direction perpendicular to the substrate. 13 . The MOM capacitor according to claim 1 , further comprising a dummy layer located between the substrate and the first conductive layer, the dummy layer including a well layer, an active layer and an active layer from bottom to top. layer, a dummy active layer and a dummy gate layer, wherein the well layer and the active layer are connected through contact holes. 14 . The MOM capacitor according to claim 13 , wherein the projections of the first conductive layer and the second conductive layer on the substrate fall into the region where the well layer is located. 15 .

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