CN114566199A - Read reference circuit, read operation circuit and memory cell - Google Patents

Abstract

The application provides a read reference circuit, a read operation circuit and a memory cell, the read reference circuit includes: one or more reference modules connected in parallel; the reference module comprises a first reference unit and a second reference unit which are connected in series and different in write data; the current directions of the first reference unit and the second reference unit are the same during writing operation and reading operation respectively. According to the technical scheme, the reading reference circuit, the reading operation circuit and the memory unit can avoid the interference of the MRAM during reading operation.

Description

Read reference circuit, read operation circuit and storage unit

technical field

The present application relates to the field of semiconductor technology, and in particular, to a read reference circuit, a read operation circuit and a storage unit.

Background technique

Magnetic random access memory (MRAM, Magnetic Random Access Memory) has the characteristics of high read and write speed, high density, low power consumption, long data retention time and long life, so it has immeasurable broad prospects. Due to the variable resistance of MRAM, data information can be stored through its different resistance states.

There is a magnetic tunnel junction (MTJ) in MRAM. The rewriting of MTJ data is to change the magnetic moment direction of the free layer through the flow of spin electrons. Therefore, a small current for a long time will also rewrite the data, so it is prone to read disturbances during read operations. ) causes data to be overwritten.

SUMMARY OF THE INVENTION

The technical problem solved by the present application is to prevent the MRAM from being disturbed during a read operation.

In order to solve the above technical problem, the present application provides a read reference circuit, comprising: one or more reference modules connected in parallel; the reference module includes two first reference units and second reference units that are connected in series and have different written data ; The current directions of the first reference unit and the second reference unit are the same during the write operation and the read operation, respectively.

In the embodiment of the present application, the read reference circuit further includes: a first reference bit line, connected to the first reference cell; a second reference bit line, connected to the second reference cell; and a reference source line, connected to the The first reference unit and the second reference unit; wherein, one of the first reference bit line and the second reference bit line outputs a reference signal, the other is connected to a low level, and the reference source line is floating .

In the embodiment of the present application, 0 is written to the first reference unit, 1 is written to the second reference unit, the first reference bit line outputs a reference signal, and the second reference bit line is connected to a low level.

In the embodiment of the present application, the first reference unit includes: a first MTJ unit, connected to the first reference bit line; a first transistor, a first electrode of the first transistor is connected to the first MTJ unit, The second electrode of the first transistor is connected to the reference source line and the second reference cell.

In the embodiment of the present application, the second reference unit includes: a second MTJ unit connected to the second reference bit line; a second transistor, the first electrode of the second transistor is connected to the second MTJ unit, The second electrode of the second transistor is connected to the reference source line and the second electrode of the first transistor.

The present application also provides a read operation circuit, including: a read reference circuit for providing a reference signal, including one or more reference modules connected in parallel, the reference modules including two first reference units connected in series and with different written data and the second reference unit, the current directions of the first reference unit and the second reference unit are the same when the write operation and the read operation are performed respectively; the data path provides the data to be read and outputs the data signal; the amplifier circuit, and The reference circuit is connected to the data path for comparing the data signal with the reference signal and obtaining a read result.

In this embodiment of the present application, the reference circuit further includes: a first reference bit line connected to the first reference cell; a second reference bit line connected to the second reference cell; and a reference source line connected to the first reference cell A reference unit and the second reference unit; one of the first reference bit line and the second reference bit line is connected to the amplifying circuit, the other is connected to a low level, and the reference source line is floating.

In the embodiment of the present application, 0 is written in the first reference cell, 1 is written in the second reference cell, the first reference bit line is connected to the amplifying circuit, and the second reference bit line is connected to a low level.

In the embodiment of the present application, the first reference unit includes: a first MTJ unit, connected to the first reference bit line; a first transistor, a first electrode of the first transistor is connected to the first MTJ unit, The second electrode of the first transistor is connected to the reference source line and the second reference cell.

In the embodiment of the present application, the second reference unit includes: a second MTJ unit connected to the second reference bit line; a second transistor, the first electrode of the second transistor is connected to the second MTJ unit, The second electrode of the second transistor is connected to the reference source line and the second electrode of the first transistor.

In the embodiment of the present application, the data path includes a data storage unit, one end of the data storage unit is connected to a bit line, the other end is connected to a source line, and the source line is connected to the amplifying circuit.

In the embodiment of the present application, the data signal is the output current of the data path, and the reference signal is the output current of the reference circuit.

In the embodiment of the present application, the amplifying circuit includes a sense amplifier.

The present application also provides a storage unit, including the read operation circuit described in the claims.

The read reference circuit of the technical solution of the present application includes one or more reference modules connected in parallel, and each reference module includes two first reference cells and second reference cells that are connected in series and have different written data, and make the first reference The read operation current of the unit and the second reference unit are in the same direction as the write operation current, which effectively solves the problem of read disturb in the reference unit that writes "1", significantly improves the data storage performance, and also ensures that the improved The consistency of the reference circuit and the overall array breaks the conventional cognition that the reference bit line is connected to a high level and the reference source line is connected to a low level during a read operation in the existing read reference circuit.

Description of drawings

The following figures describe in detail exemplary embodiments disclosed in this application. Where like reference numbers refer to similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, the accompanying drawings are for illustration and description purposes only, and are not intended to limit the scope of the application, and other embodiments are also possible The same accomplishes the inventive intent in this application. It should be understood that the figures are not drawn to scale. in:

1 is a schematic structural diagram of a reference circuit;

2 is a schematic structural diagram of a read reference circuit according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a read operation circuit according to an embodiment of the present application.

Detailed ways

The following description provides specific application scenarios and requirements of the present application, and is intended to enable those skilled in the art to make and use the contents of the present application. Various partial modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and without departing from the spirit and scope of the present application. application. Therefore, the present application is not to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

Referring to FIG. 1, a reference circuit includes a reference cell (0cell) for writing "0" and a reference cell (1cell) for writing "1", wherein the reference cell for writing "0" includes MTJ0 and transistor M0, One end of the MTJ0 is connected to the reference bit line BL_REF<1>, the other end is connected to the transistor M0, and one end of the transistor M0 is connected to the source line SL. The reference cell (1cell) for writing "1" includes MTJ1 and a transistor M1, one end of the MTJ1 is connected to the reference bit line BL_REF<0>, the other end is connected to the transistor M1, and one end of the transistor M1 is connected to the source line SL .

The reference cell for writing "0" and the reference cell for writing "1" are connected in parallel. When a read operation is performed, the bit line BL_REF<1> and the bit line BL_REF<0> are connected to a high level, and the source line SL Grounding, the reference current IP of the reference cell that writes "0" flows from FL (free layer) to PL (fixed layer), the magnitude of the reference current _IP is V0/(R _{P +} r0), and V0 is written "0""The voltage across the reference cell, R _P is the resistance of MTJ0, and r0 is the resistance of transistor M0. In the same way, the reference current I _AP of the reference cell that writes "1" flows from FL (free layer) to PL (fixed layer), the magnitude of the reference current I _AP is V1/(R _AP +ri), and V1 is "write" The voltage across the reference unit of 0", R _AP is the resistance of MTJ1, r1 is the resistance of transistor M1, the reference current I=0.5 (I _P + I _AP ).

Usually, a set of reference circuits will be used as a reference for devices on multiple bit lines BL. Assuming that there are 2x bit lines BL, the total amount of charge flowing through the reference device is 2x times that of the general device, which makes the total charge in the reference device. The amount is 2x times that of the general device. Since the writing current of the reference cell that writes "1" is inconsistent with the flow direction of the reference current I _AP , this greatly increases the probability of read disturb in 1 cell in the reference device, and the Greatly limits the data retention of the entire MRAM.

The technical solution of the present application provides a read reference circuit, which breaks through the conventional cognition that the reference bit line is connected to a high level and the reference source line is connected to a low level during a read operation, and the reliability is improved by changing the implementation form of the reference circuit. 0cell and 1cell are used in series to make the reference current flow consistent with the data written in MTJ, which solves the problem that MRAM is prone to readdisturb, effectively improves the data storage performance, and at the same time ensures the improved reference circuit and overall array (array) consistency.

The technical solutions of the present application will be described in detail below with reference to the embodiments and the accompanying drawings.

Referring to FIG. 2 , the read reference circuit of the embodiment of the present application includes reference modules 11 , the number of the reference modules 11 may be one or more, and the reference modules 11 are connected in parallel. The embodiment of the present application takes two parallel reference modules as an example for description.

The reference module 11 includes a first reference unit 111 and a second reference unit 112 connected in series, and the write data of the first reference unit 111 and the second reference unit 112 are different, for example, the first reference unit 111 writes "" 0", the second reference unit 112 writes "1", or the first reference unit 111 writes "1", and the second reference unit 112 writes "0". The embodiment of the present application stipulates that when "0" is written, the current flows from the free layer of the MTJ unit to the fixed layer, and when "1" is written, the current flows from the fixed layer of the MTJ unit to the free layer. In other embodiments, it can also be specified that when "0" is written, the current flows from the fixed layer of the MTJ unit to the free layer, and when "1" is written, the current flows from the free layer of the MTJ unit to the fixed layer, and programming is performed according to the actual situation.

The first reference unit 111 in this embodiment of the present application has the same current flow when performing a write operation and a read operation, and the second reference unit 112 also has the same current flow when performing a write operation and a read operation. The cell 111 and the second reference cell 112 are connected in series, so the direction and magnitude of the current flowing through the first reference cell 111 and the second reference cell 112 are the same. The current directions of the first reference unit 111 and the second reference unit 112 are respectively the same during the write operation and the read operation, which can avoid read disturb of the reference unit.

The read reference circuit further includes a first reference bit line BL_REF<1>, a second reference bit line BL_REF<2> and a reference source line SL_REF, the first reference bit line BL_REF<1> is connected to the first reference cell 111, that is, the first reference bit line BL_REF<1> is connected to one end of the reference module 11, and the second reference bit line BL_REF<2> is connected to the second reference unit 112, that is, the second reference unit 112. The reference bit line BL_REF<2> is connected to the other end of the reference block 11 . The reference source line SL_REF is connected to the first reference unit 111 and the second reference unit 112 of each reference module 11 , that is, all reference units share a reference source line SL_REF.

Wherein, one of the first reference bit line BL_REF<1> and the second reference bit line BL_REF<2> is used to output a reference signal, the other is connected to a low level, and the reference source line SL_REF is floating. In this embodiment of the present application, the reference bit line connected to the reference cell written with "0" is used for outputting a reference signal, and the reference bit line connected to the reference cell written with "1" is connected to a low level. In this embodiment of the present application, the first reference unit 111 writes “0”, the first reference bit line BL_REF<1> connected to the first reference unit 111 is used to output a reference signal, and the second reference unit 111 writes "1", and the second reference bit line BL_REF<2> connected to the second reference unit 112 is connected to a low level. In other embodiments, it can also be specified that the first reference unit 111 writes “1”, the first reference bit line BL_REF<1> connected to the first reference unit 111 is connected to a low level, and the second reference The unit 111 writes "0", the second reference bit line BL_REF<2> connected to the second reference unit 112 is used for outputting a reference signal, and the reference source line SL_REF is floating.

In this embodiment of the present application, the connection mode of the first reference bit line BL_REF<1>, the second reference bit line BL_REF<2> and the reference source line SL_REF is designed, so that the first reference unit 111 can be used during write and read operations. The current direction of the reference cell is the same, and the current direction of the second reference cell 112 is also the same during the write operation and the read operation, which avoids writing " The 1″ reference unit has a read disturb phenomenon.

Continuing to refer to FIG. 2 , the first reference cell 111 includes a first MTJ cell (0cell) and a first transistor M1, the first MTJ cell (0cell) is connected to the first reference bit line BL_REF<1>, and writes Both the input current and the reference current I _REF flow from FL (free layer) to PL (pinned layer). The first electrode of the first transistor M1 is connected to the first MTJ cell (0 cell), and the second electrode of the first transistor M1 is connected to the reference source line SL_REF and the second reference cell 112 . In this embodiment of the present application, the first transistor M1 may be a PMOS transistor, the first electrode of the first transistor M1 may be a source electrode, and the second electrode of the first transistor M1 may be a drain electrode.

The second reference cell 112 includes a second MTJ cell (1cell) and a second transistor M2, the second MTJ cell (1cell) is connected to the second reference bit line BL_REF<2> and flows through the second MTJ The direction of the write current and the reference current for the cell (1 cell) is from PL to FL. The first electrode of the second transistor M2 is connected to the second MTJ cell (1 cell), and the second electrode of the second transistor M2 is connected to the reference source line SL_REF and the second electrode of the first transistor M1. In this embodiment of the present application, the second transistor M2 may be a PMOS transistor, the first electrode of the second transistor M2 may be a drain electrode, and the second electrode of the second transistor M2 may be a source electrode.

The read reference circuit of the embodiment of the present application adopts the connection mode of the shared reference source line SL_REF, two reference units are connected in series to form a set of reference modules, and then multiple sets of reference modules are connected in parallel to form a reference module. When writing data, the data written in the reference cell connected to the first reference bit line BL_REF<1> is "0", and the data written in the reference cell connected with the second reference bit line BL_REF<2> The data is "1"; during the read operation, the first reference bit line BL_REF<1> is connected to an amplification module (such as a sense amplifier), the second reference bit line BL_REF<2> is grounded, and the reference source Line SL_REF is floating, when the number of parallel groups is 2, the obtained reference current I _REF is:

I _REF =2V/(R _P +R _AP +2×r);

Wherein, V is the total voltage of the first reference cell 111 and the second reference cell 112, R _P is the resistance of the first MTJ cell (0 cell), and R _AP is the second MTJ cell (1 cell) ), and r is the resistance of the first transistor M1 and the second transistor M2. The size of the I _REF is between _{IP and I AP shown} in FIG. 1 .

For the first MTJ cell (0 cell) of the first reference bit line BL_REF<1>, the current direction is from FL to PL, which is the same as the current direction of writing data "0"; for the second reference bit For the second MTJ cell (1cell) of line BL_REF<2>, the current direction is from PL to FL, which is the same as the current direction of writing data "1", thus avoiding the possibility of read disturb in the reference cell.

Referring to FIG. 3 , an embodiment of the present application further provides a read operation circuit, including a reference circuit 1 , a data path 2 and an amplification circuit 3 . Wherein, the reference circuit 1 is used to provide a reference signal, the data path 2 is used to provide the data to be read and output the data signal, the amplifying circuit 3 is used to compare the data signal and the reference signal, and obtain Read the result.

The reference circuit 1 includes one or more reference modules 11 connected in parallel, the reference module 11 includes two first reference cells 111 and second reference cells 112 that are connected in series and have different written data, and the first reference cell 111. The current direction of the second reference unit 112 is the same when the write operation and the read operation are performed respectively, which can avoid the possibility of read disturb in each reference unit, and effectively improve the data storage performance of the MRAM.

The reference circuit 1 further includes a first reference bit line BL_REF<1>, a second reference bit line BL_REF<2> and a reference source line SL_REF, the first reference bit line BL_REF<1> is connected to the first reference cell 111 , the second reference bit line BL_REF<2> is connected to the second reference unit 112 , and the reference source line SL_REF is connected to the first reference unit 111 and the second reference unit 112 . Wherein, one of the first reference bit line BL_REF<1> and the second reference bit line BL_REF<2> is connected to the amplifying circuit 3, the other is connected to a low level, and the reference source line SL_REF is floating null. In the embodiment of the present application, the reference bit line connected to the reference cell written with "0" is connected to the amplifier circuit 3, and the reference bit line connected to the reference cell written with "1" is connected to the low level, that is, the first reference bit line BL_REF<1> is connected to the amplifying circuit 3 for outputting a reference signal, the second reference bit line BL_REF<2> is connected to a low level to provide a low level, and the reference source line SL_REF has no current to pass through, so that the read The reference circuit is a series circuit to ensure that the reference current flows from the first reference unit 111 to the second reference unit 112 .

Continuing to refer to FIG. 3 , the first reference cell 111 includes a first MTJ cell (0 cell) and a first transistor M1, the first MTJ cell is connected to the first reference bit line BL_REF<1>, and stores data “0” ", the first electrode of the first transistor M1 is connected to the first MTJ cell (0 cell), and the second electrode of the first transistor M1 is connected to the reference source line SL_REF and the second reference cell 112 . The first transistor M1 may be a PMOS transistor, the first electrode of the first transistor M1 may be a source electrode, and the second electrode of the first transistor M1 may be a drain electrode.

The second reference unit 112 includes a second MTJ unit (1cell) and a second transistor M2, the second MTJ unit (1cell) is connected to the second reference bit line BL_REF<2>, and stores data "1", The second electrode of the second transistor M2 is connected to the reference source line SL_REF and the second electrode of the first transistor M1. The second transistor M2 may be a PMOS transistor, the first electrode of the second transistor M2 may be the drain, and the second electrode of the second transistor M2 may be the source.

The data path 2 includes a data storage unit 21. The number of the data storage unit 21 can be multiple, and is used to store the same or different data. One end of the data storage unit 21 is connected to the bit line BL, and the other end is connected to the source. Line SL, the source line SL is connected to the amplifying circuit 3 .

The data storage unit 21 includes an MTJ cell (cell) and a transistor M0, a free layer (FL) of the MTJ cell (cell) is connected to the bit line BL, and a fixed layer (PL) of the MTJ cell (cell) is connected to the first electrode of the transistor M0, and the second electrode of the transistor M0 is connected to the source line SL, wherein the transistor M0 may be a PMOS, and the first electrode of the transistor M0 may be a source, so The second electrode of the transistor M0 may be a drain electrode.

The amplifying circuit 3 is connected to the reference circuit 1 and the data path 2 . Specifically, the amplifying circuit 3 is connected to the first reference bit line BL_REF<1> of the reference circuit 1 and the data path 2 . The bit line BL is used to compare the data signal of the data path 2 with the reference signal of the reference circuit 1, and obtain a read result. In some embodiments, the data signal is the output current I _cell of the data path 2 , and the reference signal is the output current I _REF of the reference circuit 1 . If the output current I _cell is greater than the output current I _REF , then The read result is "1"; if the output current I _cell is less than the output current I _EF , the read result is "0".

In the embodiment of the present application, the reference bit line connected to the reference cell written with "0" in the read reference circuit outputs a reference signal, the reference bit line connected to the reference cell written with "1" is connected to a low level, and the two reference The source line shared by the cells is floating, so that the reference cells are connected in series, and at the same time, the direction of the write operation current and the read operation current of each reference cell is the same, which solves the problem of the write current and the reference current of the reference cell due to writing "1". The read disturb problem caused by the inconsistent flow direction greatly improves the read performance of the read reference circuit.

Embodiments of the present application further provide a storage unit including the above-mentioned read operation circuit.

In conclusion, after reading the contents of this application, those skilled in the art can understand that the foregoing contents of the application may be presented by way of example only, and may not be limiting. Although not explicitly described herein, it will be understood by those skilled in the art that this application is intended to cover various reasonable changes, improvements and modifications to the embodiments. Such changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.

It should be understood that the term "and/or" as used in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intervening elements. It should also be understood that the terms "comprising", "comprising", "including" or "comprising", when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements and/or components, It does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

It will also be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference signs refer to the same elements throughout the specification.

Furthermore, this specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes illustrated are foreseeable due to, for example, manufacturing techniques and/or tolerances. Thus, example embodiments should not be construed as limited to the shapes of regions shown herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched area shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device nor to limit the scope of example embodiments.

Claims (14)

1. A read reference circuit, comprising:

one or more reference modules connected in parallel;

the reference module comprises a first reference unit and a second reference unit which are connected in series and different in write data;

the current directions of the first reference unit and the second reference unit are the same during the writing operation and the reading operation respectively.

2. The read reference circuit of claim 1, further comprising:

a first reference bit line connected to the first reference cell;

a second reference bit line connected to the second reference cell;

a reference source line connecting the first reference cell and the second reference cell;

one of the first reference bit line and the second reference bit line outputs a reference signal, the other one of the first reference bit line and the second reference bit line is connected to a low level, and the reference source line is floating.

3. The read reference circuit of claim 2, wherein the first reference cell writes a 0, the second reference cell writes a 1, the first reference bit line outputs a reference signal, and the second reference bit line is tied low.

4. The read reference circuit of claim 2, wherein the first reference cell comprises:

a first MTJ cell connected to the first reference bit line;

a first transistor having a first electrode connected to the first MTJ cell and a second electrode connected to the reference source line and the second reference cell.

5. The read reference circuit of claim 4, wherein the second reference cell comprises:

a second MTJ cell connected to the second reference bit line;

a second transistor having a first electrode connected to the second MTJ cell and a second electrode connected to the reference source line and a second electrode of the first transistor.

6. A read operation circuit, comprising:

the reading reference circuit is used for providing a reference signal and comprises one or more parallel reference modules, each reference module comprises a first reference unit and a second reference unit which are connected in series and different in written data, and the current directions of the first reference unit and the second reference unit are the same when the first reference unit and the second reference unit are respectively subjected to writing operation and reading operation;

a data path providing data to be read and outputting a data signal;

and the amplifying circuit is connected with the reference circuit and the data path and used for comparing the data signal with the reference signal and obtaining a reading result.

7. The read operation circuit of claim 6, wherein the reference circuit further comprises:

a first reference bit line connected to the first reference cell;

a second reference bit line connected to the second reference cell;

a reference source line connecting the first reference cell and the second reference cell;

one of the first reference bit line and the second reference bit line is connected with the amplifying circuit, the other one of the first reference bit line and the second reference bit line is connected with a low level, and the reference source line is floating.

8. The read operation circuit of claim 7, wherein the first reference cell writes a 0, the second reference cell writes a 1, the first reference bit line is connected to the amplifying circuit, and the second reference bit line is connected to a low level.

9. The read operation circuit of claim 7, wherein the first reference cell comprises:

a first MTJ cell connected to the first reference bit line;

a first transistor having a first electrode connected to the first MTJ cell and a second electrode connected to the reference source line and the second reference cell.

10. The read operation circuit of claim 9, wherein the second reference cell comprises:

a second MTJ cell connected to the second reference bit line;

a second transistor having a first electrode connected to the second MTJ cell and a second electrode connected to the reference source line and a second electrode of the first transistor.

11. The read operation circuit of claim 6, wherein the data path comprises a data storage unit, one end of the data storage unit is connected with a bit line, the other end of the data storage unit is connected with a source line, and the source line is connected with the amplifying circuit.

12. The read circuit of claim 6, wherein the data signal is an output current of the data path and the reference signal is an output current of the reference circuit.

13. The read operation circuit of claim 6, wherein the amplification circuit comprises a sense amplifier.

14. A memory cell comprising the read operation circuit of any one of claims 6 to 13.

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