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CN114664344A - Magnetic random access memory, memory array and electronic equipment - Google Patents

Magnetic random access memory, memory array and electronic equipment Download PDF

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Publication number
CN114664344A
CN114664344A CN202011541239.1A CN202011541239A CN114664344A CN 114664344 A CN114664344 A CN 114664344A CN 202011541239 A CN202011541239 A CN 202011541239A CN 114664344 A CN114664344 A CN 114664344A
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magnetic
data
tunnel junction
coupled
unit
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Inventor
夏文斌
王韬
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1695—Protection circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1697—Power supply circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

A magnetic random access memory, a memory array, and an electronic device, the magnetic random access memory comprising: the drive signal module is used for providing a read signal; the storage array comprises a plurality of storage units which are arranged in an array, wherein each storage unit comprises a magnetic tunnel junction, and each magnetic tunnel junction comprises a magnetic fixed layer and a magnetic free layer which are oppositely arranged; a data unit for loading a read signal and outputting a data voltage; the reference unit comprises a parallel state reference unit and an anti-parallel state reference unit; the magnetic free layer of the parallel state reference unit is coupled with the magnetic fixed layer of the anti-parallel state reference unit to form a reference output end, and the reference unit is used for loading a read signal and outputting a reference voltage through the reference output end; and the comparison circuit is used for reading the data of the data unit according to the relative size of the data voltage and the reference voltage. The embodiment of the invention is beneficial to reducing the possibility of the inversion of the resistance state of the reference unit during the reading operation, ensuring the reliability of the reference unit and improving the performance of the MRAM.

Description

Magnetic random access memory, memory array and electronic equipment
Technical Field
Embodiments of the present invention relate to the field of circuits, and in particular, to a magnetic random access memory, a memory array and an electronic device.
Background
Magnetic Random Access Memory (MRAM) is a non-volatile Magnetic Random Access Memory, and MRAM devices that possess the high-speed read-write capability of Static Random Access Memory (SRAM), as well as the high integration of Dynamic Random Access Memory (DRAM), and can be written to repeatedly, essentially indefinitely, and is a "full-kinetic" solid-state Memory. The magnetic random access memory is considered to be a 'universal' processor which is most widely applied in the future due to the advantages of high read-write speed, long service life, non-volatility and the like, and is expected to dominate the next generation memory market.
In an MRAM device, data is stored by the magnetic state of a memory element. An MRAM cell generally includes a transistor and a Magnetic Tunnel Junction (MTJ) that together form a memory cell. The MTJ structure includes at least two magnetic layers and an insulating layer for isolating the two magnetic layers. The two electromagnetic layers can maintain two magnetic polarization fields separated by an insulating layer, one of which is a fixed magnetic layer whose polarization direction is fixed, and the other of which is a freely rotating magnetic layer whose polarization direction can be changed by a change in an external field. When the polarization directions of the two electromagnetic layers are parallel, the tunneling current flowing through the MTJ structure has a maximum value, and the MTJ structure has a low cell resistance: when the polarization directions of the two magnetic layers are anti-parallel, the tunneling current flowing through the MTJ structure has a minimum value, and the unit resistance of the MTJ structure is high. The information is read by measuring the resistance of the MRAM cell, which is the working principle of the MTJ structure.
However, currently, reliability of MRAM needs to be improved.
Disclosure of Invention
Embodiments of the present invention provide a magnetic random access memory, a memory array, and an electronic device, which reduce the possibility of the inversion of the resistance state of a reference cell during a read operation, and improve the reliability of an MRAM.
To solve the above problems, an embodiment of the present invention provides a magnetic random access memory, including: the driving signal module is used for providing a reading signal; the storage array comprises a plurality of storage units which are arranged in an array, wherein each storage unit comprises a magnetic tunnel junction, and each magnetic tunnel junction comprises a magnetic fixed layer and a magnetic free layer which are oppositely arranged; defining a storage unit of data to be read as a data unit, wherein the data unit is used for loading the read signal and outputting a data voltage; defining a memory cell used as a data reading reference as a reference cell, wherein the reference cell comprises a parallel state reference cell and an anti-parallel state reference cell; the magnetic free layer of the parallel state reference unit is coupled with the magnetic fixed layer of the anti-parallel state reference unit to form a reference output end, and the reference unit is used for loading the read signal and outputting a reference voltage through the reference output end; and the comparison circuit is used for reading the data of the data unit according to the relative size of the data voltage and the reference voltage.
Accordingly, an embodiment of the present invention further provides a memory array applied to a magnetic random access memory, where the magnetic random access memory includes: a drive signal module for providing a read signal to the memory array; the comparison circuit is used for reading the data of the storage array according to the relative size of the data voltage and the reference voltage output by the storage array; the storage array comprises: the storage unit comprises a plurality of storage units which are arranged in an array, wherein each storage unit comprises a magnetic tunnel junction, and each magnetic tunnel junction comprises a magnetic fixed layer and a magnetic free layer which are oppositely arranged; defining a storage unit of data to be read as a data unit, wherein the data unit is used for loading the read signal and outputting the data voltage; defining a memory cell used as a data reading reference as a reference cell, wherein the reference cell comprises a parallel state reference cell and an anti-parallel state reference cell; and the magnetic free layer of the parallel state reference unit is coupled with the magnetic fixed layer of the anti-parallel state reference unit to form a reference output end, and the reference unit is used for loading the read signal and outputting the reference voltage through the reference output end.
Correspondingly, an embodiment of the present invention further provides an electronic device, including: the embodiment of the invention provides a magnetic random access memory.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the magnetic random access memory provided by the embodiment of the invention, the reference unit comprises a Parallel state reference unit and an Anti-Parallel state reference unit, a magnetic free layer of the Parallel state (Parallel, P-state) reference unit is coupled with a magnetic fixed layer of the Anti-Parallel state (Anti-Parallel, AP-state) reference unit to form a reference output end, the reference unit is used for loading the read signal and outputting a reference voltage through the reference output end; in MRAM, the memory cell is written to a high resistance state (R)H) Or the direction of the current in the antiparallel state is the same as the direction of the magnetic pinned layer pointing to the magnetic free layer, and the memory cell is written to the low resistance state (R)L) Or the direction of the current in the parallel state is consistent with the direction of the magnetic free layer pointing to the magnetic pinned layer, in the embodiment of the present invention, the magnetic free layer of the parallel state reference unit is coupled to the magnetic pinned layer of the antiparallel state reference unit to form a reference output terminal, so that, during a read operation, the direction of the read current passing through the antiparallel state reference unit is consistent with the direction of the magnetic pinned layer pointing to the magnetic free layer, the direction of the read current passing through the parallel state reference unit is consistent with the direction of the magnetic free layer pointing to the magnetic pinned layer, that is, the direction of the read current passing through the antiparallel state reference unit is consistent with the direction of the current of Write 1(Write 1), and the direction of the read current passing through the parallel state reference unit is consistent with the direction of the current of Write 0(Write 0), thereby ensuring that after a long-time read operation, the resistance states of the antiparallel state reference unit and the parallel state reference unit are not easy to flip, the probability of the inversion of the resistance state of the reference unit during the reading operation is reduced, a more reliable reference resistor is correspondingly provided for the data reading of the data unit, the reliability of the reference unit is ensured, the data reading accuracy of the MRAM is further improved, and the reliability of the MRAM is correspondingly improved.
In the memory array provided by the embodiment of the invention, the reference unit comprises a parallel state reference unit and an anti-parallel state reference unit, wherein a magnetic free layer of the parallel state reference unit is coupled with a magnetic fixed layer of the anti-parallel state reference unit to form a reference output end, and the reference unit is used for loading the read signal and outputting the reference voltage through the reference output end; therefore, during the reading operation, the direction of the reading current passing through the antiparallel state reference unit is consistent with the direction of the magnetic fixed layer pointing to the magnetic free layer, the direction of the reading current passing through the parallel state reference unit is consistent with the direction of the magnetic free layer pointing to the magnetic fixed layer, that is, the direction of the reading current passing through the antiparallel state reference unit is consistent with the direction of the current of the write 1, and the direction of the reading current passing through the parallel state reference unit is consistent with the direction of the current of the write 0, so as to ensure that after the long-time reading operation, the resistance states of the antiparallel state reference unit and the parallel state reference unit are not easy to turn over, reduce the possibility of the turning over of the resistance state of the reference unit during the reading operation, correspondingly provide more reliable reference resistance for the data reading of the data unit, ensure the reliability of the reference unit, and further improve the data reading accuracy of the MRAM, the reliability of the MRAM is accordingly improved.
The electronic device provided by the embodiment of the invention comprises the magnetic random access memory, the probability of the inversion of the resistance state of the reference unit in the magnetic random access memory during the reading operation is low, a more reliable reference resistance is correspondingly provided for the data reading of the data unit, the reliability of the reference unit is ensured, the data reading accuracy of the MRAM and the reliability of the MRAM are further improved, and correspondingly, the performance of the electronic device provided by the embodiment of the invention is also improved, for example: the data reading accuracy is improved, and the user experience and the sensitivity are optimized.
Drawings
FIG. 1 is a diagram of a MRAM architecture;
FIGS. 2 to 4 are schematic structural diagrams of an embodiment of a magnetic random access memory according to the present invention;
FIG. 5 is a diagram of another embodiment of a MRAM in accordance with the present invention.
Detailed Description
As is known in the art, reliability of MRAM is to be improved.
It has been analyzed that in the standard MRAM reference resistance read strategy, data reading is performed using a reference cell in which a plurality of magnetic tunnel junctions are in an antiparallel state (i.e., a high resistance state) and a reference cell in a parallel state (i.e., a low resistance state) as references. Generally, the number of times the reference cell is read is much greater than the number of times the data cell is read. If no special processing is performed, after a long-time reading operation, the resistance state of the reference cell is easy to be inverted, so that the reference resistance value is changed, the data reading error rate is rapidly increased, and the reliability of the MRAM is reduced.
The reasons why the reliability of MRAM needs to be improved are now analyzed in conjunction with a magnetic random access memory. FIG. 1 is a diagram of a magnetic random access memory.
As shown in fig. 1, the magnetic random access memory includes: a drive signal module 16 for providing a read signal; the storage array comprises a plurality of storage units arranged in an array, wherein each storage unit comprises a magnetic tunnel junction 10, and each magnetic tunnel junction 10 comprises a magnetic fixed layer 101 and a magnetic free layer 102 positioned on the magnetic fixed layer 101; defining a memory cell of data to be read as a data cell 11, defining a memory cell used as a data read reference as a reference cell 12, wherein the reference cell 12 comprises a high resistance state (RH) reference cell 12H and a low resistance state (RL) reference cell 12L, and the magnetic free layers 102 of the high resistance state reference cell 12H and the low resistance state reference cell 12L are coupled to form a reference output end 13A; a load circuit 14 coupled to the data unit 11 and to a reference output 13A of the reference unit 13; the load circuit 14 is used for converting the reading current of the data unit 11 into a data voltage Vdata and converting the reading current of the reference unit 13 into a reference voltage Vref; and a comparison circuit 15 comprising a first input terminal 151, a second input terminal 152 and an output terminal 153, wherein the first input terminal 151 is coupled to the data cell 11, the second input terminal 152 is coupled to the reference output terminal 13A, the comparison circuit 15 is configured to read information of the data cell 11 according to relative magnitudes of the data voltage Vdata and the reference voltage Vref, and the output terminal 153 outputs a comparison result signal.
As shown by the direction of the dotted arrow in fig. 1, when reading the magnetic random access memory, a read current firstly passes through the magnetic free layer 102 of the MTJ 10 and then passes through the magnetic reference layer 101, the read current is opposite to the current direction of the Write 1(RH)) of the high-resistance state reference cell 12H, that is, the same as the Write current direction for writing the high-resistance state reference cell 12H from the high-resistance state to the low-resistance state, and in a data read state for a long time, the risk of the resistance state of the MTJ 10 in the high-resistance state reference cell 12H flipping is high, that is, the MTJ 10 in the high-resistance state reference cell 12H is easily flipped from the anti-parallel (AP) state to the parallel (P) state, so that the reference resistance value changes, the accuracy of MRAM reading data decreases, and the reliability of the MRAM decreases.
One way to optimize the above problem is to set the bit line voltage Vread (REF _ BL) of the reference cell lower than the bit line voltage Vread (BL) of the data cell during a read operation. Since the data writing usually requires a large writing current, the reading current of the reference cell is reduced after the reference bit line voltage is reduced, and the risk of the resistance state in the high resistance state reference cell being inverted is reduced.
However, this does not solve the problem of the inversion of the resistance state of the reference cell, which still has a certain probability of inversion. Furthermore, this also increases the complexity and difficulty of the circuit design.
In order to solve the above technical problem, an embodiment of the present invention provides a magnetic random access memory, in which a magnetic free layer of a parallel state reference unit is coupled to a magnetic pinned layer of an anti-parallel state reference unit to form a reference output terminal, so that, during a read operation, a read current direction passing through the anti-parallel state reference unit is consistent with a direction of the magnetic pinned layer pointing to the magnetic free layer, and a read current direction passing through the parallel state reference unit is consistent with a direction of the magnetic free layer pointing to the magnetic pinned layer, that is, a read current direction passing through the anti-parallel state reference unit is consistent with a current direction of write 1, and a read current direction passing through the parallel state reference unit is consistent with a current direction of write 0, so as to ensure that resistance states of the anti-parallel state reference unit and the parallel state reference unit are not easily flipped after a long-time read operation, and reduce a possibility that a resistance state of the reference unit is flipped during a read operation, correspondingly, more reliable reference resistance is provided for data reading of the data unit, the reliability of the reference unit is guaranteed, and the data reading accuracy and the reliability of the MRAM are improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below. Fig. 2 to 4 are schematic structural diagrams of an mram according to an embodiment of the present invention.
In this embodiment, the Magnetic Random Access Memory (MRAM)200 includes: a driving signal module 180 for providing a read signal; the memory array 400 comprises a plurality of memory cells arranged in an array, wherein each memory cell comprises a Magnetic Tunnel Junction (MTJ)100, each magnetic tunnel junction 100 comprises a magnetic fixed layer (Pinned layer)1001 and a magnetic Free layer (Free layer)1002 which are arranged oppositely, the memory cell for data to be read is defined as a data cell 110, and the data cell 110 is used for loading a read signal and outputting a data voltage Vdata; defining a memory cell used as a data reading reference as a reference cell 120, where the reference cell 120 includes an Anti-Parallel (AP) reference cell 120H and a Parallel (P) reference cell 120L, a magnetic free layer 1002 of the Parallel reference cell 120L is coupled to a magnetic fixed layer 1001 of the Anti-Parallel reference cell 120H to form a reference output terminal 120A, and the reference cell 120 is used for loading a reading signal and outputting a reference voltage Vref through the reference output terminal 120A; the comparison circuit 150 is used for reading data of the data unit 110 according to the relative magnitude of the data voltage Vdata and the reference voltage Vref.
In the present embodiment, "coupled" refers to direct connection or indirect connection, and "coupled" in the following description is not described one by one.
The driving signal module 180 is used to provide a read signal to the memory array 400 so that the memory array 400 outputs data based on the read signal. In this embodiment, the driving signal module 180 is used for providing a bit line voltage, the reference unit 120 is used for loading the bit line voltage and outputting a reference current through the reference output terminal 120A, and the data unit 110 is used for loading the bit line voltage and outputting a data current.
In this embodiment, the magnetic random access memory 200 further includes: a load circuit 140 coupled to the data unit 110 and to the reference output 120A; the load circuit 140 is used for converting the read current of the data cell 110 into the data voltage Vdata and converting the read current of the reference cell 120 into the reference voltage Vref.
In this embodiment, the driving signal module 180 includes: a clamp circuit 160 coupled to the load circuit 140, the clamp circuit 160 being used for clamping the bit line voltages of the data cell 110 and the reference cell 120; the bit line selection circuit 170 has one end coupled to the clamping circuit 160 and the other end coupled to the data cell 110 and the reference output 120A of the reference cell 120, respectively, and the bit line selection circuit 170 is adapted to select the data cell 110 and the reference cell 120 to be read.
The clamp circuit 160 is used for providing the bit line voltage to the data cell 110 and the reference cell 120, and for clamping the bit line voltage of the data cell 110 and the bit line voltage of the reference cell 120, so as to limit the bit line voltage of the data cell 110 and the reference cell 120 within a preset range, so as to prevent the bit line voltage of the data cell 110 and the reference cell 120 from being too large, which may cause the magnetic tunnel junction 100 of the data cell 110 and the reference cell 120 to be damaged, thereby protecting the data cell 110 and the reference cell 120.
In this embodiment, the clamp circuit 160 includes an NMOS transistor, a drain of the NMOS transistor is coupled to the load circuit 140, a source of the NMOS transistor is coupled to the bit line selection circuit 170, and a gate of the NMOS transistor is used for loading the clamp control signal VClamp.
In the read operation, the voltage applied to the gate of the NMOS transistor is: the sum of the threshold voltage of the NMOS transistor and the bit line voltage ensures that the bit line voltage loaded on the data unit 110 or the reference unit 120 is the preset bit line voltage, and when the voltage loaded on the gate of the NMOS transistor is greater than the preset bit line voltage, the channel of the NMOS transistor is turned off, thereby protecting the circuit.
As shown in fig. 3, in an implementation, the clamp circuit 160 may include a first NMOS transistor N1 and a second NMOS transistor N2. The drain of the first NMOS transistor N1 is coupled to the first output terminal of the load circuit 140, the gate of the first NMOS transistor N1 is coupled to the clamp control signal VClamp, the drain of the second NMOS transistor N2 is coupled to the second output terminal of the load circuit 140, the gate of the second NMOS transistor N2 is adapted to be coupled to the clamp control signal VClamp, and the first NMOS transistor N1 and the second NMOS transistor N2 are adapted to clamp the bit line voltages of the data unit 110 and the reference unit 120 under the control of the same clamp control signal VClamp, so as to avoid the damage of the data unit 110 and the reference unit 120 due to the excessive bit line voltages caused by misoperation and other factors.
In a particular implementation, the bit line selection circuit 170 may include a first bit line selection switch MUXdataAnd a second bit line selection switch MUXrefFirst bit line select switch MUXdataThe first connection terminal of the first NMOS transistor N1, the first bit line selection switch MUXdataIs coupled to the data unit 110, the first bit line select switch MUXdataFor selecting the data unit 110 to be read.
In a specific implementation, the second bit line selection switch MUXrefThe first connection terminal of the second NMOS transistor N2, and the second bit line selection switch MUXrefIs coupled to the reference cell 120, a second bit line selection switch MUXrefFor selecting the reference cell 120 to be read. In particular, the second bit line selection switch MUXrefIs coupled to the reference output 120A.
The storage unit is used for storing data. As shown in fig. 4, the memory array 400 includes a plurality of memory cells arranged in a matrix. The plurality of memory cells are repeating cells, i.e., the plurality of memory cells have the same structure.
Therefore, the anti-parallel state reference cell 120H or the parallel state reference cell 120L has the same structure as the data cell 110, which is beneficial to improving the accuracy of the reference cell 120 for being used as a reference for reading data.
In a specific implementation, the magnetic tunnel junction 100 in the memory cell is used to store data. Specifically, when the magnetic directions of the magnetic pinned layer 1001 and the magnetic free layer 1002 are parallel, the memory cell is in a parallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a maximum value, and the magnetic tunnel junction 100 is in a low resistance state (RL); when the magnetic directions of the magnetic pinned layer 1001 and the magnetic free layer 1002 are antiparallel, the memory cell is in an antiparallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a minimum value, and the magnetic tunnel junction 100 is in a high resistance state (RH).
The magnetization direction of the magnetic pinned layer 1001 is fixed for use as a magnetization direction reference layer for the magnetic free layer 1002. The magnetization direction of the magnetic free layer 1002 has two stable orientations, parallel or opposite to the magnetization direction of the magnetic pinned layer 1001, respectively, thereby enabling the magnetic tunnel junction 100 to be in a low resistance state or a high resistance state. The materials of the magnetic free layer 1002 and the magnetic pinned layer 1001 are both ferromagnetic metal materials, such as: CoFeB or CoFe.
In this embodiment, the magnetic tunnel junction 100 further includes: a Tunneling Barrier Layer (Tunneling Barrier) 1003 located between the magnetic pinned Layer 1001 and the magnetic free Layer 1002. The tunneling barrier layer 1003 is used to achieve electrical isolation between the magnetic fixed layer 1001 and the magnetic free layer 1002. The tunneling barrier layer 1003 is made of an insulating material, for example: MgO, SrO, BaO, RaO, SiO2、Al2O3、HfO2、NiO、GdO、Ta2O5、MoO2、TiO2Or WO2。
As an example, the magnetic tunnel junction 100 is Bottom-Pinned (Bottom-Pinned), and the magnetic tunnel junction 100 includes a magnetically Pinned layer 1001 and a magnetically free layer 1002 on the magnetically Pinned layer 1001.
The memory cell also includes a select transistor N0 coupled to the magnetic tunnel junction 100, the gate of the select transistor N0 being coupled to the word line WL (word line). The select transistor N0 is adapted to be turned on or off under the control of a signal to turn on the word line WL to read the data stored in the magnetic tunnel junction 100. In this embodiment, the selection transistor N0 is an NMOS transistor. As shown in fig. 4, in the memory array 400, a plurality of memory cells are arranged in an array, and the gate of the selection transistor of each memory cell is coupled to a corresponding word line WL < n >, where n is an integer greater than or equal to 0.
In this embodiment, the magnetic tunnel junction 100 is magnetically pinned at the bottom, accordingly, in the data cell 110, the drain of the select transistor N0 is coupled to the magnetic pinned layer 1002 of the magnetic tunnel junction 100, and the source sl (source line) of the select transistor N0 is grounded VSS.
In a specific implementation, the magnetic random access memory 200 uses the magnetic tunnel junction 100 in at least one anti-parallel reference cell 120H and at least one parallel reference cell 120L to form a standard resistance, and compares the data cell 110 with the standard resistance to determine whether the data cell 110 is in a high resistance state or a low resistance state, thereby implementing data reading of the data cell 110.
The data cell 110 is data to be read, and the resistance state of the magnetic tunnel junction 100 in the data cell 110 is to be confirmed.
The reference unit 120 is adapted to store and output reference data for reference to read the data of the data unit 110. The reference output terminal 120A is used for outputting a reference signal for data reading of the data unit 110. Specifically, in a read operation, the reference unit 120 outputs a reference signal through the reference output terminal 120A based on the read signal provided by the driving signal module 180.
Specifically, the reference unit 120 includes at least one anti-parallel state (i.e., high resistance state (RH)) reference unit 120H and at least one parallel state (i.e., low resistance state (RL)) reference unit 120L, where the magnetic tunnel junction 100 in the at least one anti-parallel state reference unit 120H and the at least one parallel state reference unit 120L form a standard resistance, and data reading of the data unit 110 is implemented by comparing the data unit 110 with the standard resistance to determine whether the data unit 110 is in the high resistance state or the low resistance state.
In this embodiment, the antiparallel-state reference unit 120H means that the magnetic tunnel junction 100 in the antiparallel-state reference unit 120H is in an Antiparallel (AP) state, and the magnetic direction of the magnetic free layer 1002 is antiparallel to the magnetic direction of the magnetic pinned layer 1001; the parallel state reference cell 120L means that the magnetic tunnel junction 100 in the parallel state reference cell 120L is in the parallel (P) state, and the magnetic direction of the magnetic free layer 1002 is parallel to the magnetic direction of the magnetic pinned layer 1001.
As an example, in the reference cells 120, the number of the antiparallel state reference cells 120H and the number of the parallel state reference cells 120L are the same, and the number of the antiparallel state reference cells 120H and the number of the parallel state reference cells 120L are both y; wherein y is a positive integer. By making the number of the anti-parallel reference cells 120H and the number of the parallel reference cells 120L the same, it is advantageous to reduce the complexity of the circuit design.
In the present embodiment, for convenience of illustration and explanation, the reference cell 120 includes an antiparallel-state reference cell 120H and a parallel-state reference cell 120L as an example. However, the reference cells 120 include the antiparallel state reference cells 120H and the parallel state reference cells 120L in a number not limited thereto. In other embodiments, the reference cells may include a plurality of antiparallel state reference cells and a plurality of parallel state reference cells, and the number of antiparallel state reference cells and the number of parallel state reference cells may be different.
In the MRAM, a writing current (writing "0") direction for writing the magnetic tunnel junction 100 from a high resistance state (i.e., an antiparallel state) to a low resistance state (i.e., a parallel state) coincides with a direction in which the magnetic free layer 1002 points to the magnetic pinned layer 1001, and a writing current (writing "1") direction for writing the magnetic tunnel junction 100 from a low resistance state to a high resistance state coincides with a direction in which the magnetic pinned layer 1001 points to the magnetic free layer 1002.
In this embodiment, the magnetic pinned layer 1001 of the anti-parallel reference cell 120H is coupled to the magnetic free layer 1002 of the parallel reference cell 120L to form the reference output 120A, the magnetic tunnel junctions 100 in the anti-parallel reference cell 120H and the parallel reference cell 120L are coupled to the driving signal module 180 in different ways, so that during a read operation, the direction of the read current through the anti-parallel state reference cell 120H coincides with the direction of the magnetic pinned layer 1001 pointing to the magnetic free layer 1002, and the direction of the read current through the parallel state reference cell 120L coincides with the direction of the magnetic free layer 1002 pointing to the magnetic pinned layer 1001, the direction of the read current through the anti-parallel state reference cell 120H coincides with the direction of the current for writing 1, the direction of the read current through the parallel state reference cell 120L coincides with the direction of the current for writing 0, further, it is ensured that after a long time of read operation, the resistance states of the anti-parallel state reference cell 120H and the parallel state reference cell 120L are not easily turned over.
As an example, the magnetic tunnel junction 100 is Bottom-pinned, the magnetic tunnel junction 100 includes a magnetically pinned layer 1001 and a magnetically free layer 1002 on the magnetically pinned layer 1001.
Accordingly, in this embodiment, the magnetic free layer 1001 of the data cell 110 is coupled to the load circuit 140.
Specifically, the drain of select transistor N0 in data cell 110 is coupled to the magnetically pinned layer 1001 of the magnetic tunnel junction 100, and the source of select transistor N0 in data cell 110 is coupled to ground VSS.
Accordingly, in the parallel state reference cell 120L of the present embodiment, the drain of the select transistor N0 is coupled to the magnetically pinned layer 1001 of the magnetic tunnel junction 100, the source REF _ SL <0> of the select transistor N0 is coupled to the ground VSS, and the magnetic free layer 1002 of the magnetic tunnel junction 100 is used to form the reference output terminal 120A.
In this embodiment, in the anti-parallel reference cell 120H, the drain of the select transistor N0 is coupled to the magnetically pinned layer 1001 of the magnetic tunnel junction 100, the source REF _ SL <1> of the select transistor N0 is used to form the reference output 120A, and the magnetic free layer 1002 of the magnetic tunnel junction 100 is coupled to ground VSS.
In the present embodiment, during the read operation, the direction of the read current is along the direction from the reference output terminal 120A to the ground terminal VSS. Specifically, in the present embodiment, in the parallel-state reference unit 120L, the direction of the read current passing through the magnetic tunnel junction 100 is the same as the direction of the magnetic free layer 1002 pointing to the magnetic pinned layer 1001, that is, the same as the direction of the current writing the magnetic tunnel junction 100 in the low resistance state or the parallel state, and the magnetic tunnel junction 100 in the parallel-state reference unit 120L is already in the low resistance state, so that the resistance state of the parallel-state reference unit 120L can be prevented from being inverted;
in the antiparallel-state reference cell 120H, the direction of the read current passing through the magnetic tunnel junction 100 coincides with the direction in which the magnetic pinned layer 1001 points to the magnetic free layer 1002, that is, the same direction as the current for writing the magnetic tunnel junction 100 in the high-resistance state or antiparallel state, and the magnetic tunnel junction 100 in the antiparallel-state reference cell 120H is already in the high-resistance state, so that the resistance state of the antiparallel-state reference cell 120H can be prevented from being inverted.
The load circuit 120 serves to convert the read current of the data cell 110 into the data voltage Vdata and to convert the read current of the reference cell 120 into the reference voltage Vref, so that the comparison circuit 150 can read information of the data cell 110 by comparing the relative magnitudes of the data voltage Vdata and the reference voltage Vref.
The load circuit 140 includes an input terminal (not shown), a first output terminal (not shown) and a second output terminal (not shown), the input terminal of the load circuit 140 is coupled to the power supply VDD, the first output terminal is coupled to the data unit 110, and the second output terminal is coupled to the reference output terminal 120A.
As shown in fig. 2, when data reading is not performed, the data voltage Vdata converted by the load circuit 140 is equal to the reference voltage Vref; when data is read, if the resistance of the data unit 110 is in the low resistance state RL, the data voltage Vdata at the access point between the comparison circuit 150 and the load circuit 140 is pulled low due to the resistance of the low resistance state RL, and the data voltage Vdata is reduced and shows a trend of decreasing compared with the state without data reading, and the comparison circuit 150 can detect that the data voltage Vdata of the data unit 110 is smaller than the reference voltage Vref, so that the data bit stored in the data unit 110 is judged to be "0".
If the resistance of the data unit 110 is in the high-resistance state RH, the data voltage Vdata connected to the access point of the comparison circuit 150 and the load circuit 140 is increased due to the high-resistance state RH, and the data voltage Vdata is increased and tends to increase compared to the state without data reading, and the comparison circuit 150 can detect that the data voltage Vdata of the data unit 110 is greater than the reference voltage Vref of the reference unit 120, so as to determine that the data bit stored in the data unit 110 is "1", or vice versa.
In this embodiment, the load circuit 140 is a current mirror. The current mirror is used to mirror a read current generated at the reference cell 120 into the data cell 110 and convert the read current of the data cell 110 into a data voltage Vdata.
In this embodiment, the reference cells 120 include the same number of antiparallel state reference cells 120H and parallel state reference cells 120L, and the number of antiparallel state reference cells 120H and parallel state reference cells 120L is y; wherein y is a positive integer.
In a read operation, the bit line voltage applied to the data cell 110 by the driving signal module 180 is a data bit line voltage Vread (BL), and the bit line voltage applied to the reference cell 120 by the driving signal module 180 is a reference bit line voltage Vread (REF _ BL); the mirror ratio taken from the reference cell 120 to the data cell 110 is 2 y: x; where x is the ratio of the data bit line voltage Vread (BL) to the reference bit line voltage Vread (REF _ BL). By setting the mirror ratio described above, it is ensured that the read current of the data cell 110 is compared to the read current of the reference cell 120 generated at the same bit line voltage.
In this embodiment, the data bit line voltage Vread (BL) and the reference bit line voltage Vread (REF _ BL) are the same, so that the mirror scale compensation factor x is 1, the mirror scale compensation factor x is an integer, which is beneficial to reducing the complexity of the circuit design, and the driving signal module 180 includes a clamp circuit 160 coupled to the load circuit 140, where the clamp circuit 160 is configured to clamp the bit line voltages of the data unit 110 and the reference unit 120, and by making the data bit line voltage Vread (BL) and the reference bit line voltage Vread (REF _ BL) the same, the data unit 110 and the reference unit 120 can use the same clamp voltage module 160, which is also beneficial to reducing the complexity of the design of the clamp circuit 160.
As an example, a current mirror includes: the first PMOS pipe group P _ Cell and the second PMOS pipe group P _ REF comprise a PMOS pipe or a plurality of PMOS pipes which are connected in parallel;
in the first PMOS transistor group P _ Cell, a source of the PMOS transistor is coupled to a power VDD, a drain of the PMOS transistor is coupled to a gate of the PMOS transistor, and a drain of the PMOS transistor is coupled to the data unit 110, the first PMOS transistor group P _ Cell is adapted to convert a read current passing through the first PMOS transistor group P _ Cell into a data voltage Vdata;
in the second PMOS transistor group P _ REF, the source of the PMOS transistor is coupled to the power VDD, the drain of the PMOS transistor is coupled to the gate, the drain of the PMOS transistor is coupled to the reference output 120A, and the second PMOS transistor group P _ REF is adapted to convert the read current passing through the second PMOS transistor group into the reference voltage Vref.
Correspondingly, the drain of the PMOS transistor of the first PMOS transistor group is the first output terminal of the load circuit 140, and the drain of the PMOS transistor of the second PMOS transistor group P _ REF is the second output terminal of the load circuit 140.
In this embodiment, the data bit line voltage Vread (BL) and the reference bit line voltage Vread (REF _ BL) are the same, so that the mirror scale compensation factor x is 1, and the first PMOS transistor group P _ Cell is a PMOS transistor.
In this embodiment, the number of the antiparallel state reference units 120H and the number of the parallel state reference units 120L are the same, and the number of the antiparallel state reference units 120H and the number of the parallel state reference units 120L are both y; and y is a positive integer, so that the second PMOS tube group comprises 2y parallel PMOS tubes.
As an example, the number of the anti-parallel state reference units 120H and the parallel state reference units 120L is one, and thus, the second PMOS tube group P _ REF includes 2 PMOS tubes connected in parallel.
The comparison circuit 150 is used for reading the information of the data unit 110 according to the relative sizes of the data voltage Vdata and the reference voltage Vref. In this embodiment, the comparing circuit 150 includes a first input 1501, a second input 1502 and an output 1503, the first input 1501 is coupled to the data unit 110, the second input 1502 is coupled to the reference output 120A, the comparing circuit 150 is configured to read information of the data unit 110 according to relative magnitudes of the data voltage Vdata and the reference voltage Vref, and the output 1503 outputs a comparison result signal.
In this embodiment, the comparison circuit 150 is a Sense Amplifier (SA). As an example, a non-inverting input of a sense amplifier is coupled to data cell 110 and an inverting input of the sense amplifier is coupled to reference cell 120.
In a specific implementation, if the data voltage Vdata is less than the reference voltage Vref, it may be determined that the data stored in the data unit 110 is "0", and the magnetic tunnel junction 100 of the data unit 110 is in a low resistance state (i.e., a parallel state); if the data voltage Vdata is greater than the reference voltage Vref, it can be determined that the data stored in the data unit 110 is "1", and the magnetic tunnel junction 100 of the data unit 110 is in a high resistance state (i.e., an antiparallel state); or vice versa.
FIG. 5 is a diagram of another embodiment of a MRAM in accordance with the present invention. The same parts of the embodiments of the present invention as those of the previous embodiments are not described herein again, but the differences are: the magnetic tunnel junction 300 is Top-Pinned magnetic (Top-Pinned), and the magnetic tunnel junction 300 includes a magnetic free layer 3002 and a magnetic Pinned layer 3001 on the magnetic free layer 3002.
In this embodiment, the magnetic pinned layer 3001 of the data cell 310 is coupled to the load circuit 340.
In this embodiment, the memory cell further includes a select transistor N0 coupled to the magnetic tunnel junction 300, the gate of the select transistor N0 being coupled to the word line WL.
Accordingly, in the data cell 310 of the present embodiment, the drain of the select transistor N0 is coupled to the magnetic free layer 3002 of the magnetic tunnel junction 300, and the source of the select transistor N0 is grounded.
In this embodiment, in the parallel state reference cell 320L, the drain of the select transistor N0 is coupled to the magnetic free layer 3002 of the magnetic tunnel junction 300, the source of the select transistor N0 is used to form the reference output 320A, and the magnetic pinned layer 3001 of the magnetic tunnel junction 300 is coupled to the ground VSS.
In this embodiment, in the anti-parallel reference cell 320H, the magnetic pinned layer 3001 of the magnetic tunnel junction 300 is used to form the reference output terminal 320A, the drain of the select transistor N0 is coupled to the magnetic free layer 3002 of the magnetic tunnel junction 300, and the source of the select transistor N0 is coupled to the ground VSS.
In the MRAM, a writing current (writing "0") direction for writing the magnetic tunnel junction 300 from a high resistance state (i.e., an antiparallel state) to a low resistance state (i.e., a parallel state) coincides with a direction in which the magnetic free layer 3002 points to the magnetic pinned layer 3001, and a writing current (writing "1") direction for writing the magnetic tunnel junction 300 from a low resistance state to a high resistance state coincides with a direction in which the magnetic pinned layer 3001 points to the magnetic free layer 3002.
In the present embodiment, during the read operation, the direction of the read current is along the reference output terminal 320A toward the ground terminal VSS. Specifically, in the present embodiment, in the parallel-state reference cell 320L, the direction of the read current passing through the magnetic tunnel junction 300 is the same as the direction of the magnetic free layer 3002 pointing to the magnetic pinned layer 3001, that is, the same as the direction of the current writing the magnetic tunnel junction 300 to the low resistance state (i.e., the parallel state), and the magnetic tunnel junction 300 in the parallel-state reference cell 320L has already been in the low resistance state, so that the resistance state of the parallel-state reference cell 320L can be prevented from being inverted;
in the antiparallel-state reference cell 320H, the direction of the read current through the magnetic tunnel junction 300 coincides with the direction of the magnetic pinned layer 3001 pointing to the magnetic free layer 3002, that is, the same direction as the current for writing the magnetic tunnel junction 300 in the high-resistance state, and the magnetic tunnel junction 300 in the antiparallel-state reference cell 320H is already in the high-resistance state, so that the resistance state of the antiparallel-state reference cell 320H can be prevented from being inverted.
For a detailed description of the magnetic random access memory of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and the description of this embodiment is not repeated herein.
Correspondingly, the embodiment of the invention also provides a storage array. FIG. 4 is a schematic structural diagram of a memory array according to an embodiment of the present invention.
In this embodiment, the memory array 400 is applied to a magnetic random access memory, which includes: a drive signal module for providing a read signal to the memory array; and a comparison circuit for reading data of the memory array according to the relative magnitude of the data voltage and the reference voltage outputted by the memory array 400.
Referring to fig. 4 in combination, in this embodiment, the memory array 400 includes: the memory cell comprises a plurality of memory cells arranged in an array, wherein each memory cell comprises a magnetic tunnel junction 100, each magnetic tunnel junction 100 comprises a magnetic fixed layer 1001 and a magnetic free layer 1002 which are arranged oppositely, the memory cell of data to be read is defined as a data cell 110, and the data cell 110 is used for loading a read signal and outputting a data voltage Vdata; the memory cell used as a reference for data reading is defined as a reference cell 120, the reference cell 120 includes an antiparallel state (AP-state) reference cell 120H and a parallel state (P-state) reference cell 120L, a magnetic free layer 1002 of the parallel state reference cell 120L is coupled to a magnetic pinned layer 1001 of the antiparallel state reference cell 120H to form a reference output 120A, and the reference cell 120 is used for loading a read signal and outputting a reference voltage Vref through the reference output 120A.
In this embodiment, the magnetic free layer 1002 of the parallel reference cell 120L is coupled to the magnetic pinned layer 1001 of the anti-parallel reference cell 120H to form a reference output 120A, and the reference cell 120 is configured to load a read signal and output a reference voltage Vref through the reference output 120A; therefore, during a read operation, the direction of the read current passing through the anti-parallel state reference cell 120H is consistent with the direction of the magnetic pinned layer 1001 pointing to the magnetic free layer 1002, the direction of the read current passing through the parallel state reference cell 120L is consistent with the direction of the magnetic free layer 1002 pointing to the magnetic pinned layer 1001, that is, the direction of the read current passing through the anti-parallel state reference cell 120H is consistent with the direction of the current for writing 1, and the direction of the read current passing through the parallel state reference cell 120L is consistent with the direction of the current for writing 0, so as to ensure that after a long-time read operation, the resistance states of the anti-parallel state reference cell 120H and the parallel state reference cell 120L are not easily flipped, reduce the possibility of flipping of the resistance state of the reference cell 120 during the read operation, correspondingly provide a more reliable reference resistance for data read of the data cell, ensure the reliability of the reference cell, and further improve the data read accuracy of the MRAM, the reliability of the MRAM is accordingly improved.
The storage unit is used for storing data. The plurality of memory cells are repeating cells, i.e., the plurality of memory cells have the same structure. Therefore, the anti-parallel reference cell 120H or the parallel reference cell 120L has the same structure as the data cell 110, which is beneficial to improving the accuracy of the reference cell 120 as a reference for reading data.
In a specific implementation, the magnetic tunnel junction 100 in the memory cell is used to store data. Specifically, when the magnetic directions of the magnetic pinned layer 1001 and the magnetic free layer 1002 are parallel, the memory cell is in a parallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a maximum value, and the magnetic tunnel junction 100 is in a low resistance state (RL); when the magnetic directions of the magnetic pinned layer 1001 and the magnetic free layer 1002 are antiparallel, the memory cell is in an antiparallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a minimum value, and the magnetic tunnel junction 100 is in a high resistance state (RH).
The magnetization direction of the magnetic pinned layer 1001 is fixed for use as a magnetization direction reference layer for the magnetic free layer 1002. The magnetization direction of the magnetic free layer 1002 has two stable orientations, parallel or opposite to the magnetization direction of the magnetic pinned layer 1001, respectively, thereby enabling the magnetic tunnel junction 100 to be in a low resistance state (i.e., parallel state) or a high resistance state (anti-parallel state). The materials of the magnetic free layer 1002 and the magnetic pinned layer 1001 are ferromagnetic metal materials.
In this embodiment, the magnetic tunnel junction 100 further includes: a tunneling barrier layer 1003 between the magnetic fixed layer 1001 and the magnetic free layer 1002. The tunneling barrier layer 1003 is used to achieve electrical isolation between the magnetic fixed layer 1001 and the magnetic free layer 1002. The material of the tunnel barrier layer 1003 is an insulating material.
As an example, the magnetic tunnel junction 100 is Bottom-Pinned (Bottom-Pinned), and the magnetic tunnel junction 100 includes a magnetically Pinned layer 1001 and a magnetically free layer 1002 on the magnetically Pinned layer 1001.
The memory cell also includes a select transistor N0 coupled to the magnetic tunnel junction 100, the gate of the select transistor N0 being coupled to the word line WL (word line). The select transistor N0 is adapted to be turned on or off under the control of a signal to turn on the word line WL to read the data stored in the magnetic tunnel junction 100. In this embodiment, the selection transistor N0 is an NMOS transistor.
In this embodiment, the magnetic tunnel junction 100 is bottom pinned, the magnetic tunnel junction 100 includes a pinned layer 1001 and a free layer 1002 on the pinned layer 1001, and accordingly, in the data cell 110, the drain of the select transistor N0 is coupled to the pinned layer 1002 of the magnetic tunnel junction 100, and the source of the select transistor N0 is coupled to the ground VSS.
In a specific implementation, the magnetic random access memory 200 uses the magnetic tunnel junction 100 in at least one anti-parallel reference cell 120H and at least one parallel reference cell 120L to form a standard resistance, and compares the data cell 110 with the standard resistance to determine whether the data cell 110 is in a high resistance state or a low resistance state, thereby implementing data reading of the data cell 110.
The data cell 110 is data to be read, and the resistance state of the magnetic tunnel junction 100 in the data cell 110 is to be confirmed. The reference unit 120 is adapted to store and output reference data for reference to read the data of the data unit 110.
The reference output terminal 120A is used for outputting a reference signal for data reading of the data unit 110. Specifically, in a read operation, the reference unit 120 outputs a reference signal through the reference output terminal 120A based on the read signal provided by the driving signal module 180.
Specifically, the reference unit 120 includes at least one antiparallel (i.e., high Resistance (RH)) reference unit 120H and at least one parallel (i.e., low Resistance (RL)) reference unit 120L, where the magnetic tunnel junction 100 in the at least one antiparallel reference unit 120H and the at least one parallel reference unit 120L form a standard resistance, and the data unit 110 is compared with the standard resistance to determine whether the data unit 110 is in the high resistance state or the low resistance state, thereby reading data of the data unit 110.
In this embodiment, the antiparallel state reference unit 120H means that the magnetic tunnel junction 100 in the antiparallel state reference unit 120H is in an Antiparallel (AP) state, and the magnetic direction of the magnetic free layer 1002 is antiparallel to the magnetic direction of the magnetic pinned layer 1001; the parallel state reference cell 120L means that the magnetic tunnel junction 100 in the parallel state reference cell 120L is in a parallel (P) state, and the magnetic direction of the magnetic free layer 1002 is parallel to the magnetic direction of the magnetic pinned layer 1001.
As an example, in the reference cells 120, the number of the antiparallel state reference cells 120H and the number of the parallel state reference cells 120L are the same, and the number of the antiparallel state reference cells 120H and the number of the parallel state reference cells 120L are both y; wherein y is a positive integer. By making the number of the anti-parallel state reference cells 120H and the parallel state reference cells 120L the same, it is advantageous to reduce the complexity of circuit design.
In the present embodiment, for convenience of illustration and explanation, the reference cell 120 includes an antiparallel-state reference cell 120H and a parallel-state reference cell 120L as an example. However, the reference cells 120 include the antiparallel state reference cells 120H and the parallel state reference cells 120L in a number not limited thereto. In other embodiments, the reference cells may include a plurality of antiparallel state reference cells and a plurality of parallel state reference cells, and the number of antiparallel state reference cells and the number of parallel state reference cells may be different.
As an example, the magnetic tunnel junction 100 is bottom pinned magnetically, and the magnetic tunnel junction 100 includes a magnetically pinned layer 1001 and a magnetically free layer 1002 on the magnetically pinned layer 1001. Specifically, the drain of select transistor N0 in data cell 110 is coupled to the magnetically pinned layer 1001 of the magnetic tunnel junction 100, and the source of select transistor N0 in data cell 110 is coupled to ground VSS.
Accordingly, in the parallel state reference cell 120L of the present embodiment, the drain of the selection transistor N0 is coupled to the magnetic pinned layer 1001 of the magnetic tunnel junction 100, the source of the selection transistor N0 is coupled to the ground VSS, and the magnetic free layer 1002 of the magnetic tunnel junction 100 is used to form the reference output terminal 120A.
In this embodiment, in the anti-parallel reference cell 120H, the drain of the select transistor N0 is coupled to the magnetic pinned layer 1001 of the magnetic tunnel junction 100, the source of the select transistor N0 is used to form the reference output 120A, and the magnetic free layer 1002 of the magnetic tunnel junction 100 is coupled to the ground VSS.
In the present embodiment, during the read operation, the direction of the read current is along the direction from the reference output terminal 120A to the ground terminal VSS.
Specifically, in the parallel-state reference cell 120L, the direction of the read current passing through the magnetic tunnel junction 100 is the same as the direction of the magnetic free layer 1002 pointing to the magnetic pinned layer 1001, that is, the same as the direction of the current writing the magnetic tunnel junction 100 to the low resistance state or the parallel state, and the magnetic tunnel junction 100 in the parallel-state reference cell 120L is already in the low resistance state, so that the resistance state of the parallel-state reference cell 120L can be prevented from being inverted;
in the antiparallel-state reference cell 120H, the direction of the read current passing through the magnetic tunnel junction 100 coincides with the direction in which the magnetic pinned layer 1001 points to the magnetic free layer 1002, that is, the same direction as the current for writing the magnetic tunnel junction 100 in the high-resistance state or antiparallel state, and the magnetic tunnel junction 100 in the antiparallel-state reference cell 120H is already in the high-resistance state, so that the resistance state of the antiparallel-state reference cell 120H can be prevented from being inverted.
Correspondingly, the invention also provides a storage array of another embodiment. The same points of the embodiments of the present invention as those of the previous embodiments are not described herein again, and the embodiments of the present invention are different from the previous embodiments in that: the magnetic tunnel junction is Top-Pinned magnetic (Top-Pinned), and the magnetic tunnel junction includes a magnetic free layer and a magnetic Pinned layer on the magnetic free layer.
In this embodiment, the memory cell further includes a select transistor coupled to the magnetic tunnel junction, the gate of the select transistor being coupled to the word line. Accordingly, in this embodiment, in the data cell, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.
In this embodiment, in the parallel reference cell, a drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, a source of the selection transistor is used to form a reference output terminal, and the magnetic pinned layer of the magnetic tunnel junction is grounded.
In this embodiment, in the antiparallel state reference unit, the magnetic pinned layer of the magnetic tunnel junction is used to form a reference output terminal, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.
In the MRAM, a writing current (writing "0") direction for writing the magnetic tunnel junction from a high resistance state (i.e., an antiparallel state) to a low resistance state (i.e., a parallel state) coincides with a direction in which the magnetic free layer points to the magnetic pinned layer, and a writing current (writing "1") direction for writing the magnetic tunnel junction from a low resistance state to a high resistance state coincides with a direction in which the magnetic pinned layer points to the magnetic free layer.
In this embodiment, during a read operation, the direction of the read current is along the direction from the reference output terminal to the ground terminal. Specifically, in the embodiment, in the parallel-state reference unit, the direction of the read current passing through the magnetic tunnel junction is the same as the direction of the magnetic free layer pointing to the magnetic fixed layer, that is, the same as the current direction for writing the magnetic tunnel junction into the low resistance state (i.e., the parallel state), and the magnetic tunnel junction in the parallel-state reference unit is already in the low resistance state, so that the resistance state of the parallel-state reference unit can be prevented from being turned over;
in the anti-parallel state reference unit, the direction of a reading current passing through the magnetic tunnel junction is consistent with the direction of the magnetic fixed layer pointing to the magnetic free layer, namely the direction of the current for writing the magnetic tunnel junction into a high resistance state, and the magnetic tunnel junction in the anti-parallel state reference unit is already in the high resistance state, so that the resistance state of the anti-parallel state reference unit can be prevented from being turned over.
For a specific description of the memory array in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Correspondingly, the embodiment of the invention also provides the electronic equipment. The electronic device includes: the embodiment of the invention provides a magnetic random access memory.
As can be seen from the foregoing description, in the magnetic random access memory provided in the embodiments of the present invention, the resistance state of the reference cell is low in possibility of being flipped during a read operation, and accordingly, a more reliable reference resistance is provided for data reading of the data cell, and reliability of the reference cell is ensured, so that data reading accuracy of the MRAM is improved, and accordingly, reliability of the MRAM is improved, and accordingly, performance of the electronic device provided in the embodiments of the present invention is also improved, for example: the data reading accuracy is improved, and the user experience and the sensitivity are optimized.
In this embodiment, the electronic device may be an electronic device capable of storing and reading data, for example: chip, cell-phone, computer, equipment such as on-vehicle electronic product.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A magnetic random access memory, comprising:
the driving signal module is used for providing a reading signal;
the storage array comprises a plurality of storage units which are arranged in an array, wherein each storage unit comprises a magnetic tunnel junction, and each magnetic tunnel junction comprises a magnetic fixed layer and a magnetic free layer which are oppositely arranged;
defining a storage unit of data to be read as a data unit, wherein the data unit is used for loading the read signal and outputting a data voltage;
defining a memory cell used as a data reading reference as a reference cell, wherein the reference cell comprises a parallel state reference cell and an anti-parallel state reference cell; the magnetic free layer of the parallel state reference unit is coupled with the magnetic fixed layer of the anti-parallel state reference unit to form a reference output end, and the reference unit is used for loading the read signal and outputting a reference voltage through the reference output end;
and the comparison circuit is used for reading the data of the data unit according to the relative size of the data voltage and the reference voltage.
2. The magnetic random access memory of claim 1 wherein the magnetic tunnel junction comprises a magnetically fixed layer and a magnetically free layer on the magnetically fixed layer;
alternatively, the magnetic tunnel junction includes a magnetic free layer and a magnetic pinned layer on the magnetic free layer.
3. The magnetic random access memory of claim 2 wherein the magnetic tunnel junction comprises a magnetically fixed layer and a magnetically free layer on the magnetically fixed layer; the memory cell further comprises a select transistor connected to the magnetic tunnel junction, a gate of the select transistor being coupled to a word line;
in the data unit, the drain electrode of the selection transistor is coupled with the magnetic fixed layer of the magnetic tunnel junction, and the source electrode of the selection transistor is grounded;
in the parallel state reference unit, the drain electrode of the selection transistor is coupled with the magnetic fixed layer of the magnetic tunnel junction, and the source electrode of the selection transistor is grounded;
in the antiparallel reference unit, the drain of the selection transistor is coupled to the magnetic fixed layer of the magnetic tunnel junction, the source of the selection transistor is used for forming the reference output end, and the magnetic free layer of the magnetic tunnel junction is grounded.
4. The magnetic random access memory of claim 2 wherein the magnetic tunnel junction comprises a magnetic free layer and a magnetic pinned layer on the magnetic free layer; the memory cell further comprises a select transistor connected to the magnetic tunnel junction, a gate of the select transistor being coupled to a word line;
in the data unit, the drain electrode of the selection transistor is coupled with the magnetic free layer of the magnetic tunnel junction, and the source electrode of the selection transistor is grounded;
in the parallel state reference unit, the drain of the selection transistor is coupled with the magnetic free layer of the magnetic tunnel junction, the source of the selection transistor is used for forming the reference output end, and the magnetic fixed layer of the magnetic tunnel junction is grounded;
in the antiparallel-state reference unit, the magnetic fixed layer of the magnetic tunnel junction is used for forming the reference output end, the drain of the selection transistor is coupled with the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.
5. The magnetic random access memory of claim 1 wherein the driving signal module is configured to provide a bit line voltage, the reference cell is configured to load the bit line voltage and output a reference current through the reference output, and the data cell is configured to load the bit line voltage and output a data current;
the magnetic random access memory further comprises: a load circuit coupled to the data cell and to the reference output; the load circuit is used for converting the data current of the data unit into a data voltage and converting the reference current of the reference unit into a reference voltage.
6. The magnetic random access memory of claim 5, wherein the drive signal module comprises:
a clamp circuit coupled to the load circuit, the clamp circuit to provide a bit line voltage to the data cell and a reference cell and to clamp the bit line voltage of the data cell and the reference cell;
and one end of the bit line selection circuit is coupled with the clamping circuit, the other end of the bit line selection circuit is correspondingly coupled with the data unit and the reference output end respectively, and the bit line selection circuit is suitable for selecting the data unit to be read and the reference unit.
7. The MRAM of claim 6, wherein the clamp circuit comprises an NMOS transistor having a drain coupled to the load circuit, a source coupled to the bit line select circuit, and a gate for loading a clamp control signal;
in the read operation, the voltage applied to the gate of the NMOS transistor is: and the sum of the threshold voltage of the NMOS tube and the bit line voltage.
8. The magnetic random access memory of claim 5 wherein the load circuit is a current mirror.
9. The magnetic random access memory of claim 8 wherein the number of the anti-parallel state reference cells and the number of the parallel state reference cells are the same, both the number of the anti-parallel state reference cells and the number of the parallel state reference cells are y; wherein y is a positive integer;
during a read operation, the bit line voltage loaded to the data unit by the driving signal module is a data bit line voltage, and the bit line voltage loaded to the reference unit by the driving signal module is a reference bit line voltage;
the mirror ratio taken from reference cell to data cell is 2 y: x; wherein x is a ratio of the data bit line voltage to the reference bit line voltage.
10. The magnetic random access memory of claim 9 wherein the data bit line voltage and the reference bit line voltage are the same.
11. The magnetic random access memory of claim 8, wherein the current mirror comprises: the first PMOS pipe group and the second PMOS pipe group respectively comprise a PMOS pipe or a plurality of PMOS pipes which are connected in parallel;
in the first PMOS tube group, a source electrode of a PMOS tube is coupled to a power supply, a drain electrode of the PMOS tube is coupled to a grid electrode of the PMOS tube, a drain electrode of the PMOS tube is coupled to the data unit, and the first PMOS tube group is suitable for converting reading current passing through the first PMOS tube group into data voltage;
in the second PMOS tube group, a source of the PMOS tube is coupled to a power supply, a drain of the PMOS tube is coupled to a gate, and a drain of the PMOS tube is coupled to the reference output terminal, and the second PMOS tube group is adapted to convert a read current passing through the second PMOS tube group into a reference voltage.
12. The magnetic random access memory of claim 1 wherein the compare circuit includes a first input coupled to the data cell, a second input coupled to the reference output, and an output for outputting a compare result signal.
13. The magnetic random access memory of claim 1 wherein the comparison circuit is a sense amplifier.
14. A memory array for a magnetic random access memory, the magnetic random access memory comprising: a drive signal module for providing a read signal to the memory array; the comparison circuit is used for reading the data of the storage array according to the relative size of the data voltage and the reference voltage output by the storage array;
the memory array, comprising:
the storage unit comprises a plurality of storage units which are arranged in an array, wherein each storage unit comprises a magnetic tunnel junction, and each magnetic tunnel junction comprises a magnetic fixed layer and a magnetic free layer which are oppositely arranged;
defining a storage unit of data to be read as a data unit, wherein the data unit is used for loading the read signal and outputting the data voltage;
defining a memory cell used as a data reading reference as a reference cell, wherein the reference cell comprises a parallel state reference cell and an anti-parallel state reference cell; and the magnetic free layer of the parallel state reference unit is coupled with the magnetic fixed layer of the anti-parallel state reference unit to form a reference output end, and the reference unit is used for loading the read signal and outputting the reference voltage through the reference output end.
15. The memory array of claim 14, wherein the magnetic tunnel junction comprises a magnetically pinned layer and a magnetically free layer on the magnetically pinned layer;
alternatively, the magnetic tunnel junction includes a magnetic free layer and a magnetic pinned layer on the magnetic free layer.
16. The memory array of claim 15, wherein the magnetic tunnel junction comprises a magnetically pinned layer and a magnetically free layer on the magnetically pinned layer; the memory cell further comprises a select transistor connected to the magnetic tunnel junction, a gate of the select transistor being coupled to a word line;
in the data unit, the drain electrode of the selection transistor is coupled with the magnetic fixed layer of the magnetic tunnel junction, and the source electrode of the selection transistor is grounded;
in the parallel state reference unit, the drain electrode of the selection transistor is coupled with the magnetic fixed layer of the magnetic tunnel junction, and the source electrode of the selection transistor is grounded;
in the antiparallel reference unit, the drain of the selection transistor is coupled to the magnetic fixed layer of the magnetic tunnel junction, the source of the selection transistor is used for forming the reference output end, and the magnetic free layer of the magnetic tunnel junction is grounded.
17. The memory array of claim 15, wherein the magnetic tunnel junction comprises a magnetic free layer and a magnetic pinned layer on the magnetic free layer; the memory cell further comprises a select transistor connected to the magnetic tunnel junction, a gate of the select transistor being coupled to a word line;
in the data unit, the drain electrode of the selection transistor is coupled with the magnetic free layer of the magnetic tunnel junction, and the source electrode of the selection transistor is grounded;
in the parallel state reference unit, the drain electrode of the selection transistor is coupled with the magnetic free layer of the magnetic tunnel junction, the source electrode of the selection transistor is used for forming the reference output end, and the magnetic fixed layer of the magnetic tunnel junction is grounded;
in the antiparallel-state reference unit, the magnetic fixed layer of the magnetic tunnel junction is used for forming the reference output end, the drain of the selection transistor is coupled with the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.
18. An electronic device comprising the magnetic random access memory according to any one of claims 1 to 13.
CN202011541239.1A 2020-12-23 2020-12-23 Magnetic random access memory, memory array and electronic equipment Pending CN114664344A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118690420A (en) * 2024-08-26 2024-09-24 中科芯磁科技(珠海)有限责任公司 Method and circuit for clearing content of configuration memory of MRAM type FPGA

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118690420A (en) * 2024-08-26 2024-09-24 中科芯磁科技(珠海)有限责任公司 Method and circuit for clearing content of configuration memory of MRAM type FPGA
CN118690420B (en) * 2024-08-26 2024-10-29 中科芯磁科技(珠海)有限责任公司 Method and circuit for clearing configuration memory content of MRAM type FPGA

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