CN108182956B

CN108182956B - High-speed MRAM readout circuit

Info

Publication number: CN108182956B
Application number: CN201810053718.5A
Authority: CN
Inventors: 戴瑾
Original assignee: Shanghai Information Technologies Co ltd
Current assignee: Shanghai Information Technologies Co ltd
Priority date: 2018-01-19
Filing date: 2018-01-19
Publication date: 2023-07-21
Anticipated expiration: 2038-01-19
Also published as: CN108182956A

Abstract

The invention discloses a high-speed MRAM (magnetic random Access memory) readout circuit, which comprises a row of a plurality of equivalent MOS (metal oxide semiconductor) tubes, a reference unit combination, a comparator and two operational amplifiers OP Amp; each storage unit is connected with one MOS tube Pa in a plurality of equivalent MOS tubes in series; the reference unit combination is formed by connecting N reference units in parallel; each of the N reference units is connected with one of N equivalent MOS tubes in series; one input of the two operational amplifiers OP Amp is respectively connected with the MOS tube Pa and the N MOS tubes Pbi, and the other input is a read voltage V_read; the comparator outputs the result by comparing the gate voltages output from the two operational amplifiers OP Amp. The power consumption reading circuit of the reading circuit disclosed by the invention is high in speed, and the risk of unstable reading can be eliminated.

Description

High-speed MRAM readout circuit

Technical Field

The invention belongs to the field of semiconductor chip memories, and particularly relates to a high-speed MRAM (magnetic random Access memory) readout circuit.

Background

Magnetic Random Access Memory (MRAM) is an emerging non-volatile memory technology. It has high read-write speed and high integration, and can be written repeatedly infinitely many times. MRAM can be read and written as fast as SRAM/DRAM, and also can permanently retain data after power down as Flash.

MRAM has good economy and performance, and its unit capacity occupies a larger silicon area than SRAM, and also has an advantage over NOR Flash, which is often used in such chips, that is greater than embedded NOR Flash. MRAM has close read-write delay to the best SRAM, and power consumption is best in various memories and storage technologies; moreover, the MRAM is compatible with the standard CMOS semiconductor process, and the DRAM and the Flash are not compatible with the standard CMOS semiconductor process; MRAM may also be integrated with logic circuitry into one chip.

MRAM is based on MTJ (magnetic tunnel junction) structures. Composed of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1: the lower ferromagnetic material is a reference layer with a fixed magnetization direction and the upper ferromagnetic material is a memory layer with a variable magnetization direction, the magnetization direction of which may be parallel or antiparallel to the fixed magnetization layer. Due to quantum-physical effects, current can pass through the intermediate tunnel barrier layer, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The former case has low resistance and the latter case has high resistance.

The process of reading MRAM is to measure the resistance of the MTJ. Writing MRAM uses newer STT-MRAM techniques for writing operations using stronger currents through the MTJ than reading. A bottom-up current places the variable magnetization layer in a parallel orientation with respect to the fixed layer and a top-down circuit places it in an anti-parallel orientation.

As shown in FIG. 2, each MRAM memory cell is comprised of an MTJ and an NMOS tube. The gate electrode (gate) of the NMOS tube is connected to the Word Line of the chip to switch on or off the unit, and the MTJ and the MOS tube are connected in series on the Bit Line of the chip. The read-write operation is performed on the Bit Line.

As shown in fig. 3, an MRAM chip is composed of one or more MRAM memory cell arrays, each array having several external circuits, such as:

● Row address decoder: selection of a received address to become Word Line

● Column address decoder: selection of a received address to be a Bit Line

● And a read-write controller: controlling read (measurement) write (current) operations on Bit Line

● Input and output control: and externally exchange data

The read-out circuitry of MRAM is required to detect the resistance of the MRAM memory cells. Since the resistance of an MTJ shifts with temperature, etc., it is a common approach to use some memory cells on a chip that have been written to a high resistance state or a low resistance state as reference cells. A Sense Amplifier (Sense Amplifier) is then used to compare the resistances of the memory cell and the reference cell.

The read-out process of MRAM is the detection and comparison of the resistance of the memory cell. The reference cells are typically combined into a standard resistor to be compared with the memory cells to determine whether the memory cells are in a high resistance state or a low resistance state.

FIG. 4 is a schematic diagram of a prior art MRAM sense circuit, where P1, P2, and P3 shown in FIG. 4 are identical PMOS transistors forming a current mirror, and the current in each of the above paths is equal (I_read). The difference in resistance causes a difference in v_out and v_out_n, which is input to the comparator of the next stage to generate an output. The example in fig. 4 is a one-way memory cell, as opposed to a one-way P-state reference cell and an one-way AP-state reference cell. In actual use, the multi-path storage unit can be used for comparing m paths of AP and n paths of P reference units.

The use of reference cells can counteract the floating of the resistance of the memory cells caused by the non-uniformity of the processing technology, columns are generally added in an array to serve as the reference cells, and when the memory cells in the same row are compared with the reference cells in the read operation, the total resistance change of different rows caused by the different bit line lengths can be counteracted, but a part of the chip area is sacrificed to be specially used for reference.

One problem with the prior art MRAM read-out circuit shown in fig. 4 is that the speed is limited. The connection between the memory cell and the reference cell requires a long bit line and source line, both of which have large load capacitance, which is a major factor in limiting the speed of the circuit. When the read operation is powered up, these capacitors must be charged up quickly to reach circuit balance for resistance comparison. This requires the circuit to provide a very large instantaneous current, whereas the current mirror is closer to a constant current source, providing a relatively constant current, which is suitable for measuring resistance, but unsuitable when the speed requirement is high.

Another problem is read stability. The current on each cell in the circuit shown in fig. 4 is nearly equal, so the voltage on the high-resistance cell increases proportionally, if 200mV is applied to the reference cell group in order to ensure signal strength, some cells may reach 500mV due to non-uniformity of the fabrication process, smaller radius, and larger resistance, and such voltages may cause unstable state changes at the time of reading.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a high-speed MRAM readout circuit, which uses an operational amplifier Op Amp to control and adjust a MOS transistor, so as to rapidly and isobarically read out the content of a memory cell.

In order to achieve the above object, the present invention provides a high-speed MRAM readout circuit, which includes a row of a plurality of equivalent MOS transistors, a reference cell combination, a comparator, and two operational amplifiers OP Amp.

Each storage unit is connected with one MOS tube Pa in the plurality of equivalent MOS tubes in series; the series connection point is connected to one input of one operational amplifier OP Amp, the other input of the operational amplifier OP Amp is a read voltage V_read, the output of the operational amplifier OP Amp is connected with the grid electrode of the MOS tube Pa, and the grid electrode voltage of the MOS tube Pa is adjusted through a feedback effect.

The reference unit combination is formed by connecting N reference units in parallel; n equivalent Pbi (i=1, 2, …, N) in the row of the plurality of equivalent MOS transistors are connected in parallel; the N reference unit combinations are correspondingly connected in series with the N equivalent MOS unit combinations; the series connection point is connected to one input of another operational amplifier OP Amp, the other input of the operational amplifier OP Amp is a read voltage v_read, the output of the operational amplifier OP Amp is connected to the gates of the N MOS transistors Pbi (i=1, 2, …, N), and the gate voltages of the MOS transistors Pbi (i=1, 2, …, N) are adjusted by a feedback effect.

The voltage difference between the multiple equivalent MOS tubes and the two ends of the reference unit is V_read_supply.

The comparator outputs a result by comparing gate voltages output from the two operational amplifiers OP Amp.

Further, the equivalent MOS transistors are in a disconnected state during initialization, and are controlled to be opened through the operational amplifier OP Amp.

Further, the combination tube which is connected with the reference unit in series is a MOS tube with N times of the same MOS tube used for the storage unit, and the operational amplifier OP Amp is connected with the combination tube.

The readout circuit disclosed by the invention has the advantages that the speed is high, the OP Amp reaction is fast, the MOS tube can be completely opened in the initial stage, and a large current is provided, so that the parasitic capacitance C_BL is rapidly filled. The conventional sense amplifier requires a duty cycle of 5ns and can perform its task at 1-2 ns. In addition, the voltage on all the memory cells of the read-out circuit disclosed by the invention is controlled to be about V_read, so that the read-out circuit is very safe, and the risk of unstable read-out is eliminated.

Drawings

FIG. 1 is a schematic diagram of a prior art MTJ.

FIG. 2 is a schematic diagram of a prior art MRAM memory cell architecture.

FIG. 3 is a prior art MRAM chip architecture diagram.

Fig. 4 is a schematic diagram of an MRAM sensing circuit in accordance with the prior art.

FIG. 5 is a schematic diagram of an MRAM sensing circuit employing a reference voltage according to a preferred embodiment of the invention.

Detailed Description

The following detailed description of the preferred embodiments of the invention is provided to enable those skilled in the art to more readily understand the advantages and features of the invention and to make a clear and concise definition of the scope of the invention.

Fig. 5 shows a high-speed MRAM read-out circuit comprising a row of a plurality of identical MOS transistors, a reference cell combination, a comparator and two operational amplifiers OP Amp.

Each memory cell is connected in series with one MOS tube Pa in a plurality of equivalent MOS tubes, the series connection point is connected to one operational amplifier OP Amp, one input of the OP Amp is read voltage V_read, the output of the operational amplifier OP Amp is connected with the grid electrode of the MOS tube Pa, the grid electrode voltage of the MOS tube Pa is adjusted through a feedback effect, and the voltage at two ends of the memory cell is controlled to be equal to V_read.

The reference unit combination is formed by connecting N reference units in parallel; n equivalent MOS tubes Pbi (i=1, 2, …, N) in a row of multiple equivalent MOS tubes are connected in parallel, and one reference unit in the N reference units is connected in series with one MOS tube Pbi (i=1, 2, …, N) in the N MOS tubes connected in parallel; the series connection point is connected to one input of another operational amplifier OP Amp, the other input of which is a read voltage v_read, and the output of the operational amplifier OP Amp is connected to the gates of N MOS transistors Pbi (i=1, 2, …, N), and the gate voltages of the MOS transistors Pbi (i=1, 2, …, N) are adjusted by a feedback effect.

In a preferred embodiment of the present invention, N reference units combined by the reference unit are connected in series with a combination tube of N times the same MOS tube used for the memory unit, and an operational amplifier OP Amp is connected with the combination tube.

The voltage difference between the two ends of the equivalent MOS transistors and the reference unit is V_read_supply, and V_read < V_read_supply.

The voltages at both ends of the reference unit and the memory unit are locked to be equal to v_read by the operational amplifiers OP Amp, but the gate voltages outputted from the operational amplifiers OP Amp are different due to the difference of the resistances thereof, and the gate voltages of the two operational amplifiers OP Amp are compared by the comparator to output the result.

And when the MOS transistors are initialized, the equivalent MOS transistors are in a disconnected state, and the operation amplifier OpAmp is used for controlling to be opened so as to prevent the transient voltage from being too high.

The readout circuit disclosed by the embodiment is high in speed, and the risk of unstable readout can be eliminated.

The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention without requiring creative effort by one of ordinary skill in the art. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.

Claims

1. A high-speed MRAM readout circuit comprises a row of a plurality of equivalent MOS transistors, a reference unit combination, a comparator and two operational amplifiers OP Amp, and is characterized in that,

each storage unit is connected with one MOS tube Pa in the plurality of equivalent MOS tubes in series; the series connection point is connected to one input of one operational amplifier OP Amp, the other input of the operational amplifier OP Amp is a read voltage V_read, the output of the operational amplifier OP Amp is connected with the grid electrode of the MOS tube Pa, and the grid voltage of the MOS tube Pa is adjusted through a feedback effect;

the reference unit combination is formed by connecting N reference units in parallel; n equivalent MOS tubes Pbi in the row of multiple equivalent MOS tubes are connected in parallel, i=1, 2, …, N; the N reference units are connected with the N equivalent MOS tubes Pbi in series in a one-to-one correspondence manner; the series connection point is connected to one input of another operational amplifier OP Amp, the other input of the operational amplifier OP Amp is a read voltage V_read, the output of the operational amplifier OP Amp is connected with the grid electrodes of the N identical MOS tubes Pbi, and the grid voltage of the MOS tubes Pbi is adjusted through a feedback effect;

the voltage difference between the multiple equivalent MOS tubes and the two ends of the reference unit is V_read_supply;

2. The high-speed MRAM read circuit of claim 1, wherein the plurality of equivalent MOS transistors are in an off state upon initialization, and are controlled to be turned on by the operational amplifier OP Amp.

3. The high-speed MRAM read out circuit of claim 1, wherein N reference cells combined with the reference cells are in series a combination tube formed of N times the same MOS transistors as used for the memory cells, and the operational amplifier OP Amp is connected to the combination tube.