CN113744776B - Memory circuit, data writing and reading method thereof, memory and electronic equipment - Google Patents

Abstract

The invention can provide a memory circuit, a data writing and reading method thereof, a memory and an electronic device. The writing method comprises the following steps: a unidirectional current within a first preset range is introduced into a bottom electrode connected with the tunnel junction so as to write first data into the tunnel junction; or a unidirectional current within a second preset range is introduced into a bottom electrode connected with the tunnel junction so as to write second data into the tunnel junction. The absolute value of the current in the second preset range is larger than that in the first preset range, and the first data and the second data are opposite. The reading method comprises the following steps: a preset read voltage is applied to the tunnel junction to read out the data written in the tunnel junction. The memory circuit includes a bottom electrode, a tunnel junction, a first switching device, a second switching device, a bit line, a source line, and a read line. The invention changes the written data content by controlling the absolute value of the unidirectional current, so as to effectively solve at least one problem existing in the prior memory technology.

Description

Memory circuit and data writing and reading method thereof, memory, electronic device

Technical field

The present invention relates to the field of memory technology. More specifically, the present invention can provide memory circuits and data writing and reading methods thereof, memories, and electronic devices.

Background technique

Spin-Orbit TorqueMagnetic Random Access Memory (SOT-MRAM) refers to a random access memory that can store data by changing the magnetization state. It has the advantages of non-volatility, low power consumption, and radiation resistance. The most basic storage unit of spin orbit moment magnetic random access memory is a magnetic tunnel junction (MTJ). Usually, spin orbit moment magnetic random access memory requires an external magnetic field to assist writing, and two electrodes need to be passed through the bottom electrode. Opposite currents are used to write different information. Since the read and write channel separation of SOT-MRAM requires two transistors to control the read and write operations of the MTJ, this greatly increases the area of the storage array and reduces the storage density. In addition, how to increase the reliability of information writing is also a major difficulty.

Contents of the invention

In order to take into account the requirements of high reliability and high integration of magnetic random access memory, the present invention can provide a memory circuit and its data writing and reading methods, memory, and electronic equipment, which can achieve the requirements of high integration on the premise of meeting the requirements of high integration. Reliable control strategy achieves the purpose of memory data writing.

In order to achieve the above technical objectives, the present invention can provide a data writing method for a memory circuit. The data writing method includes but is not limited to one or more of the following steps. A unidirectional current within a first preset range is passed into the bottom electrode connected to the tunnel junction to write the first data to the tunnel junction; alternatively, the present invention passes a unidirectional current within a first preset range into the bottom electrode connected to the tunnel junction. Two unidirectional currents within a preset range are used to write second data to the tunnel junction. Wherein, the absolute value of the current in the second preset range is greater than the absolute value of the current in the first preset range, and the first data is opposite to the second data.

In order to achieve the above technical objectives, the present invention can provide a data reading method for a memory circuit, which method includes but is not limited to the following steps. A preset read voltage is applied to the tunnel junction connected to the bottom electrode to read out the first data or second data that has been written and stored in the tunnel junction.

In order to achieve the above technical objectives, the present invention can also provide a memory circuit, which may include but is not limited to a bottom electrode, a tunnel junction, a first switching device, a second switching device, a bit line, a source line and a read line. The bottom electrode of the present invention is used to pass a unidirectional current during the data writing process, and the tunnel junction is disposed on the bottom electrode and connected to the bottom electrode, and is used to store the written data. The first switching device is connected to the tunnel junction, the second switching device is connected to one end of the bottom electrode, the bit line is connected to the other end of the bottom electrode, the source line is connected to the second switching device, and the read line is connected to the first switching device.

In order to achieve the above technical objectives, the present invention can also specifically provide a memory, which may include but is not limited to the memory circuit in any embodiment of the present invention.

In order to achieve the above technical objectives, the present invention can also specifically provide an electronic device, which may include but is not limited to the memory in any embodiment of the present invention.

The beneficial effects of the present invention are: compared with the prior art, the present invention changes the written data content through the absolute value of the unidirectional current. By passing a horizontal current into the SOT bottom electrode, the current writing method of the present invention is determined by the size of the current, that is, a small current (absolute value) writes "0" (or "1"), and a large current (absolute value) writes "0" (or "1") Write "1" (or "0"). This method can effectively avoid problems such as complex control circuits, poor data writing reliability, or increased structural complexity of the device caused by repeated adjustments of the current direction. The invention reduces the requirements for memory circuit structure complexity and control logic complexity, and can help realize the miniaturization and miniaturization of SOT-MRAM memory devices, thereby meeting the requirements for manufacturing high-density SOT-MRAM memory devices.

Description of drawings

Figure 1 shows a schematic diagram of a tunnel junction writing curve in one or more embodiments of the present invention (the abscissa represents the voltage used to form a unidirectional current, and the ordinate represents the tunnel junction resistance).

Figure 2 shows a schematic structural diagram of a memory circuit in some embodiments of the present invention.

FIG. 3 shows a schematic structural diagram of a memory circuit including multiple memory cells in some embodiments of the present invention.

Figure 4 shows a schematic structural diagram of a memory circuit in other embodiments of the present invention.

FIG. 5 shows a schematic structural diagram of a memory circuit including multiple memory cells in other embodiments of the present invention.

Figure 6 shows a schematic structural diagram of a memory circuit in some embodiments of the present invention.

FIG. 7 shows a schematic structural diagram of a memory circuit including multiple memory cells in some embodiments of the present invention.

Figure 8 shows a schematic structural diagram of a tunnel junction in one or more embodiments of the present invention.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The drawings are not drawn to scale, with certain details exaggerated and may have been omitted for purposes of clarity. The shapes of the various regions and layers shown in the figures, as well as the relative sizes and positional relationships between them are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art will base their judgment on actual situations. Additional regions/layers with different shapes, sizes, and relative positions can be designed as needed.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present between them. element. Additionally, if one layer/element is "on" another layer/element in one orientation, then the layer/element can be "under" the other layer/element when the orientation is reversed.

The present invention can provide a data writing method for a memory circuit. Specifically, it can be a method for writing different data into a memory by using current magnitude. The memory involved in the present invention is specifically SOT-MRAM (SpinOrbitTorque-Magnetic Random Access Memory), that is, a spin-orbit coupling-magnetic random access memory unit. It can be seen that embodiments of the present invention can provide a method of using current magnitude to perform SOT-MRAM The method of writing data.

As shown in Figure 1, and in combination with Figures 2 to 8, the data writing method of the memory circuit can include but is not limited to the following steps: passing into the bottom electrode connected to the tunnel junction within a first preset range A unidirectional current in a second preset range to write the first data to the tunnel junction; or, a unidirectional current in a second preset range is passed into the bottom electrode connected to the tunnel junction in order to write a third data different from the first data. Two data to the tunnel junction. In this embodiment, the absolute value of the current in the second preset range is greater than the absolute value of the current in the first preset range, and the first data is opposite to the second data. The first data is "1" and the second data is "0"; or the first data is "0" and the second data is "1". The unidirectional current is a unidirectional current parallel to the extension direction of the bottom electrode. In this embodiment, the extension direction of the bottom electrode is the horizontal direction. The tunnel junction in one or more embodiments of the present invention may include, but is not limited to, a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer and a top electrode arranged in sequence; wherein the free layer is arranged on the bottom electrode .

Write a curve in conjunction with the tunnel junction in Figure 1. The unit of voltage can be, for example, V, and the unit of resistance can be, for example, Ω. The magnitude and direction of the unidirectional current in the present invention correspond to the applied voltage, and the current increases as the voltage increases. Large; the written data corresponds to the resistance of the tunnel junction, for example, the written data "1" corresponds to the high-resistance state, the written data "0" corresponds to the low-resistance state, or the written data " 0" corresponds to the high-resistance state, and the written data "1" corresponds to the low-resistance state; it can be understood that the resistance of the tunnel junction in the present invention increases as the absolute value of the unidirectional current increases. For the specific values of the first preset range, the second preset range and the corresponding voltage, the present invention can make corresponding settings according to the actual device composition. For example, the corresponding voltage of the first preset range is -1.5V ~ -1.5V; in the example The current value corresponding to the voltage boundary value (-1.5V or +1.5V) can be called the flip current. The present invention can write "1" when the writing current is greater than the flipping current, write "0" when it is less than the flipping current, or write If the input current is less than the flip current, "1" is written, and if it is greater than the flip current, "0" is written.

Specifically, in this embodiment, passing a unidirectional current within a first preset range into the bottom electrode connected to the tunnel junction includes: causing the unidirectional current to pass through the diode and the bottom electrode connected to the tunnel junction; the conduction direction of the diode It is the direction of unidirectional current, such as the direction from the source line to the bottom electrode or the direction from the bottom electrode to the source line. In embodiments of the present invention, the bit line can be used to connect to the other end of the bottom electrode, and the read line can be connected to the first switching device, and the first switching device is connected to the tunnel junction.

The antiferromagnetic layer in the embodiment of the present invention is, for example, an artificial antiferromagnetic layer. Among them, the free layer and the reference layer in the present invention realize ferromagnetic coupling (antiferromagnetism) through the tunnel layer, and the direction of the total magnetic moment of the reference layer and the artificial antiferromagnetic layer is antiparallel (parallel) to the reference layer. Therefore, the free layer is subject to the coupling field of the reference layer, and the magnetic field direction of the total of the reference layer and the artificial antiferromagnetic layer is opposite. When current is passed through the SOT bottom electrode, under the current within the first preset range (small current), the Joule heat is small, and the free layer flips to the direction of the coupling magnetic field between the reference layer and the free layer; under the current within the second preset range (large current) current), the Joule heat increases due to the increase in current, the temperature rises accordingly, and the coupling field of the reference layer to the free layer becomes smaller. At this time, the direction of the free layer is determined by the leakage magnetic field of the artificial antiferromagnetic layer and the reference layer. Decide. Since the leakage magnetic field and the coupling field are opposite in direction, the present invention can reverse the flipping direction of the free layer under the action of currents of different sizes, that is, realizing the transition between the high-resistance state and the low-resistance state of the tunnel junction under different currents. The conversion between them realizes the writing of data "0" or "1".

The data writing method of the memory circuit of the present invention is based on the same inventive technical concept. Correspondingly, the data reading method of a memory circuit of the present invention includes the following steps:

A preset read voltage (Vread) is applied to the tunnel junction connected to the bottom electrode to read out the first data or second data that has been written and stored in the tunnel junction through the above data writing method according to the embodiment of the present invention. . The data reading process in the present invention includes: applying a preset read voltage to the tunnel junction, and then judging that the tunnel junction is in a high resistance state by reading the feedback signal received by the read amplifier (the feedback signal can be a read current or charge amount, etc.) state or low resistance state.

As shown in Figure 3, and combined with Figure 2, this embodiment provides a process of writing data "1" or "0" to a memory array.

UL(Up Left) UR(Up Right) DL(Down Left) DR(Down Right) RL GND GND GND GND wL GND GND GND GND SL Vdd Vdd GND GND BL GND Vdd GND Vdd

As shown in the table above, write data to the memory cell in the upper left (UL), for example, write "1" in the high-resistance state, write "0" in the low-resistance state, or write "0" in the high-resistance state. Write "1" in low resistance state. In this embodiment, the source line (SL) 610 is connected to the level Vdd, and the bit line (BL) 510 is connected to the level GND to form a unidirectional current in the horizontal direction through the bottom electrode 100; and the read line (RL) is connected to the level GND. 710 is connected to the level GND, so that the word line (WL) 810 is connected to the level GND. At this time, the transistor 300 is in a closed state. The present invention can write "1" or "0" into the memory cell by changing the value of Vdd, that is, changing the data written in the tunnel junction by adjusting the size of the unidirectional current in the horizontal direction. At the same time, according to the fact that multiple memory cells along the x direction in the memory array share the source line 610, the source line 620, the read line 710, the read line 720, the word line 810 and the word line 820, the multiple memory cells along the y direction share the bit line 510. , bit line 520, in order to avoid writing data into the memory cells in the upper right (UR), lower left (DL), and lower right (DR), the source line (SL) 610 of the upper right (UR) memory cell is connected. Enter the level Vdd, connect the bit line (BL) 520 to the level Vdd, connect the read line (RL) 710 to the level GND, and connect the word line (WL) 810 to the level GND; to the lower left (DL) The source line (SL) 620 of the memory cell is connected to the level GND, the bit line (BL) 510 is connected to the level GND, the read line (RL) 720 is connected to the level GND, and the word line (WL) 820 is connected to the level GND. Input level GND; connect the source line (SL) 620 of the memory cell to the lower right (DR) to the level GND, connect the bit line (BL) 520 to the level Vdd, and connect the read line (RL) 720 to the voltage level. level GND, so that word line (WL) 820 is connected to level GND.

Similarly, when reading data from a memory unit, this embodiment still takes reading data from an upper left (UL) memory unit as an example for description.

UL UR D.L. DR RL Vread Vread GND GND wL vg vg GND GND SL GND GND GND GND BL GND Vread GND Vread

As shown in the above table, in this embodiment, the source line (SL) 610 is connected to the level GND, the bit line (BL) 510 is also connected to the level GND, and the read line (RL) 710 is connected to the level Vread. The word line (WL) 810 is connected to the level Vg; where Vread represents the preset read voltage, and Vg represents the gate voltage, which is used to turn on the metal oxide semiconductor field effect transistor 300 (transistor) by applying the preset read voltage Vread , a read current is generated in the MTJ to be read, and the sense amplifier receives the corresponding feedback signal to determine whether the current tunnel junction is in a low-resistance state or a high-resistance state, and then determines the data stored in the tunnel junction. At this time, according to the fact that multiple memory cells along the x direction in the memory array share source line 610, source line 620, read line 710, read line 720, word line 810, and word line 820, multiple memory cells along the y direction share a bit line. 510. Bit line 520. In order to avoid reading the data in the memory cells in the upper right (UR), lower left (DL), and lower right (DR), the source line (SL) 610 of the upper right (UR) memory cell is Connect the level GND, connect the bit line (BL) 520 to the level Vread, connect the read line (RL) 710 to the level Vread, and connect the word line (WL) 810 to the level Vg; to the lower left (DL ) of the memory cell, the source line (SL) 620 is connected to the level GND, the bit line (BL) 510 is connected to the level GND, the read line (RL) 720 is connected to the level GND, and the word line (WL) 820 Connect the level GND; connect the source line (SL) 620 of the memory cell on the lower right (DR) to the level GND, connect the bit line (BL) 520 to the level Vread, and connect the read line (RL) 720 The level GND, so that the word line (WL) 820 is connected to the level GND.

As shown in Figure 5, and combined with Figure 4, other embodiments of the present invention can also provide a process of writing data "1" or "0" to the memory array.

UL UR D.L. DR RL GND GND GND GND SL Vdd Vdd GND GND BL GND Vdd GND Vdd

As shown in the table above, write data to the memory cell in the upper left (UL), for example, write "1" in the high-resistance state, write "0" in the low-resistance state, or write "0" in the high-resistance state. Write "1" in low resistance state. In this embodiment, the source line (SL) 610 is connected to the level Vdd, and the bit line (BL) 510 is connected to the level GND to form a unidirectional current in the horizontal direction. The direction of the unidirectional current is consistent with the conduction direction of the diode. ; Make the read line (RL) 710 connect to the level GND. The present invention writes "1" or "0" into the memory unit by changing the value of Vdd. At this time, according to the fact that multiple memory cells in the memory array along the x direction share the source line 610, the source line 620, the read line 710, and the read line 720, and the multiple memory cells along the y direction share the bit line 510 and the bit line 520, as Avoid writing data to the memory cells in the upper right (UR), lower left (DL), and lower right (DR), and connect the source line (SL) 610 of the upper right (UR) memory cell to the level Vdd, so that The bit line (BL) 520 is connected to the level Vdd, so that the read line (RL) 710 is connected to the level GND; the source line (SL) 620 of the memory cell on the lower left (DL) is connected to the level GND, so that the bit line (BL) 510 is connected to the level GND, so that the read line (RL) 720 is connected to the level GND; the source line (SL) 620 of the memory cell on the lower right (DR) is connected to the level GND, so that the bit line (BL) is connected to the level GND. )520 is connected to the level Vdd, and the read line (RL) 720 is connected to the level GND.

Similarly, when reading data from the memory cells in the above memory array, the upper left (UL) memory cell is still used as an example.

UL UR D.L. DR RL Vread Vread GND GND SL GND GND GND GND BL GND Vread GND Vread

As shown in the above table, in this embodiment, the source line (SL) 610 is connected to the level GND, the bit line (BL) 510 is also connected to the level GND, and the read line (RL) 710 is connected to the level Vread, where Vread represents the preset read voltage. By applying the preset read voltage and reading the feedback signal received by the amplifier, it is judged whether the current tunnel junction is in a low-resistance state or a high-resistance state, and then the stored data is judged to be "1" or " 0". At this time, according to the fact that multiple memory cells in the memory array along the x direction share the source line 610, the source line 620, the read line 710, and the read line 720, and the multiple memory cells along the y direction share the bit line 510 and the bit line 520, as To avoid reading the data in the storage cells in the upper right (UR), lower left (DL), and lower right (DR), connect the source line (SL) 610 of the upper right (UR) storage unit to the level GND, so that The bit line (BL) 520 is also connected to the level Vread, and the read line (RL) 710 is connected to the level Vread; the source line (SL) 620 of the memory cell to the lower left (DL) is connected to the level GND, so that The bit line (BL) 510 is also connected to the level GND, so that the read line (RL) 720 is connected to the level GND; the source line (SL) 620 of the memory cell to the lower right (DR) is connected to the level GND, and the bit line (BL) 520 is connected to the level Vread, and the read line (RL) 720 is connected to the level GND.

As shown in Figure 7, and combined with Figure 6, some embodiments of the present invention can provide a process of writing data "1" or "0" to the memory array.

As shown in the table above, write data to the memory cell in the upper left (UL), for example, write "1" in the high-resistance state, write "0" in the low-resistance state, or write "0" in the high-resistance state. Write "1" in low resistance state. In this embodiment, the source line (SL) 610 is connected to the level GND, and the bit line (BL) 510 is connected to the level Vdd to form a unidirectional current in the horizontal direction; the read line (RL) 710 is connected to the level Vdd. . The present invention writes "1" or "0" into the memory unit by changing the value of Vdd. At this time, according to the fact that multiple memory cells in the memory array along the x direction share the source line 610, the source line 620, the read line 710, and the read line 720, and the multiple memory cells along the y direction share the bit line 510 and the bit line 520, as Avoid writing data to the memory cells in the upper right (UR), lower left (DL), and lower right (DR), and connect the source line (SL) 610 of the memory cell in the upper right (UR) to the level GND, so that The bit line (BL) 520 is connected to the level GND, so that the read line (RL) 710 is connected to the level Vdd; the source line (SL) 620 of the memory cell on the lower left (DL) is connected to the level Vdd, so that the bit line (BL) 510 is connected to the level Vdd, so that the read line (RL) 720 is connected to the level Vdd; the source line (SL) 620 of the memory cell on the lower right (DR) is connected to the level Vdd, so that the bit line (BL) is connected to the level Vdd. )520 is connected to the level GND, and the read line (RL) 720 is connected to the level Vdd.

Similarly, when reading data from the memory cells in the above memory array, the upper left (UL) memory cell is still used as an example.

UL UR D.L. DR RL GND GND Vread Vread SL Vread Vread Vread Vread BL Vread GND Vread GND

As shown in the above table, in this embodiment, the source line (SL) 610 is connected to the level Vread, the bit line (BL) 510 is also connected to the level Vread, and the read line (RL) 710 is connected to the level GND, where Vread represents the preset read voltage. Through the feedback signal received by the read amplifier after presetting the read voltage, it is judged whether the current tunnel junction is in a low-resistance state or a high-resistance state, and then the stored data is judged to be "1" or "0" ". At this time, according to the fact that multiple memory cells in the memory array along the x direction share the source line 610, the source line 620, the read line 710, and the read line 720, and the multiple memory cells along the y direction share the bit line 510 and the bit line 520, as To avoid reading the data in the storage cells in the upper right (UR), lower left (DL), and lower right (DR), connect the source line (SL) 610 of the upper right (UR) storage unit to the level Vread, so that The bit line (BL) 520 is also connected to the level GND, and the read line (RL) 710 is connected to the level GND; the source line (SL) 620 of the memory cell to the lower left (DL) is connected to the level Vread, so that The bit line (BL) 510 is also connected to the level Vread, so that the read line (RL) 720 is connected to the level Vread; the source line (SL) 620 of the memory cell to the lower right (DR) is connected to the level Vread, and the bit line (BL) 520 is connected to the level GND, and the read line (RL) 720 is connected to the level Vread.

As shown in Figure 2-3, based on the same inventive technical concept as the data writing method or reading method of the memory circuit, the present invention can provide a memory circuit. The memory circuit in one or more embodiments of the present invention includes but is not limited to the bottom electrode 100, the tunnel junction 200, the first switching device 300, the second switching device 400, the bit line BL (500, 510, 520), the source line SL (600, 610, 620), Read lines RL (700, 710, 720) and word lines (800, 810, 820), etc.

The bottom electrode 100 is used to pass a unidirectional current during the data writing process to write data into the tunnel junction 200 above the bottom electrode 100; in this embodiment, the bottom electrode 100 is specifically a layer with SOT (spin orbit coupling) Effect thin film electrode materials.

The tunnel junction 200 is disposed on the bottom electrode 100 and connected to the bottom electrode 100. In the embodiment of the present invention, the tunnel junction 200 is used to store written data. During the data reading process, a preset read voltage Vread is applied to the tunnel junction 200 to generate a read current. , thereby reading the data stored in the tunnel node.

As shown in Figure 8, the tunnel junction 200 in this embodiment is a multi-layer thin film structure. The tunnel junction 200 may include but is not limited to a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer and a top electrode arranged in sequence. . Among them, the antiferromagnetic layer in this embodiment is an artificial antiferromagnetic layer. In embodiments of the present invention, the bottom electrode 100, the free layer, the tunneling layer, the reference layer, the intermediate layer, and The antiferromagnetic layer and the top electrode, for example, form the SOT bottom electrode 100 by growing Ta (tantalum), Pt (platinum), W (tungsten), etc., and form the SOT bottom electrode 100 by growing Co (cobalt), CoFeB (a magnetic material), etc. layer.

As shown in Figures 2 and 3, the present invention can form a memory circuit through a memory array structure. The first switching device 300 is connected to the tunnel junction 200 , and the second switching device 400 is connected to one end of the bottom electrode 100 . Optionally, the first switching device 300 of the present invention is a metal oxide semiconductor field effect transistor (transistor), the second switching device 400 is a diode, and the conduction direction is from the source line (600, 610, 620) to the bottom electrode 100. Corresponding to the source line, the bit line (500, 510, 520) BL in the present invention is connected to the other end of the bottom electrode 100. Furthermore, the source line (600, 610, 620) SL is connected to the second switching device 400. In the present invention, the read line (700, 710, 720) RL is connected to the first switching device 300, and the word line (800, 810, 820) WL is connected to the gate of the metal oxide semiconductor field effect transistor.

The bottom electrode 100 and the tunnel junction 200 form a memory cell, and multiple memory cells may form a memory array. In the memory array of the embodiment of the present invention, multiple memory cells along the x direction share the source line 610, the source line 620, the read line 710, the read line 720, the word line 810 and the word line 820. The multiple memory cells along the y direction share Bit lines 510 and 520 are shared. The tunnel junction 200 of the present invention includes a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer and a top electrode arranged in sequence; wherein, the free layer is arranged on the bottom electrode 100 .

As shown in Figures 4-5, the data writing method or reading method of the memory circuit is based on the same inventive technical concept, and the present invention can also provide a memory circuit of another structural form. The memory circuit in one or more embodiments of the present invention may include, but is not limited to, a bottom electrode 100, a tunnel junction 200, a first switching device 300, a second switching device 400, a bit line BL (500, 510, 520), and a source line SL (600, 610, 620). And the reading line RL(700,710,720). The bottom electrode 100 is also used to pass a unidirectional current to it during the data writing process, thereby writing information into the tunnel junction 200 above the bottom electrode 100. It can be composed of an electrode material with a spin-orbit coupling effect. The tunnel junction 200 is disposed on the bottom electrode 100 and connected to the bottom electrode 100. Data can be read from the tunnel junction 200 by applying a preset read voltage to the read line RL above the tunnel junction. In the memory array of this embodiment, multiple memory cells along the x direction share source lines 610, 620, read lines 710, and read lines 720, and multiple memory cells along the y direction share bit lines 510 and 520. The tunnel junction 200 includes a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer and a top electrode arranged in sequence; wherein, the free layer of the present invention is arranged on the bottom electrode 100 .

As shown in Figures 4 and 5, different from the memory circuit structure in Figures 2 and 3, the first switching device 300 in this embodiment is a diode, and the conduction direction is from the read line (700, 710, 720) to the tunnel junction 200. The second switching device 400 in this embodiment is a diode, and the conduction direction is specifically the direction of the unidirectional current, which is the direction from the source line (600, 610, 620) to the bottom electrode 100 as shown in the figure. The bottom electrode 100 and the tunnel junction 200 form a memory cell, and a plurality of memory cells form a memory array.

As shown in Figures 6 and 7, the data writing method or reading method of the memory circuit is based on the same inventive technical concept, and the present invention can also provide memory circuits with other structural forms. The memory circuit in one or more embodiments of the present invention may include, but is not limited to, a bottom electrode 100, a tunnel junction 200, a first switching device 300, a second switching device 400, a bit line BL (500, 510, 520), and a source line SL (600, 610, 620). And the reading line RL(700,710,720). The bottom electrode 100 is also used to pass a unidirectional current to it during the data writing process to write data into the tunnel junction 200 above the bottom electrode 100. The bottom electrode may be made of a material with a spin-orbit coupling effect. The tunnel junction 200 is disposed on the bottom electrode 100 and connected to the bottom electrode 100. Data can be read from the tunnel junction 200 according to the feedback signal received by the sense amplifier after applying a preset read voltage to the tunnel junction. In the memory array of this embodiment, multiple memory cells along the x direction share source lines 610, 620, read lines 710, and read lines 720, and multiple memory cells along the y direction share bit lines 510 and 520. The tunnel junction 200 includes a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer and a top electrode arranged in sequence; the free layer is arranged on the bottom electrode 100 .

As shown in Figures 6 and 7, different from the memory circuit structure in Figures 2 and 3, the first switching device 300 in this embodiment is a diode, and the conduction direction is from the tunnel junction 200 to the read line (700, 710, 720). The second switching device 400 in this embodiment is a diode, and the conduction direction is specifically the direction of the unidirectional current, which is the direction from the bottom electrode 100 to the source line (600, 610, 620). The bottom electrode 100 and the tunnel junction 200 form a memory cell, and a plurality of memory cells form a memory array.

Based on the same inventive technical concept as the data writing or reading method of the memory circuit, the present invention can also provide a memory, which may include but is not limited to the memory circuit in any embodiment of the present invention.

Based on the same inventive technical concept as the data writing or reading method of the memory circuit, the present invention can also provide an electronic device, which may include but is not limited to the memory in any embodiment of the present invention.

It should be understood that the electronic devices involved in the present invention may include, but are not limited to, smart phones, computers, tablets, wearable smart devices, artificial intelligence devices, mobile power supplies, etc.

In the above description, there is no detailed explanation of the technical details such as patterning and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. in desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. In addition, although each embodiment is described separately above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (11)

1. A memory circuit, comprising:

the bottom electrode is used for introducing unidirectional current in the data writing process;

the tunnel junction is arranged on the bottom electrode and connected with the bottom electrode, and is used for storing written data;

a first switching device connected to the tunnel junction;

a second switching device connected to one end of the bottom electrode;

a bit line connected to the other end of the bottom electrode;

a source line connected to the second switching device;

a read line connected to the first switching device;

the unidirectional current is unidirectional current parallel to the extending direction of the bottom electrode;

the second switching device is a diode, the conduction direction is the same as the direction of the unidirectional current, and the memory circuit changes the written data content through the absolute value of the unidirectional current.

2. The memory circuit of claim 1, wherein,

the first switching device is a metal oxide semiconductor field effect transistor;

the memory circuit further includes a word line;

the word line is connected with the grid electrode of the metal oxide semiconductor field effect transistor.

3. The memory circuit of claim 1, wherein,

the first switching device is a diode, and the conducting direction is the direction from the reading line to the tunnel junction or the direction from the tunnel junction to the reading line.

4. A memory circuit according to any one of claims 1 to 3, wherein,

the bottom electrode and the tunnel junction form a memory cell;

a plurality of the memory cells form a memory array.

5. A memory circuit according to any one of claims 1 to 3, wherein,

the tunnel junction comprises a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer and a top electrode which are sequentially arranged;

wherein the free layer is disposed on the bottom electrode.

6. A data writing method of a memory circuit, which is implemented using the memory circuit of any one of claims 1 to 5, comprising:

a unidirectional current within a first preset range is introduced into a bottom electrode connected with a tunnel junction so as to write first data into the tunnel junction;

or, introducing unidirectional current in a second preset range into the bottom electrode connected with the tunnel junction so as to write second data into the tunnel junction;

the absolute value of the current in the second preset range is larger than that in the first preset range, and the first data are opposite to the second data.

7. The method of claim 6, wherein the supplying unidirectional current within a first predetermined range to the bottom electrode connected to the tunnel junction comprises:

the direction of the unidirectional current is the same as the conduction direction of a diode, and the diode is connected with the bottom electrode.

8. The method for writing data to a memory circuit according to claim 6 or 7, wherein,

the first data is "1", and the second data is "0";

alternatively, the first data is "0" and the second data is "1".

9. A data reading method of a memory circuit, which is implemented using the memory circuit of any one of claims 1 to 5, comprising:

a preset read voltage is applied to a tunnel junction connected to a bottom electrode to read out the first data or the second data which have been written in the tunnel junction.

10. A memory comprising the memory circuit of any one of claims 1 to 5.

11. An electronic device comprising the memory of claim 10.