CN114530426A - Fan-out type packaging device - Google Patents

Abstract

The present application discloses a fan-out package device, which includes: a first chip; a plurality of blocking members, surrounded by the first chip; and a plurality of conductive pillars, surrounded by the plurality of blocking members wherein, the height of the conductive pillar is greater than the height of the blocking member; the plastic encapsulation layer covers at least the side periphery of the first chip, the blocking member and the conductive pillar, the first chip, the The blocking member and the conductive column form an integral structure through the plastic encapsulation layer. Through the above device, the present application can reduce the warpage probability of the chip in the fan-out package device.

Description

Fan-Out Package Devices

technical field

The present application relates to the technical field of chip packaging, and in particular, to a fan-out packaged device.

Background technique

In the traditional fan-out packaging method, after the chip is plastic-sealed, the plastic sealing compound in the packaging structure is deformed due to shrinkage, which easily causes the chip to shift in the packaging structure and reduces the service life of the chip.

SUMMARY OF THE INVENTION

The main technical problem to be solved by the present application is to provide a fan-out package device, which can reduce the probability of chip warpage in the fan-out package device.

In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a fan-out package device, comprising: a first chip; a plurality of blocking members arranged around the periphery of the first chip; and a plurality of conductive pillars , surrounded by the plurality of blocking members; wherein, the height of the conductive pillars is greater than the height of the blocking members; the plastic sealing layer covers at least the first chip, the blocking members and the conductive pillars. On the periphery of the side surface, the first chip, the blocking member and the conductive pillar form an integral structure through the plastic encapsulation layer.

Wherein, the blocking member has electrical conductivity, and the blocking member and the conductive column are formed of the same material.

Wherein, a plurality of blocking members are connected to each other to form an annular structure.

Wherein, the fan-out package device further includes: insulating glue covering at least part of the side surface of the blocking member, and the plastic sealing layer covering the insulating glue.

Wherein, the first chip includes a first functional surface and a first non-functional surface arranged opposite to each other, and the conductive pillar, the blocking member and the plastic sealing layer are arranged flush with the first non-functional surface, so The first functional surface is located in the plastic sealing layer; the fan-out package device further includes: at least one second chip, including a second functional surface and a second non-functional surface arranged opposite to each other; the second functional surface Towards the first functional surface, the second functional surface spans at least a portion of the first functional surface and at least a portion of the blocking member adjacent to at least a portion of the first functional surface, and the first functional surface The pads on the two functional surfaces are electrically connected to the pads on the first functional surface at corresponding positions and the blocking member; underfill at least covers the second functional surface of the second chip and the carrier the gap between the plates and the stopper.

Wherein, the side of the plastic encapsulation layer facing away from the first functional surface is flush with the second non-functional surface and the conductive column.

Wherein, the first chip includes a first functional surface and a first non-functional surface disposed opposite to each other, the conductive pillar, the blocking member and the plastic sealing layer are disposed flush with the first functional surface, the The first non-functional surface is located in the plastic encapsulation layer.

Wherein, the fan-out device further includes: a first redistribution layer, located on a surface of the plastic encapsulation layer adjacent to the first functional surface; wherein the first redistribution layer is at least connected to the first chip and the first functional surface. One end of the conductive column is electrically connected; a second redistribution layer is located on a surface of the plastic encapsulation layer on one side adjacent to the first non-functional surface; wherein the second redistribution layer is electrically connected to the other end of the conductive column connect.

Wherein, the fan-out package device further includes: a first electrical connector, located on the side of the first redistribution layer away from the plastic encapsulation layer, and electrically connected to the first redistribution layer; a second electrical connection The body is located on the side of the second redistribution layer away from the plastic sealing layer, and is electrically connected to the second redistribution layer.

Wherein, the height of the plastic sealing layer is the same as the height of the conductive column, and both ends of the conductive column in the length direction are exposed from the plastic sealing layer.

The beneficial effects of the present application are: different from the situation in the prior art, in the fan-out package device proposed in the present application, a plurality of blocking members are arranged on the periphery of the first chip, and the blocking members help limit the plastic sealing in the plastic sealing layer. The movement of the material can reduce the amount of deformation of the molding compound due to shrinkage and reduce the probability of chip warpage. In addition, the conductive pillars can realize a three-dimensional vertical interconnection structure, which is beneficial to reduce the height of the fan-out package device, and the design of the blocking members and conductive pillars of different heights can also effectively save the material cost.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. in:

FIG. 1 is a schematic structural diagram of an embodiment of a fan-out package device of the present application;

FIG. 2 is a schematic structural diagram of another embodiment of the fan-out package device of the present application;

3 is a schematic flowchart of an embodiment of a method for manufacturing a fan-out packaged device of the present application;

FIG. 4 is a schematic structural diagram of steps S101-S105 in FIG. 3 corresponding to one embodiment;

5 is a schematic flowchart corresponding to an embodiment after step S105;

FIG. 6 is a schematic structural diagram of steps S201-S202 in FIG. 5 corresponding to an embodiment.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of an embodiment of a fan-out package device proposed in the present application. The fan-out package device provided by the present application includes: a first chip 100, a plurality of blocking members 20, a plurality of Conductive pillars 30 and plastic encapsulation layer 50 .

Specifically, the first chip 100 includes a first functional surface 101 and a first non-functional surface 102 disposed opposite to each other, and a plurality of first pads 103 are disposed on the first functional surface 101 . In this embodiment, the number of the first chips 100 may be multiple, and the chip types may be the same or different.

A plurality of blocking members 20 are arranged around the periphery of the first chip 100 . As shown in FIG. 1 , a plurality of blocking members 20 may be arranged at intervals. Of course, in other embodiments, a plurality of blocking members 20 may also be connected to each other to form an annular structure. That is, at this time, the plurality of blocking members 20 are equivalent to forming a ring or other annular structures surrounding the side periphery of the first chip 100 . The blocking member 20 helps to limit the movement of the molding compound in the molding layer 50 , so as to reduce the amount of deformation of the molding compound due to shrinkage, and reduce the probability of chip warpage. In addition, the blocking member 20 has conductivity, and its material can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. This design method can enable the blocking member 20 and the conductive pillar 30 to be fabricated and formed at the same time, so as to reduce the difficulty of process fabrication.

The plurality of conductive pillars 30 are arranged around the periphery of the plurality of blocking members 20 , and the height of the conductive pillars 30 is greater than that of the blocking members 20 . The conductive pillars 30 can realize a three-dimensional vertical interconnection structure, which is beneficial to reduce the height of the fan-out package device, and the design of the blocking members 20 and the conductive pillars 30 with different heights can also effectively save the material cost. Optionally, the material of the conductive column 30 may be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. When the barrier 20 has conductivity, the conductive pillar 30 and the barrier 20 may be formed of the same material.

The plastic packaging layer 50 at least covers the side periphery of the first chip 100 , the blocking member 20 and the conductive pillar 30 , and the first chip 100 , the blocking member 20 and the conductive pillar 30 form an integral structure through the plastic packaging layer 50 . The conductive pillar 30 , the blocking member 20 and the plastic sealing layer 50 are disposed flush with the first non-functional surface 102 , and the first functional surface 101 is located in the plastic sealing layer 50 . The height of the plastic encapsulation layer 50 is the same as the height of the conductive pillars 30 , and both ends of the conductive pillars 30 in the longitudinal direction are exposed from the plastic encapsulation layer 50 . The material of the plastic encapsulation layer 50 may be epoxy resin or the like, and the formation of the plastic encapsulation layer 50 can play a certain role in fixing and protecting the devices in the encapsulation structure.

In the fan-out package device provided by the present application, a plurality of blocking members 20 are arranged on the periphery of the first chip 100 , and the blocking members 20 help to limit the movement of the plastic sealing compound in the plastic sealing layer 50 , so as to reduce the shrinkage of the plastic sealing material due to shrinkage. The generated deformation amount reduces the probability of warping of the first chip 100 . In addition, the conductive pillars 30 can realize a three-dimensional vertical interconnection structure, which is beneficial to reduce the height of the fan-out package device, and the design of the blocking members 20 and the conductive pillars 30 with different heights can also effectively save the material cost.

In one embodiment, please continue to refer to FIG. 1 , the fan-out package device provided by the present application further includes an insulating glue 40 , the insulating glue 40 covers at least part of the side surface of the blocking member 20 , the plastic sealing layer 50 covers the insulating glue 40 , and the insulating The glue 40 can limit and protect the blocking member 20 to a certain extent. Optionally, the insulating glue 40 may be formed by dispensing, and the outer surface of the insulating glue 40 may be an arc surface.

In yet another embodiment, please continue to refer to FIG. 1, the fan-out device provided by the present application further includes at least one second chip 200, including a second functional surface 201 and a second non-functional surface 202 disposed opposite to each other. A plurality of second pads 203 are disposed on the dual-function surface 201 . The second functional surface 201 faces the first functional surface 101, the second functional surface 201 spans at least part of the first functional surface 101, and at least part of the blocking member 20 adjacent to at least part of the first functional surface 101, and the second functional surface 201 The second pad 203 on the surface 201 is electrically connected to the first pad 103 on the first functional surface 101 at the corresponding position and the blocking member 20 at the corresponding position. Wherein, conductive bumps may be provided between the second pads 203 and the first pads 103 at corresponding positions to facilitate the electrical connection between the second pads 203 and the first pads 103 . The plastic encapsulation layer 50 can fix and protect the second chip 200 ; the side of the plastic encapsulation layer 50 facing away from the first functional surface 101 is flush with the second non-functional surface 202 and the conductive pillar 30 , which helps to reduce the fan-out type The thickness of the packaged device improves the heat dissipation effect. In this embodiment, the number of the second chips 200 may be 1, 2, 3, etc., and the second chips 200 and the first chip 100 can perform information interaction, which improves the functionality of the fan-out device. In addition, an underfill 55 is disposed between at least the second functional surface 201 of the second chip 200 and the carrier board 10 , and the blocking member 20 is located in the underfill 55 to prevent the first chip 100 , the second chip 200 and the The blocking member 20 plays a certain role of fixing and protecting. Specifically, in this application, the vertical section of the underfill 55 is a trapezoid, which can improve the stability of the fan-out device; in other applications, the vertical section of the underfill 55 may also be a rectangle or the like. Optionally, the side of the underfill 55 facing away from the first non-functional surface 102 may be flush with the second functional surface 201 of the second chip 200 , or may be higher than the second functional surface 201 of the second chip 200 . This is not limited. In addition, in other embodiments, the underfill 55 may not be provided.

In another embodiment, please continue to refer to FIG. 1 , the fan-out device provided by this application further includes:

The first redistribution layer 60 is located on the side surface of the plastic sealing layer 50 adjacent to the first non-functional surface 102 . The first redistribution layer 60 is electrically connected to at least one end of the first chip 100 and the conductive pillar 30 . The first redistribution layer 60 includes a dielectric layer and a patterned metal layer, and the number of layers of the first redistribution layer 60 may be one or more layers. The first redistribution layer 60 may be electrically connected to the first chip 100 and the second chip 200 , so that other devices are electrically connected to the first chip 100 and the second chip 200 through the first redistribution layer 60 .

The second redistribution layer 70 is located on the side surface of the plastic sealing layer 50 adjacent to the first functional surface 101 . The second redistribution layer 70 is electrically connected to the other end of the conductive pillar 30 . The second redistribution layer 70 also includes a dielectric layer and a patterned metal layer, and the number of layers of the second redistribution layer 70 may be one or more layers. Based on the fact that the first redistribution layer 60 and the second redistribution layer 70 are connected through the conductive pillars 30 , the second redistribution layer 70 is also electrically connected to the first chip 100 and the second chip 200 , so as to help the fan-out device be opposite to each other. Both sides of the chip can realize electrical connection with the first chip 100 and the second chip 200 .

In another embodiment, please continue to refer to FIG. 1 , the fan-out package device provided by the present application further includes:

The first electrical connection body 80 is located on the side of the first redistribution layer 60 away from the plastic sealing layer 50 and is electrically connected to the first redistribution layer 60 . The second electrical connection body 90 is located on the side of the second redistribution layer 70 away from the plastic sealing layer 50 , and is electrically connected to the second redistribution layer 70 . A plurality of solder balls 85 are disposed between the first electrical connection body 80 and the first redistribution layer 60 and between the second electrical connection body and the second redistribution layer 70 . The material of the first electrical connector 80 and the second electrical connector 90 may be titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, or the like. The first electrical connector 80 and the second electrical connector 90 facilitate the connection of the fan-out device to the substrate or other devices.

In the above-mentioned embodiment, the first functional surface 101 of the first chip 100 in FIG. Of course, in other embodiments, the first non-functional surface 102 of the first chip 100 may also be located in the plastic packaging layer 50 , and the first functional surface 101 of the first chip 100 is flush with one side surface of the plastic packaging layer 50 . Please refer to FIG. 2 for details. FIG. 2 is a schematic structural diagram of another embodiment of the fan-out package device of the present application. The fan-out packaged devices provided in this application include:

The first chip 100 includes a first functional surface 101 and a first non-functional surface 102 disposed opposite to each other, and a plurality of first bonding pads 103 are disposed on the first functional surface 101 . In this embodiment, the number of the first chips 100 may be multiple, and the chip types may be the same or different.

A plurality of blocking members 20 are arranged around the periphery of the first chip 100 , and the plurality of blocking members 20 may be arranged at intervals. Of course, in other embodiments, the plurality of blocking members 20 may also be connected to each other to form a ring structure, that is, at this time, the plurality of blocking members 20 are equivalent to forming a ring or other ring structures arranged around the side periphery of the first chip 100 . The blocking member 20 helps limit the movement of the molding compound in the molding layer 50 , so as to reduce the deformation of the molding compound due to shrinkage, and reduce the probability of warping of the core. One end of the blocking member 20 is flush with the side of the first functional surface 101 of the first chip 100 . The blocking member 20 has conductivity, and its material can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper.

The plurality of conductive pillars 30 are arranged around the periphery of the plurality of blocking members 20 , and the height of the conductive pillars 30 is greater than that of the blocking members 20 . Optionally, the material of the conductive column 30 may be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. When the conductive pillar 30 has conductivity, the conductive pillar 30 and the stopper 20 may be formed of the same material.

The plastic packaging layer 50 at least covers the side periphery of the first chip 100 , the blocking member 20 and the conductive pillar 30 , and the first chip 100 , the blocking member 20 and the conductive pillar 30 form an integral structure through the plastic packaging layer 50 . The material of the plastic encapsulation layer 50 may be epoxy resin or the like, and the formation of the plastic encapsulation layer 50 can play a certain role in fixing and protecting the devices in the encapsulation structure. At this time, the first non-functional surface 102 of the first chip 100 may also be located in the plastic packaging layer 50 , and the first functional surface 101 of the first chip 100 is flush with one side surface of the plastic packaging layer 50 .

In one embodiment, please continue to refer to FIG. 2 , the fan-out package device proposed in the present application further includes an insulating adhesive 40 , the insulating adhesive 40 covers at least part of the side surface of the blocking member 20 , the plastic sealing layer 50 covers the insulating adhesive 40 , and the insulating The glue 40 can limit and protect the blocking member 20 to a certain extent. Optionally, the insulating glue 40 may be formed by dispensing, and the outer surface of the insulating glue may be an arc surface.

In yet another embodiment, please continue to refer to FIG. 2 , the fan-out device proposed in this application further includes:

The first redistribution layer 60 is located on the side surface of the plastic sealing layer 50 adjacent to the first functional surface 101 . The first redistribution layer 60 is electrically connected to at least one end of the first chip 100 , the blocking member 20 and the conductive pillar 30 . The first redistribution layer 60 includes a dielectric layer and a patterned metal layer, and the number of layers of the first redistribution layer 60 may be one or more layers. Providing the first redistribution layer 60 facilitates the electrical connection between the first chip 100 and other devices.

The second redistribution layer 70 is located on the side surface of the plastic sealing layer 50 adjacent to the first non-functional surface 102 . The second redistribution layer 70 is electrically connected to the other end of the conductive pillar 30 . The second redistribution layer 70 also includes a dielectric layer and a patterned metal layer, and the number of layers of the second redistribution layer 70 may be one or more layers. Based on the connection between the first redistribution layer 60 and the second redistribution layer 70 through the conductive pillars 30 , the second redistribution layer 70 is also electrically connected to the first chip 100 .

In another embodiment, please continue to refer to FIG. 2 , the fan-out package device proposed in this application further includes:

The first electrical connection body 80 is located on the side of the first redistribution layer 60 away from the plastic sealing layer 50 and is electrically connected to the first redistribution layer 60 . The second electrical connection body 90 is located on the side of the second redistribution layer 70 away from the plastic sealing layer 50 , and is electrically connected to the second redistribution layer 70 . A plurality of solder balls 85 are disposed between the first electrical connection body 80 and the first redistribution layer 60 and between the second electrical connection body and the second redistribution layer 70 . The material of the first electrical connector 80 and the second electrical connector 90 may be titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, or the like. The first electrical connector 80 and the second electrical connector 90 facilitate the connection of the fan-out device to the substrate or other devices.

The specific preparation process of the fan-out packaged device shown in FIG. 1 is described in detail below with a specific application scenario. Please refer to FIGS. 3 and 4 . FIG. 3 is a schematic flowchart of an embodiment of a method for manufacturing a fan-out packaged device of the present application. FIG. 4 is a schematic structural diagram of steps S101 to S105 in FIG. Packaging methods include:

S101: Provide a carrier board 10, the carrier board 10 includes a first surface 11 and a second surface 12 that are arranged opposite to each other.

Specifically, as shown in FIG. 4a, the material of the carrier board 10 may be a hard material such as metal, silicon, plastic, etc., and the first surface 11 of the carrier board 10 is preferably horizontal.

S102 : Disposing at least one first chip 100 on the side of the first surface 11 of the carrier board 10 .

Specifically, the first chip 100 includes a first functional surface 101 and a first non-functional surface 102 disposed opposite to each other, and a plurality of bonding pads 103 are disposed on the first functional surface 101 . As shown in FIG. 4b, FIG. 4b is only schematic, and only one first chip 100 is drawn in FIG. 4b, but in this embodiment, the number of first chips 100 can be separated by 1, 2, 3, etc. It is disposed on the side of the first surface 11 of the carrier board 10 .

S103: Disposing a plurality of blocking members 20 and a plurality of conductive pillars 30 on the side of the carrier board 10 where the first chip 100 is disposed.

Specifically, as shown in FIG. 4 c , a plurality of blocking members 20 are surrounded on the periphery of the first chip 100 ; and a plurality of conductive pillars 30 are surrounded on the periphery of the plurality of blocking members 20 . Wherein, the height of the conductive pillar 30 is greater than the height of the blocking member 20 . In addition, the blocking member 20 has electrical conductivity, and the blocking member 20 and the conductive column 30 are formed of the same material, which can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably for titanium or copper. The arrangement of the conductive pillars 30 helps to realize a three-dimensional vertical interconnection structure of the fan-out device, and the arrangement of the blocking member 20 helps to improve the stability of the fan-out device.

Further, in this embodiment, the fan-out package device further includes insulating glue 40 , and the insulating glue 40 at least covers at least part of the side surface of the blocking member 20 to play a certain role in fixing and protecting the blocking member 20 . Wherein, the insulating glue 40 can be formed by dispensing glue, and the surface of the insulating glue 40 is arc-shaped based on the surface tension of the glue. Optionally, the insulating glue 40 can also be formed on the periphery of the plurality of blocking members 20 by methods such as glue dispensing.

In this embodiment, the plurality of blocking members 20 and the plurality of conductive pillars 30 may be formed by disposing a photoresist layer on the side of the first surface 11 of the carrier board 10 . Specifically, a first photoresist layer can be formed on the side of the first surface 11 , and the first photoresist layer can be exposed and developed to form a first via hole, and a conductive metal can be filled in the first via hole to form a barrier Piece 20. Further, a second photoresist layer is formed on the side of the first photoresist layer away from the carrier plate 10, and a part of the second photoresist layer and the first photoresist layer are exposed and developed at the same time to generate a second via hole , filling the second via hole with conductive metal to form a conductive pillar 30 with a height higher than that of the blocking member 20 . Optionally, a photoresist layer with grooves can also be provided on the side of the first surface 11 of the carrier plate 10, and the photoresist layer is exposed and developed to generate the first via hole and the second via hole, wherein the first via hole and the second via hole are formed. A via hole is located at the bottom of the groove, and a second via hole is located at the sidewall of the groove. The first via hole and the second via hole are filled with conductive metal at the same time to generate the blocking member 20 and the conductive pillar 30. The height of the conductive pillar 30 higher than the stopper 20 . In addition, the blocking member 20 and the conductive pillar 30 can also be generated by disposing a first photoresist layer and a second photoresist layer on the side of the first surface 11 of the carrier 10, wherein the first photoresist layer and the second photoresist layer One of the photoresist layers is a positive photoresist, and the other is a negative photoresist, and the specific implementation process is not repeated here. Wherein, after the blocking member 20 and the conductive pillars 30 are formed by using photoresist, a portion of the photoresist around the blocking member 20 may be reserved to serve as the insulating glue 40 to fix and protect the blocking member 20 to a certain extent.

S104: Disposing at least one second chip 200 on one side of the first functional surface 101 of the first chip 100, and forming underfill at least between the second functional surface of the second chip and the carrier board.

Specifically, as shown in FIG. 4d, FIG. 4d is only schematic, and only two second chips 200 are shown in FIG. The second chip 200 of 3 and so on. The second chip 200 includes a second functional surface 201 and a second non-functional surface 202 disposed opposite to each other; the second functional surface 201 faces the first functional surface 101 , and the second functional surface 201 spans at least the first functional surface 101 part, and at least part of the blocking member 20 adjacent to at least part of the first functional surface 101, and the second pad 203 on the second functional surface 201 and the first pad 103 on the first functional surface at the corresponding position and the barrier Pieces 20 are electrically connected.

Further, an underfill 55 is formed at least between the second functional surface 201 of the second chip 200 and the carrier board 10 , and the blocking member 20 is located in the underfill 55 . Optionally, the side of the underfill 55 facing away from the carrier board 10 may be flush with the second functional surface 201 of the second chip 200 , or may be higher than the second functional surface 201 of the second chip 200 . In addition, in other embodiments, it may not be the underfill 55 , that is, step S105 is directly executed after the second chip 200 is disposed.

S105 : forming a plastic encapsulation layer 50 on the side of the carrier board 10 where the first chip 100 is disposed.

Specifically, as shown in FIG. 4e , the fan-out package device proposed in the present application further includes a plastic sealing layer 50 , and the plastic sealing layer 50 at least covers the side periphery of the first chip 100 , the insulating glue 40 , the blocking member 20 and the conductive pillar 30 , The first chip 100 , the blocking member 20 and the conductive pillars 30 form an integral structure through the molding layer 50 . The conductive pillars 30 , the blocking member 20 and the plastic sealing layer 50 are disposed flush with the first non-functional surface 102 , and the first functional surface 101 is located in the plastic sealing layer 50 . In addition, the side of the plastic encapsulation layer 50 away from the carrier board 10 may be ground so that the side of the plastic encapsulation layer 50 away from the first functional surface 101 is flush with the second non-functional surface 202 and the conductive pillars 30 . Further, the plastic encapsulation layer 50 around the conductive pillar 30 is cut to obtain a single fan-out packaged device.

In another application manner, before step S105 , the first functional surface 101 of the first chip 100 may also face the carrier board 10 , and then the plastic encapsulation layer 50 is formed on the side of the carrier board 10 where the first chip 100 is disposed through step S105 .

Please refer to FIG. 5 and FIG. 6 , FIG. 5 is a schematic flow chart corresponding to an embodiment after step S105, FIG. 6 is a schematic structural diagram of steps S201-S202 in FIG. 5 corresponding to an embodiment, and after step S105, it further includes:

S201 : The carrier board 10 is removed, and the first redistribution layer 60 and the second redistribution layer 70 are provided.

Referring to FIG. 6 a , the first redistribution layer 60 is located on a surface of the plastic encapsulation layer 50 adjacent to the first non-functional surface 102 . The first redistribution layer 60 is electrically connected to at least one end of the first chip 100 and the conductive pillar 30 . The second redistribution layer 70 is located on the side surface of the plastic sealing layer 50 adjacent to the first functional surface 101 .

S202 : the first electrical connection body 80 is provided on the side of the first redistribution layer 60 away from the plastic sealing layer 50 , and the second electrical connection body 90 is provided on the side of the second redistribution layer 70 away from the plastic sealing layer 50 .

Specifically, referring to FIG. 6b, the first electrical connection body 80 is located on the side of the first redistribution layer 60 away from the plastic sealing layer 50, and is electrically connected to the first redistribution layer 60; the second electrical connection body 90 is located at the second redistribution layer 50. The layer 70 faces away from the molding layer 50 and is electrically connected to the second redistribution layer 70 . Among them, a plurality of solder balls 85 are provided between the first redistribution wiring 60 and the first electrical connection body 80 and between the second redistribution layer 70 and the second electrical connection body 90 .

Of course, in another preparation process, the first functional surface 101 of the first chip 100 can also be disposed toward the carrier board 10 before the above step S105 , and the plastic encapsulation layer 50 can be formed on the side where the first chip 100 is disposed on the carrier board through step S105 . Further, the redistribution layer and the electrical connection body are arranged through the steps in FIG. 5 .

The above description is only an embodiment of the present application, and is not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies Fields are similarly included within the scope of patent protection of this application.

Claims (10)

1. A fan-out packaged device, comprising:

a first chip;

the plurality of blocking parts are arranged around the first chip;

the conductive posts surround the barriers; wherein the height of the conductive post is greater than the height of the blocking member;

and the plastic packaging layer at least covers the first chip, the blocking piece and the periphery of the side face of the conductive post, and the first chip, the blocking piece and the conductive post form an integral structure through the plastic packaging layer.

2. The fan-out packaged device of claim 1,

the blocking member has conductive properties, and the blocking member and the conductive post are formed of the same material.

3. The fan-out package device of claim 1 or 2,

a plurality of the barriers are interconnected to form a ring-shaped structure.

4. The fan-out package device of claim 1 or 2, further comprising:

and the insulating glue at least covers at least part of the side face of the barrier piece, and the plastic packaging layer covers the insulating glue.

5. The fan-out package device of claim 2, wherein the first chip comprises a first functional side and a first non-functional side that are opposite to each other, the conductive posts, the blocking members, and the molding layer are flush with the first non-functional side, and the first functional side is located in the molding layer; the fan-out package device further comprises:

at least one second chip, including a second functional surface and a second non-functional surface which are arranged oppositely; the second functional surface faces the first functional surface, the second functional surface spans at least part of the first functional surface and at least part of the stopper adjacent to at least part of the first functional surface, and a second pad on the second functional surface is electrically connected with the first pad on the first functional surface and the stopper at a corresponding position;

and the underfill at least covers the gap between the second functional surface of the second chip and the carrier plate and the barrier.

6. The fan-out packaged device of claim 5,

the plastic packaging layer deviates from one side of the first functional surface and is flush with the second non-functional surface and the conductive column.

7. The fan-out package device of claim 2,

the first chip comprises a first functional surface and a first non-functional surface which are arranged in a back-to-back mode, the conductive column, the blocking piece and the plastic package layer are flush with the first functional surface, and the first non-functional surface is located in the plastic package layer.

8. The fan-out package device of any one of claims 5-7, further comprising:

the first rewiring layer is positioned on one side surface, adjacent to the first non-functional surface, of the plastic packaging layer; wherein the first redistribution layer is electrically connected to at least one end of the first chip and the conductive pillar;

the second rewiring layer is positioned on the surface of one side, close to the first functional surface, of the plastic packaging layer; wherein the second redistribution layer is electrically connected to the other end of the conductive pillar.

9. The fan-out package device of claim 8, further comprising:

the first electric connector is positioned on one side, away from the plastic packaging layer, of the first redistribution layer and is electrically connected with the first redistribution layer;

and the second electric connector is positioned on one side of the second rewiring layer, which is deviated from the plastic packaging layer, and is electrically connected with the second rewiring layer.

10. The fan-out package device of claim 8,

the height of the plastic package layer is the same as that of the conductive columns, and two ends of the conductive columns in the length direction are exposed out of the plastic package layer.

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