CN114530385A - Fan-out type packaging method - Google Patents

Abstract

The application discloses a fan-out type packaging method, which comprises the following steps: sequentially forming a first photoresist layer and a second photoresist layer on the first surface of the carrier plate; one of the first photoresist layer and the second photoresist layer is a positive photoresist, and the other one of the first photoresist layer and the second photoresist layer is a negative photoresist; exposing and developing the first photoresist layer and the second photoresist layer at the same time, wherein a plurality of first through holes are formed in the first photoresist layer, and a plurality of second through holes are formed in the second photoresist layer positioned on the periphery of the side face of the first photoresist layer; forming a barrier within the first via and a conductive post within the second via; and removing the first photoresist layer and the second photoresist layer. Through the mode, the probability of chip warping can be reduced, the height of the fan-out type device is reduced, and material cost is saved.

Description

Fan-Out Packaging Method

technical field

The present application relates to the technical field of chip packaging, and in particular, to a fan-out packaging method.

Background technique

In the existing chip packaging method, the chip is packaged into a complete chip packaging structure through plastic packaging material, but in the subsequent use process, the plastic packaging material is easily deformed due to shrinkage, causing the chip to shift within the packaging structure, thereby reducing the number of chips. service life.

SUMMARY OF THE INVENTION

The main technical problem to be solved by the present application is to provide a fan-out packaging method, which can reduce the amount of deformation of the plastic packaging material due to shrinkage and ensure the stability of the chip.

In order to solve the above-mentioned technical problems, a technical solution adopted in the present application is to provide a fan-out packaging method, which includes: forming a first photoresist layer and a second photoresist layer on the first surface of the carrier plate successively; wherein , one of the first photoresist layer and the second photoresist layer is a positive photoresist, and the other is a negative photoresist; and the second photoresist layer covers the first photoresist A side surface of a photoresist layer and a surface of the first photoresist layer away from the carrier board; the first photoresist layer and the second photoresist are exposed and developed at the same time, and the first photoresist layer and the second photoresist are exposed and developed simultaneously. A plurality of first via holes are formed on a photoresist layer, and a plurality of second via holes are formed on the second photoresist layer located on the side periphery of the first photoresist layer; wherein, the second The height of the via hole is greater than the height of the first via hole; forming a blocking member in the first via hole, and forming a conductive column in the second via hole; removing the first photoresist layer and all the the second photoresist layer.

Wherein, the blocking member has conductive performance; and the steps of forming the blocking member in the first via hole and forming a conductive column in the second via hole include: forming the first via hole and all the conductive pillars in the second via hole. The second via hole is filled with conductive material at the same time to form the blocking member and the conductive column.

Wherein, after the step of removing the first photoresist layer and the second photoresist layer, the steps include: arranging a first chip in an area surrounded by a plurality of the blocking members; A plastic encapsulation layer is formed on the side where the first chip is disposed, so that the first chip, the blocking member and the conductive column form an integral structure; and the carrier plate is removed.

Wherein, before the step of successively forming a first photoresist layer and a second photoresist layer on the first surface of the carrier board, the step includes: disposing a first chip on the first surface of the carrier board; wherein, When the first photoresist layer and the second photoresist layer are formed on the first surface of the carrier, the side of the second photoresist layer facing away from the carrier is opposite to the first chip and facing away from the carrier One side of the board is away from the carrier board; after the step of removing the first photoresist layer and the second photoresist layer, the step includes: forming on the side of the carrier board where the first chip is arranged A plastic encapsulation layer is formed, so that the first chip, the blocking member and the conductive column form an integral structure; and the carrier plate is removed.

Wherein, the first chip includes a functional surface and a non-functional surface arranged opposite to each other, and the non-functional surface of the first chip faces the carrier; the first photoresist layer and the second photoresist layer are When the adhesive layer is exposed and developed at the same time, a plurality of third via holes are formed on the photoresist layer covering the functional surface of the first chip, and one of the third via holes is related to the function of the first chip. The pads on the surface correspond to each other; while the conductive pillars are formed in the second via holes, conductive bumps are formed in the third via holes.

Wherein, the step of forming a plastic sealing layer on the side where the first chip is arranged on the carrier board includes: forming a plastic sealing layer on the side where the first chip is arranged on the carrier board, and the plastic sealing layer covers the The conductive column and the gap in the space surrounded by the conductive column; wherein, the plastic sealing layer is flush with the surface of the conductive column on the side away from the carrier board.

Wherein, the first chip includes a first functional surface and a first non-functional surface arranged opposite to each other, and the first non-functional surface of the first chip faces the carrier board; Before the step of forming the plastic encapsulation layer on the side of the first chip, the method further includes: arranging at least one second chip on the side of the first functional surface of the first chip away from the carrier board, and at least one second chip on the side of the second chip. An underfill is formed between the second functional surface and the carrier, and the blocking member is located in the underfill; wherein the second functional surface of the second chip faces the first functional surface of the first chip , the second chip spans at least part of the first chip and at least part of the blocking member adjacent to at least part of the first chip, and the pads on the second functional surface of the second chip electrically connected to the pad on the first functional surface of the first chip at the corresponding position and the blocking member; the step of forming a plastic encapsulation layer on the side where the first chip is provided on the carrier board includes: : the plastic sealing layer is formed on the side where the first chip is arranged on the carrier, and the plastic sealing layer covers the gap in the space surrounded by the conductive pillar, the second chip and the conductive pillar ; Grinding the plastic packaging layer from the side of the plastic packaging layer away from the carrier plate, so that the surface of the plastic packaging layer, the conductive column and the second chip is flush with the side away from the carrier plate.

Wherein, the first chip includes a first functional surface and a first non-functional surface disposed opposite to each other, and the first functional surface of the first chip faces the carrier board; the carrier board is provided with the The step of forming a plastic encapsulation layer on one side of the first chip includes: forming a plastic encapsulation layer on the side where the first chip is arranged on the carrier board, the plastic encapsulation layer covering the conductive pillars and the surrounding area of the conductive pillars. A gap in the space; wherein, the plastic encapsulation layer is flush with the surface of the conductive column on the side facing away from the carrier board.

Wherein, after the step of removing the carrier plate, the method further includes: forming a first redistribution layer and a second redistribution layer on both sides of the conductive pillar in the length direction, respectively; wherein the first redistribution layer is at least One end of the conductive column is electrically connected to the first chip, and the second redistribution layer is electrically connected to the other end of the conductive column; a first redistribution layer is provided on the side away from the conductive column. A conductive connection body, and a second conductive connection body is disposed on the side of the second redistribution layer away from the conductive column.

Wherein, before the step of forming the plastic encapsulation layer on the side where the first chip is disposed on the carrier plate, the method includes: forming insulating glue at least on the periphery of the plurality of blocking members.

The beneficial effects of the present application are: different from the situation in the prior art, in the present application, a first photoresist layer and a second photoresist layer, one of which is a positive photoresist and the other is a negative photoresist, are arranged on the carrier plate. The adhesive layer is used to form a plurality of blocking members and a plurality of conductive pillars on the carrier board, wherein the plurality of blocking members and a plurality of conductive pillars are equivalent to cofferdam walls, which help to limit the movement of the molding compound in the fan-out device, Therefore, the deformation amount caused by shrinkage of the plastic packaging material is reduced, and the probability of warpage of the first chip is reduced; in addition, the conductive pillar can also realize a three-dimensional vertical interconnection structure, which is beneficial to reduce the height of the fan-out device, and the different heights. The design of the conductive pillars can effectively save material costs.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. in:

FIG. 1 is a schematic flowchart of an embodiment of the fan-out packaging method of the present application;

FIG. 2 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S101;

3 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S102;

4 is a schematic cross-sectional structure diagram of step S102 corresponding to another embodiment pair;

FIG. 5a is a schematic cross-sectional structural diagram of an embodiment corresponding to step S103;

5b is a schematic cross-sectional structure diagram corresponding to another embodiment of step S103;

6 is a schematic cross-sectional structural diagram of step S104 corresponding to an embodiment;

7 is a schematic flowchart corresponding to an embodiment after step S104;

8a is a schematic cross-sectional structural diagram of an embodiment corresponding to step S201;

8b is a schematic cross-sectional structure diagram corresponding to an embodiment after step S201;

FIG. 9 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S202;

10 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S203;

FIG. 11 is a schematic cross-sectional structural diagram of an embodiment corresponding to step S204;

FIG. 12 is a schematic flowchart of another embodiment of the fan-out packaging method of the present application;

13 is a schematic cross-sectional structural diagram of step S301 corresponding to an embodiment;

FIG. 14 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S302;

15 is a schematic flowchart of another embodiment of the fan-out packaging method of the present application;

16 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S401;

FIG. 17 is a schematic cross-sectional structural diagram of step S402 corresponding to an embodiment.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Please refer to FIG. 1. FIG. 1 is a schematic flowchart of an embodiment of the fan-out packaging method of the present application. The method includes:

S101 : forming a first photoresist layer and a second photoresist layer on the first surface of the carrier plate successively.

Please refer to FIG. 2 . FIG. 2 is a schematic cross-sectional structure diagram of step S101 corresponding to an embodiment. The specific implementation process of this step includes: firstly forming a first photoresist layer 20 on the first surface of the carrier board 10 , and then forming a first photoresist layer 20 on the carrier board 10 . A second photoresist layer 30 is formed on the first surface of the plate. Wherein, one of the first photoresist layer 20 and the second photoresist layer 30 is a positive photoresist, and the other is a negative photoresist; and the second photoresist layer 30 covers the first photoresist layer 20 and the side surface of the first photoresist layer 20 away from the carrier 10; that is, the orthographic projection of the first photoresist layer 20 on the carrier 10 is located on the positive side of the second photoresist layer 30 on the carrier 10. Projection inside. Specifically, the positive photoresist is insoluble in the developing solution before exposure, and soluble in the developing solution after exposure; the negative photoresist is soluble in the developing solution before exposure, and insoluble after exposure developer.

S102: Expose and develop the first photoresist layer and the second photoresist layer simultaneously.

When the first photoresist layer 20 is a negative photoresist and the second photoresist layer 30 is a positive photoresist, please refer to FIG. 3 . FIG. 3 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S102 . The specific implementation process of step S102 includes: exposing and developing the first photoresist layer 20 and the second photoresist layer 30 at the same time, so as to form a plurality of first via holes 21 on the first photoresist layer 20, and A plurality of second via holes 31 are formed on the second photoresist layer 30 on the periphery of the side surface of the first photoresist layer 20 . The height of the second via hole 31 is greater than the height of the first via hole 21 . Specifically, please refer to Figure a in FIG. 3 , a film 40 is provided on the side of the second photoresist layer 30 away from the carrier 10 , and a plurality of openings 41 are provided on the film 40 . Expose the film 40 first, remove the film 40 after the exposure, and simultaneously perform development on the first photoresist layer 20 and the second photoresist layer 30. In response to the first photoresist layer in this embodiment The photoresist layer 20 is a negative photoresist, the second photoresist layer 30 is a positive photoresist, the second photoresist layer 30 at the position corresponding to the opening 41 is removed after development, and the position corresponding to the opening 41 is removed. The first photoresist layer 20 at the position cannot be removed after developing. Wherein, the second photoresist layer 30 located on the outer periphery of the side surface of the first photoresist layer 20 and at the position corresponding to the opening 41 is removed after exposure and development to form a plurality of second via holes 31 . For the orthographic projection openings 41 located in the first photoresist layer 20 on the first photoresist layer 20, the second photoresist layer 30 at the corresponding positions of these openings 41 is removed through exposure and development treatment, and in addition these openings are removed. The first photoresist layer 20 corresponding to the area surrounded by 41 is not exposed to light because it is blocked by the film 40, and the first photoresist layer 20 corresponding to the area surrounded by the opening 41 is a negative photoresist layer. It is also removed to form the first vias 21. Based on the fact that the second photoresist layer 30 at the corresponding positions of these openings 41 is removed after the development process, and the first photoresist layer 20 corresponding to the area surrounded by the openings 41 is After the development process is removed, there is no photoresist layer connected to the second photoresist layer 30 around the area corresponding to the area surrounded by the opening 41 , and this part of the second photoresist layer 30 is also removed. After a part of the first photoresist layer 20 and a part of the second photoresist layer 30 are removed, as shown in FIG. 3 b .

When the first photoresist layer 20 is a positive photoresist and the second photoresist layer 30 is a negative photoresist, please refer to FIG. 4 , which is a cross-sectional structure of step S102 corresponding to another embodiment pair Schematic diagram, in this embodiment, the specific implementation process of step S102 includes: as shown in Figure a in FIG. A plurality of openings 41 . First, the film 40 is exposed to light. After the exposure, the film 40 is removed, and the first photoresist layer 20 and the second photoresist layer 30 are developed simultaneously. For the opening 41 located at the outer periphery of the side of the first photoresist layer 20, wherein the second photoresist layer 30 surrounding the middle part of the opening 41 is not exposed to light exposure, based on the fact that the second photoresist layer 30 is a negative photoresist, The portion of the second photoresist layer 30 is removed to form the second via hole 31 . For the orthographic projection openings 41 in the first photoresist layer 20 on the first photoresist layer 20, the first photoresist layer 20 at the corresponding positions of the openings 41 is exposed and removed under development to remove The first via holes 21 are formed, and the second photoresist layer 30 outside the corresponding positions of these openings 41 and not subjected to exposure treatment is removed after the development treatment. Therefore, the orthographic projection on the first photoresist layer 20 is located in the The photoresist layer around the second photoresist layer 30 at the position corresponding to the opening 41 in the photoresist layer 20 is no longer connected to the photoresist layer, and the part of the second photoresist layer 30 is also removed. After a part of the first photoresist layer 20 and a part of the second photoresist layer 30 are removed, as shown in FIG. 4 b.

S103 : forming a blocking member in the first via hole, and forming a conductive column in the second via hole.

When the first photoresist layer 20 is a negative photoresist and the second photoresist layer 30 is a positive photoresist, please refer to FIG. 5a, which is a schematic cross-sectional structure diagram corresponding to an embodiment of step S103, Specifically, the specific implementation process of the above-mentioned step S103 includes: simultaneously filling the first via hole 21 and the second via hole 31 with a conductive material to form the blocking member 22 and the conductive pillar 32 . One end of the blocking member 22 facing away from the carrier 10 is flush with the surface of the first photoresist layer 20 , and one end of the conductive pillar 32 facing away from the carrier 10 is flush with the surface of the second photoresist layer 30 . Wherein, the blocking member 22 has electrical conductivity. The conductive material may be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. The conductive pillars 32 help to realize a three-dimensional vertical interconnection structure of the fan-out device, and the blocking member 22 helps to improve the stability of the fan-out device.

When the first photoresist layer 20 is a positive photoresist and the second photoresist layer 30 is a negative photoresist layer, please refer to FIG. 5b , which is a cross-sectional structure of step S103 corresponding to another embodiment Schematically, specifically, in this embodiment, step S103 includes: simultaneously filling the first via hole 21 and the second via hole 31 with a conductive material to form the blocking member 22 and the conductive pillar 32 . One end of the blocking member 22 facing away from the carrier 10 is flush with the surface of the first photoresist layer 20 , and one end of the conductive pillar 32 facing away from the carrier 10 is flush with the surface of the second photoresist layer 30 .

S104: Remove the first photoresist layer and the second photoresist layer.

Please refer to FIG. 6 . FIG. 6 is a schematic cross-sectional structure diagram of step S104 corresponding to an embodiment. Specifically, the above-mentioned step S104 includes: removing the first photoresist layer 20 and the second photoresist layer 30 to expose the blocking member 22 and conductive pillars 32 to facilitate the execution of step S201.

Further, please refer to FIG. 7. FIG. 7 is a schematic flowchart corresponding to an embodiment after step S104, and the embodiment includes:

S201: Disposing a first chip in an area surrounded by a plurality of blocking members.

Please refer to FIG. 8a. FIG. 8a is a schematic cross-sectional structural diagram of step S201 corresponding to an embodiment. Specifically, the implementation process of step S201 includes: in response to the first chip 100 including the first functional surface 101 and the first non-contact surface disposed opposite to each other For the functional surface 102 , the first non-functional surface 102 of the first chip 100 faces the carrier board 10 .

Please refer to FIG. 8b. FIG. 8b is a schematic cross-sectional structure diagram corresponding to an embodiment after step S201. Specifically, after step S201 is performed, it further includes forming insulating glue 25 at least on the periphery of the plurality of blocking members 22, wherein a glue-dropping glue can be used. The insulating glue 25 is arranged in such a way that the surface of the insulating glue 25 is arc-shaped because the surface of the glue has tension. Optionally, insulating glue 25 may also be formed on the periphery of the plurality of blocking members 22 by methods such as dispensing glue, and the insulating glue 25 may be cylindrical, tapered, or the like, which is not limited herein. By disposing the insulating glue 25 on the periphery of the blocking member 22 , the blocking member 22 can be fixed to a certain extent.

S202: Disposing at least one second chip on the side of the first functional surface of the first chip away from the carrier, and forming underfill at least between the second functional surface of the second chip and the carrier.

Please refer to FIG. 9. FIG. 9 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S202. FIG. 9 is only schematic. In FIG. 9, only two second chips 200 are drawn. The second chip 200 is numbered 1, 2, 3, and so on. The specific implementation process of step S202 includes: disposing at least one second chip 200 on the side of the first functional surface 101 of the first chip 100 away from the carrier board 10 . The second chip 200 includes a second functional surface 201 and a second non-functional surface 202 disposed opposite to each other, the second functional surface 201 of the second chip 200 faces the first functional surface 101 of the first chip 100 , and the second chip 200 At least part of the blocking member 22 spanning at least part of the first chip 100 and at least part of the first chip 100 adjacent to the first chip 100 , and the pads on the second functional surface 201 of the second chip 200 correspond to the first chip 100 at the corresponding position. The pad of a functional surface 101 is electrically connected to the blocking member 22 , that is, part of the blocking member 22 can be electrically connected to the first chip 100 through the second chip 200 . Specifically, conductive bumps may be provided on the pads of the first functional surface 101 of the first chip 100 , and conductive bumps may be provided on at least part of the blocking member 22 that is at least partially adjacent to the first chip 100 , so as to facilitate the first Connections between the two chips 200 and the first chip, and between the second chip 200 and part of the blocking member 22 . By arranging at least one second chip 200 on the side of the first functional surface 101 of the first chip 100, multiple chips can be packaged and the overall height of the fan-out device can be reduced.

Further, please continue to refer to FIG. 9 , step S202 further includes: forming an underfill 28 at least between the second functional surface 201 of the second chip 200 and the carrier board 10 , and the blocking member 22 is located in the underfill 28 , so as to The first chip 100 , the second chip 200 and the blocking member 22 are fixed and protected to a certain extent. Specifically, in this application, the vertical section of the underfill 28 is a trapezoid, which can improve the stability of the fan-out device; in other applications, the vertical section of the underfill 28 may also be a rectangle or the like. Optionally, the side of the underfill 28 facing away from the carrier board 10 may be flush with the second functional surface 201 of the second chip 200 , or may be higher than the second functional surface 201 of the second chip 200 , which is not limited in this application . In addition, in other embodiments, the underfill 28 may not be provided, that is, step S203 is directly performed after the second chip 200 is provided.

S203 : forming a plastic encapsulation layer on the side where the first chip is disposed on the carrier board.

Please refer to FIG. 10 . FIG. 10 is a schematic cross-sectional structure diagram of step S203 corresponding to an embodiment. The specific implementation process of step S203 includes: forming a plastic encapsulation layer 60 on the side where the first chip 100 is disposed on the carrier board 10 , so that the first chip 100 , the blocking member 22 and the conductive pillar 32 form an integral structure, and the plastic encapsulation layer 60 covers the gap in the space surrounded by the conductive pillar 32 , the second chip 200 and the conductive pillar 32 . Further, the plastic packaging layer 60 is ground from the side facing away from the carrier 10 , so that the surface of the plastic packaging layer 60 , the conductive pillars 32 and the second chip 200 on the side facing away from the carrier 10 is flush. Grinding the side of the plastic encapsulation layer 60 away from the carrier board 10 helps to reduce the overall thickness of the packaged fan-out device and improve the heat dissipation effect.

S204: Remove the carrier plate, and form a first redistribution layer and a second redistribution layer on both sides in the length direction of the conductive column, respectively.

Please refer to FIG. 11 . FIG. 11 is a schematic cross-sectional structure diagram of step S204 corresponding to an embodiment. The specific implementation process of step S204 includes: removing the carrier board 10 , and forming a first rebar on both sides of the conductive column 32 in the length direction respectively. The wiring layer 70 and the second rewiring layer 80 . Wherein, in response to the partial blocking member 22 being electrically connected to the first chip 100 through the second chip 200 , and the first redistribution layer 70 being electrically connected to the blocking member 22 , the first redistribution layer 70 is at least connected to one end of the conductive pillar 32 . It is electrically connected to the first chip 100 ; the second redistribution layer 80 is electrically connected to the other end of the conductive pillar 32 .

Further, please continue to refer to FIG. 11 , a first electrical connection body 75 is provided on the side of the first redistribution layer 70 away from the conductive pillar 32 , and a second electrical connection body is provided on the side of the second redistribution layer 80 away from the conductive pillar 32 85 to facilitate subsequent connection with the substrate or other integrated chips. Optionally, a plurality of solder balls 90 may be provided between the first redistribution layer 70 and the first electrical connector 75 and between the second redistribution layer 80 and the second electrical connector 85 to facilitate the first The connection between the redistribution layer 70 and the first electrical connection body 75 , and the connection between the second redistribution layer 80 and the second electrical connection body 85 .

Of course, in another embodiment, before step S203, the first functional surface 101 of the first chip 100 faces the carrier board 10. In this case, please refer to FIG. 12. FIG. 12 is another embodiment corresponding to the fan-out packaging method of the present application. The schematic flow chart of this embodiment, the specific implementation process of this embodiment includes:

S301: Disposing a first chip in an area surrounded by a plurality of blocking members, and forming a plastic encapsulation layer on the side of the carrier plate on which the first chip is disposed.

Specifically, please refer to FIG. 13 . FIG. 13 is a schematic cross-sectional structure diagram of step S301 corresponding to an embodiment. The specific implementation process of step S301 includes: in response to the first chip 100 including the first functional surface 101 and the first functional surface 101 disposed opposite to each other. For the non-functional surface 102 , the first functional surface 101 of the first chip 100 faces the carrier board 10 , and a plastic sealing layer 60 is formed on the side where the first chip 100 is disposed on the carrier board 10 . The plastic sealing layer 60 covers the conductive pillars 32 and the conductive pillars. The gap in the space surrounded by 32; wherein, the surface of the plastic encapsulation layer 60 and the conductive column 32 facing away from the carrier board 10 is flush. By providing the plastic encapsulation layer 60 , the first chip 100 , the conductive pillars 32 and the blocking member 22 can be fixed and protected to a certain extent, and they can be packaged into a complete structure.

S302: Remove the carrier board.

Please refer to FIG. 14 . FIG. 14 is a schematic cross-sectional structure diagram of step S302 corresponding to an embodiment. The specific implementation process of step S302 includes: removing the carrier board 10 , and forming a first rebar on both sides of the conductive column 32 in the length direction respectively. The wiring layer 70 and the second rewiring layer 80 . A first electrical connection body 75 is provided on the side of the first redistribution layer 70 away from the conductive pillar 32 , and a second electrical connection body 85 is provided on the side of the second redistribution layer 80 away from the conductive pillar 32 . Optionally, a plurality of solder balls 90 may be provided between the first redistribution layer 70 and the first electrical connection body 75 and between the second redistribution layer 80 and the second electrical connection body 85 .

In another embodiment, the first chip 100 can also be set first, and then the first photoresist layer 20 and the second photoresist layer 30 can be formed successively. Please refer to FIG. 15. FIG. 15 is a schematic flowchart of the fan-out packaging method proposed in the present application corresponding to another embodiment. The specific implementation process of this embodiment includes:

S401 : firstly disposing a first chip on the carrier board, and then forming a first photoresist layer and a second photoresist layer successively.

Please refer to FIG. 16 . FIG. 16 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S401 . Specifically, the first chip 100 is firstly disposed on the carrier board 10 , and the first chip 100 includes a first functional surface 101 and a first non-functional surface 102 that are disposed opposite to each other. The first non-functional surface 102 of the first chip 100 faces the carrier board 10 . Then, a first photoresist layer 20 and a second photoresist layer 30 are successively formed on the first surface of the carrier 10, and one of the first photoresist layer 20 and the second photoresist layer 30 is a positive photoresist , and the other is a negative photoresist. Wherein, when the first photoresist layer 20 and the second photoresist layer 30 are formed on the first surface of the carrier board 10 , the side of the second photoresist layer 30 facing away from the carrier board 10 is opposite to the first chip 100 and facing away from the carrier board 10 . One side is away from the carrier plate 10 .

S402 : forming a plurality of conductive pillars and a plurality of blocking members on the side where the first chip is disposed on the carrier board.

Please refer to FIG. 17 . FIG. 17 is a schematic cross-sectional structure diagram of step S402 corresponding to an embodiment. The specific implementation process of step S402 includes: using the method of step S102 in FIG. The second photoresist layer 30 is exposed and developed at the same time, and the method of step S103 in FIG. 1 will be used to form a plurality of conductive pillars 32 and a plurality of blocking members 22 on the side of the carrier 10 where the first chip 100 is disposed, and remove them. The first photoresist layer 20 and the second photoresist layer 30 .

Further, after removing the first photoresist layer 20 and the second photoresist layer 30 , the method further includes: forming a plastic encapsulation layer on the side where the first chip 100 is disposed on the carrier plate 10 , so that the first chip 100 and the blocking member are formed. 22 and conductive pillars 32 form a unitary structure. For the specific process, reference may be made to the steps in FIG. 7 , which will not be repeated here.

In this embodiment, the above step S402 may also include: when the first photoresist layer 20 and the second photoresist layer 30 are exposed and developed at the same time, the photoresist covering the first functional surface 101 of the first chip 100 A plurality of third via holes are formed on the layer, and one third via hole corresponds to a pad on the first functional surface 101 of a first chip 100 . In addition, while the conductive pillars 32 are formed in the second via holes, conductive bumps are formed in the third via holes. Wherein, the side of the first chip 100 facing away from the carrier 10 is flush with the side of the first photoresist layer 20 facing away from the carrier 10, then only the second photoresist layer 30 can be exposed and developed to form the third via hole , which reduces the difficulty of forming the third via hole. Forming the conductive bumps at the same time as the conductive pillars 32 can avoid the subsequent separate provision of conductive bumps on the first functional surface 101 of the first chip 100 ; wherein the conductive bumps are provided on the first functional surface 101 of the first chip 100 It is helpful to subsequently arrange a chip or a rewiring layer on the side of the first functional surface 101 of the first chip 100 .

In this embodiment, in step S401 , the first functional surface 101 of the first chip 100 may also face the carrier board 10 , and then the first photoresist layer 20 and the second photoresist layer 30 are formed successively to form a plurality of barriers Pieces 22 and conductive pillars 32 .

In the present application, a first photoresist layer 20 and a second photoresist layer 30 , one of which is a positive photoresist and the other is a negative photoresist, is disposed on the carrier 10 to form a plurality of barriers on the carrier. The member 22 and the plurality of conductive pillars 32, wherein the plurality of blocking members 22 and the plurality of conductive pillars 32 are equivalent to cofferdam walls, which help to limit the movement of the molding compound in the fan-out device, thereby reducing the shrinkage of the molding compound. The deformation of the first chip 100 reduces the probability of warping of the first chip 100; in addition, the conductive pillars 32 can also realize a three-dimensional vertical interconnection structure, which is beneficial to reduce the height of the fan-out device. Material cost can be effectively saved.

The above description is only an embodiment of the present application, and is not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies Fields are similarly included within the scope of patent protection of this application.

Claims (10)

1. A fan-out packaging method, comprising:

sequentially forming a first photoresist layer and a second photoresist layer on the first surface of the carrier plate; one of the first photoresist layer and the second photoresist layer is a positive photoresist, and the other one of the first photoresist layer and the second photoresist layer is a negative photoresist; the second photoresist layer covers the side surface of the first photoresist layer and the surface of one side of the first photoresist layer, which is far away from the carrier plate;

exposing and developing the first photoresist layer and the second photoresist layer simultaneously, wherein a plurality of first through holes are formed in the first photoresist layer, and a plurality of second through holes are formed in the second photoresist layer on the periphery of the side face of the first photoresist layer; wherein the height of the second via is greater than the height of the first via;

forming a barrier within the first via and a conductive pillar within the second via;

and removing the first photoresist layer and the second photoresist layer.

2. The fan-out packaging method of claim 1,

the barrier has conductive properties; the steps of forming a barrier within the first via and forming a conductive pillar within the second via include: filling a conductive material in the first via and the second via simultaneously to form the barrier and the conductive pillar.

3. The fan-out packaging method of claim 2, wherein the step of removing the first and second photoresist layers is followed by:

arranging a first chip in an area surrounded by the barriers;

forming a plastic package layer on one side of the carrier plate, where the first chip is arranged, so that the first chip, the blocking member and the conductive column form an integral structure;

and removing the carrier plate.

4. The fan-out packaging method of claim 2,

before the step of sequentially forming the first photoresist layer and the second photoresist layer on the first surface of the carrier plate, the method comprises the following steps of: arranging a first chip on the first surface of the carrier plate; when a first photoresist layer and a second photoresist layer are formed on the first surface of the carrier plate, one side of the second photoresist layer departing from the carrier plate is far away from the carrier plate relative to one side of the first chip departing from the carrier plate;

after the step of removing the first photoresist layer and the second photoresist layer, the method includes:

forming a plastic package layer on one side of the carrier plate, where the first chip is arranged, so that the first chip, the blocking member and the conductive column form an integral structure;

and removing the carrier plate.

5. The fan-out packaging method of claim 4,

the first chip comprises a first functional surface and a first non-functional surface which are arranged oppositely, and the first non-functional surface of the first chip faces the carrier plate;

when the first photoresist layer and the second photoresist are exposed and developed simultaneously, a plurality of third through holes are formed on the photoresist layer covering the first functional surface of the first chip, and one third through hole corresponds to a bonding pad on the first functional surface of the first chip;

and forming a conductive bump in the third via hole while forming the conductive pillar in the second via hole.

6. The fan-out packaging method of claim 5,

the step of forming a plastic package layer on one side of the first chip arranged on the carrier plate comprises the following steps: forming a plastic package layer on one side of the carrier plate, where the first chip is arranged, wherein the plastic package layer covers the conductive posts and gaps in a space surrounded by the conductive posts; the plastic packaging layer is flush with the surface of one side, away from the carrier plate, of the conductive column.

7. The fan-out packaging method of claim 3 or 4,

the first chip comprises a first functional surface and a first non-functional surface which are arranged oppositely, and the first non-functional surface of the first chip faces the carrier plate;

before the step of forming the plastic package layer on the side of the first chip on the carrier plate, the method further comprises the following steps: arranging at least one second chip on one side, away from the carrier plate, of the first functional surface of the first chip, and forming underfill between at least the second functional surface of the second chip and the carrier plate, wherein the blocking piece is positioned in the underfill; wherein the second functional surface of the second chip faces the first functional surface of the first chip, the second chip spans at least a portion of the first chip and at least a portion of the dam adjacent to at least a portion of the first chip, and a pad on the second functional surface of the second chip is electrically connected to a pad on the first functional surface of the first chip and the dam at a corresponding location;

the step of forming a plastic package layer on one side of the first chip arranged on the carrier plate comprises the following steps: forming the plastic package layer on one side of the carrier plate, where the first chip is arranged, and covering the conductive column, the second chip and a gap in a space surrounded by the conductive column with the plastic package layer; grinding the plastic packaging layer from one side of the plastic packaging layer, which is far away from the carrier plate, so that the surface of one side, which is far away from the carrier plate, of the plastic packaging layer, the conductive columns and the second chip is flush.

8. The fan-out packaging method of claim 3 or 4,

the first chip comprises a first functional surface and a first non-functional surface which are arranged oppositely, and the first functional surface of the first chip faces the carrier plate; the step of forming a plastic package layer on one side of the first chip arranged on the carrier plate comprises the following steps: forming a plastic package layer on one side of the carrier plate, where the first chip is arranged, wherein the plastic package layer covers the conductive posts and gaps in a space surrounded by the conductive posts; the plastic packaging layer is flush with the surface of one side, away from the carrier plate, of the conductive column.

9. The fan-out packaging method of claim 3 or 4, wherein the step of removing the carrier plate is followed by further comprising:

forming a first redistribution layer and a second redistribution layer on two sides of the conductive pillar in the length direction respectively; wherein the first redistribution layer is electrically connected to at least one end of the conductive pillar and the first chip, and the second redistribution layer is electrically connected to the other end of the conductive pillar;

and arranging a first electric connector on one side of the first redistribution layer, which is far away from the conductive column, and arranging a second electric connector on one side of the second redistribution layer, which is far away from the conductive column.

10. The fan-out packaging method according to claim 3 or 4, wherein before the step of forming the molding layer on the side of the carrier where the first chip is arranged, the method comprises:

and forming insulating glue at least on the periphery of the barriers.

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