CN114530386A - Fan-out type packaging method - Google Patents

Abstract

The present application discloses a fan-out packaging method, which includes: providing a carrier board, and arranging a first chip on the carrier board; forming a plurality of blocking members and a plurality of conductive parts on the periphery of the first chip successively pillars; wherein, the plurality of conductive pillars are located on the periphery of the plurality of blocking members, and the height of the conductive pillars is greater than the height of the blocking members; formed on the side where the first chip is disposed on the carrier plate A plastic encapsulation layer is formed so that the first chip, the blocking member and the conductive column form an integral structure; and the carrier plate is removed. Through the above method, the present application can reduce the amount of deformation of the plastic packaging material due to shrinkage, and ensure the stability of the chip; and the design of the blocking members and conductive pillars of different heights can also effectively save packaging materials, thereby reducing packaging costs.

Description

A fan-out packaging method

technical field

The present application relates to the technical field of chip packaging, and in particular, to a fan-out packaging method.

Background technique

In the traditional fan-out packaging method, after the chip is plastic-sealed, the plastic sealing compound in the packaging structure is deformed due to shrinkage, which easily causes the chip to shift in the packaging structure and reduces the service life of the chip.

SUMMARY OF THE INVENTION

The main technical problem to be solved by the present application is to provide a fan-out packaging method, which can reduce the amount of deformation of the plastic packaging material due to shrinkage and ensure the stability of the chip.

In order to solve the above technical problems, a technical solution adopted in the present application is to provide a fan-out packaging method, which includes: providing a carrier board, and arranging a first chip on the carrier board; forming a plurality of blocking members and a plurality of conductive pillars successively; wherein, the plurality of conductive pillars are located on the periphery of the plurality of blocking members, and the height of the conductive pillars is greater than that of the blocking members; A plastic encapsulation layer is formed on the side where the first chip is disposed, so that the first chip, the blocking member and the conductive column form an integral structure; and the carrier plate is removed.

Wherein, the blocking member has electrical conductivity.

Wherein, the step of successively forming a plurality of blocking members and a plurality of conductive pillars on the periphery of the first chip includes: forming a first photoresist layer on the side of the carrier plate where the first chip is disposed; exposing and developing the first photoresist to form a plurality of first via holes on the first photoresist layer, and the plurality of first via holes are located on the periphery of the first chip; forming the blocking member in the first via hole; forming a second photoresist layer on the side of the first photoresist layer away from the carrier; The second photoresist layer is exposed and developed to form a plurality of second via holes on the first photoresist layer and the second photoresist layer, and the plurality of second via holes are located in the the periphery of a plurality of first vias; the conductive pillars are formed in the second vias.

Wherein, the step of forming the blocking member in the first via hole includes: forming the blocking member in the first via hole through a metal sputtering process; the blocking member is formed in the first photoresist Before the step of forming the second photoresist layer on the side of the layer away from the carrier plate, the step includes: removing the sputtered metal on the surface of the first photoresist layer on the side away from the carrier plate.

Wherein, before the step of forming a plastic encapsulation layer on the side where the first chip is disposed on the carrier, the steps include: removing all the first photoresist layers and all the second photoresist layers; at least in An insulating glue is formed on the periphery of the plurality of blocking members.

Wherein, before the step of forming a plastic encapsulation layer on the side where the first chip is disposed on the carrier plate, the step includes: removing all the second photoresist layer and the first photoresist around the conductive pillars Floor.

Wherein, the first chip includes a first functional surface and a first non-functional surface arranged opposite to each other, and the first non-functional surface of the first chip faces the carrier board; Before the step of forming the plastic encapsulation layer on the side of the first chip, the method further includes: arranging at least one second chip on the side of the first functional surface of the first chip away from the carrier board, and at least one second chip on the side of the second chip. An underfill is formed between the second functional surface and the carrier, and the blocking member is located in the underfill; wherein the second functional surface of the second chip faces the first functional surface of the first chip , the second chip spans at least part of the first chip and at least part of the blocking member adjacent to at least part of the first chip, and the second chip on the second functional surface of the second chip The pads are electrically connected to the first pads on the first functional surface of the first chip at corresponding positions and the blocking member.

Wherein, the step of forming a plastic encapsulation layer on the side where the first chip is arranged on the carrier includes: forming the plastic encapsulation layer on the side where the first chip is arranged on the carrier, and the plastic encapsulation layer covering the conductive column, the second chip and the gap in the space surrounded by the conductive column; grinding the plastic sealing layer from the side of the plastic sealing layer away from the carrier, so that the The surface of the plastic encapsulation layer, the conductive post and the second chip on the side facing away from the carrier board is flush.

Wherein, the first chip includes a first functional surface and a first non-functional surface disposed opposite to each other, and the first functional surface of the first chip faces the carrier disk; the carrier disk is provided with the The step of forming a plastic encapsulation layer on one side of the first chip includes: forming a plastic encapsulation layer on the side where the first chip is arranged on the carrier board, the plastic encapsulation layer covering the conductive pillars and the surrounding area of the conductive pillars. A gap in the space; wherein, the plastic encapsulation layer is flush with the surface of the conductive column on the side facing away from the carrier board.

Wherein, after removing the carrier plate, the method further includes: forming a first redistribution layer and a second redistribution layer respectively on both sides of the conductive pillar in the length direction; wherein the first redistribution layer is at least the same as the The conductive pillar is electrically connected to the first chip, and the second redistribution layer is electrically connected to the conductive pillar; a first electrical connector is provided on the side of the first redistribution layer away from the conductive pillar, and a A second electrical connection body is provided on the side of the second redistribution layer away from the conductive column.

The beneficial effects of the present application are: different from the situation in the prior art, the present application forms a plurality of blocking members and a plurality of conductive columns on the periphery of the chip; wherein, the plurality of blocking members and the plurality of conductive columns are equivalent to a cofferdam retaining wall, which The movement of the plastic sealing compound in the plastic sealing layer can be limited, so as to reduce the deformation amount of the plastic sealing material due to shrinkage and the probability of warping of the first chip; in addition, the conductive pillars can also realize a three-dimensional vertical interconnection structure, which is beneficial to reduce the fan-out packaging device. In addition, the different heights of the blocking member and the conductive column design can also effectively save the material cost.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. in:

FIG. 1 is a schematic flowchart of an embodiment of the fan-out packaging method of the present application;

FIG. 2 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S101;

FIG. 3 is a schematic flowchart of step S102 corresponding to an embodiment;

4a is a schematic cross-sectional structural diagram of step S201 corresponding to an embodiment;

4b is a schematic cross-sectional structure diagram corresponding to an embodiment of step S202;

4c is a schematic cross-sectional structure diagram corresponding to another embodiment of step S202;

FIG. 5 is a schematic flowchart of step S103 corresponding to an embodiment;

6a is a schematic cross-sectional structural diagram of an embodiment before step S301 is implemented;

6b is a schematic cross-sectional structure diagram corresponding to an embodiment of step S301;

FIG. 7a is a schematic cross-sectional structural diagram of an embodiment corresponding to step S302;

7b is a schematic cross-sectional structure diagram corresponding to an embodiment after step S302;

FIG. 8 is a schematic cross-sectional structure diagram corresponding to an embodiment of step S104;

FIG. 9 is a schematic cross-sectional structural diagram of another embodiment of the fan-out packaging method of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Please refer to FIG. 1. FIG. 1 is a schematic flowchart of an embodiment of the fan-out packaging method of the present application. The method includes:

S101: Disposing a first chip on the carrier board.

Specifically, please refer to FIG. 2 . FIG. 2 is a schematic cross-sectional structure diagram of the above step S101 corresponding to an embodiment. FIG. 2 is only schematic. For ease of understanding, only one first chip 100 is shown in FIG. 2 . In application, a plurality of first chips 100 may be arranged on the carrier board 50 at intervals, so as to adopt the fan-out packaging method proposed in the present application for the plurality of first chips 100 to obtain a plurality of packaged chip structures, and cut two Adjacent packaged chip structures intermediate portions to obtain a single packaged chip structure.

In an application manner, step S101 specifically includes: disposing a first chip 100 on the carrier board 50 , the first chip 100 including a first functional surface 1001 and a first non-functional surface 1002 disposed opposite to each other, and the first chip 100 The first non-functional surface 1002 of the 1002 faces the carrier board 50 . Wherein, a plurality of first pads 10 (only two are shown in the figure) are disposed on the first functional surface 1001 of the first chip 100 to receive and/or transmit signals.

Optionally, the first non-functional surface 1002 of the first chip 100 can be fixed to the carrier board 50 by bonding glue; it is also possible to attach at least one first chip 100 to the carrier board 50 by attaching double-sided tape to the carrier board 50 . On the double-sided tape, the first non-functional surface 1002 of the first chip 100 faces the carrier board 50 at this time. The material of the carrier plate 50 may specifically be one of silicon, glass, metal, and organic compound. Disposing the first chip 100 on the carrier board 50 can play a certain role in limiting the position of the first chip 100 .

S102 : successively forming a plurality of blocking members and a plurality of conductive pillars on the periphery of the first chip.

Please refer to FIG. 3. FIG. 3 is a schematic flowchart of the above-mentioned step S102 corresponding to an embodiment, and the step includes:

S201 : forming a first photoresist layer on the side where the first chip is disposed on the carrier, forming a plurality of first via holes on the photoresist layer, and forming a blocking member in the first via holes.

Please refer to FIG. 4a. FIG. 4a is a schematic cross-sectional structure diagram corresponding to an embodiment of the above step S201. In an application mode, a first photoresist layer 101 is formed on the side where the first chip 100 is disposed on the carrier plate 50 ; A plurality of first via holes 1010 are formed thereon, and the plurality of first via holes 1010 are located on the periphery of the first chip 100 . The blocking member 20 is formed in the first via hole 1010 . The side of the first photoresist layer 101 facing away from the carrier 50 is flush with the first functional surface 1001 of the first chip 100 , that is, the end of the blocking member 20 facing away from the carrier 50 is flush with the first functional surface 1001 of the first chip 100 level, so as to facilitate the subsequent execution of step S301. Specifically, part of the first photoresist layer 101 at the peripheral position of the first chip 100 is exposed and developed, and the exposed and developed first photoresist layer 101 is removed to form a plurality of first via holes 1010. The blocking member 20 is formed in a via hole 1010 by a metal sputtering process. Specifically, a film with a plurality of openings can be provided on the side of the first photoresist layer 101 away from the carrier 50, and the side of the film away from the carrier 50 can be exposed and developed to remove the corresponding openings on the film. The first photoresist layer 101 at the position, thereby forming a plurality of first via holes 1010 , and then forming the blocking member 20 in the first via holes 1010 . The blocking member 20 has electrical conductivity to facilitate the subsequent execution of step S301, and its material may be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper . By using the method of forming the first via hole 1010 on the first photoresist layer 101 to form the blocking member 20, the difficulty of forming the blocking member 20 in the packaging process can be effectively reduced. In this application mode, the first photoresist layer 101 can also cover the first functional surface 1001 of the first chip 100 , and the first photoresist layer at the position corresponding to the first functional surface 1001 of the first chip 100 exposure and development are performed to form third via holes, conductive metal is filled in the third via holes to form conductive bumps, and the conductive bumps are arranged to help the first chip 100 be disposed on the first functional surface 1001 side of the first chip 100 . Chip 100 is a chip to which the chip 100 is electrically connected.

S202 : forming a second photoresist layer on the side of the first photoresist layer away from the carrier, forming a plurality of second via holes on the first photoresist layer and the second photoresist layer, and forming a plurality of second via holes in the second via holes Conductive pillars are formed inside.

Specifically, before forming the second photoresist layer 102 on the side of the first photoresist layer 101 away from the carrier 50, the method further includes removing the sputtered metal on the surface of the first photoresist layer 101 away from the carrier 50, so as to avoid The sputtered metal on the surface affects the exposure and development of the first photoresist layer 101 and the second photoresist layer 102, so that the second via hole 1020 cannot be formed. Wherein, the method of exposing and developing the surface of the first photoresist layer 101 away from the carrier plate 50 can be used to reduce the thickness of the first photoresist layer as a whole to remove the sputtered metal on the surface of the first photoresist layer 101 .

Please refer to FIG. 4b. FIG. 4b is a schematic cross-sectional structure diagram corresponding to an embodiment of the above step S202. In an application mode, the second photoresist layer 102 is formed on the side of the first photoresist layer 101 away from the carrier plate 50, and the first photoresist layer 101 and the second photoresist layer 102 are exposed and developed to A plurality of second via holes 1020 are formed on the first photoresist layer 101 and the second photoresist layer 102, and the plurality of second via holes 1020 are located at the periphery of the plurality of first via holes 1010; Conductive pillars 30 are formed in 1020 . Further, part of the first photoresist layer 101 and the second photoresist layer 102 at the peripheral positions of the first via hole 1010 are exposed and developed, and part of the first photoresist layer 101 and the second photoresist layer 101 and the second photoresist layer after exposure and development are exposed and developed. The resist layer 102 is removed to form a plurality of second via holes 1020, the plurality of second via holes 1020 are located on the periphery of the plurality of first via holes 1010, and the conductive pillars 30 are formed in the second via holes 1020 by sputtering metal process . The material of the conductive column 30 may be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. By using the method of forming the second via holes 1020 on the first photoresist layer 101 and the second photoresist layer 102 to form the conductive pillars 30 , the difficulty of forming the conductive pillars 30 in the packaging process can be effectively reduced.

Optionally, please refer to FIG. 4c. FIG. 4c is a schematic cross-sectional structural diagram of the above-mentioned step S202 corresponding to another implementation process. The implementation process includes: after the step S201, all remaining first photoresist layers 101 are exposed and developed to remove All remaining first photoresist layer 101 . Further, a second photoresist layer 102 is re-formed on the side where the first chip 100 is disposed on the carrier plate 50, and the height of the second photoresist layer 102 is higher than that of the blocking member 20; for the second photoresist layer 102, exposure and development are performed to form a plurality of second via holes 1020 on the second photoresist layer 102, and the plurality of second via holes 1020 are located on the periphery of the blocking member 20, and the metal sputtering process is performed in the second via holes 1020 to form conductive pillars 30 . The interconnection in the vertical direction after the chip is packaged can be realized through the conductive pillars 30 .

S103 : forming a plastic encapsulation layer on the side where the first chip is disposed on the carrier board.

When the non-functional surface of the first chip faces the carrier board, please refer to FIG. 5 . FIG. 5 is a schematic flowchart of the above step S103 corresponding to an embodiment, and the method includes:

S301: Disposing at least one second chip on the side of the first functional surface of the first chip away from the carrier, and forming underfill at least between the second functional surface of the second chip and the carrier.

Please refer to FIG. 6a. FIG. 6a is a schematic cross-sectional structural diagram of a previous implementation manner of the above step S301. In an application manner, before the above-mentioned step S301 is performed, the method further includes: removing the first photoresist layer 101 and all the second photoresist layers 102 to expose the blocking member 20 and the conductive pillar 30 , and at least in a plurality of blocking An insulating glue 60 is formed on the periphery of the member 20 to protect and limit the blocking member 20 to a certain extent. The insulating glue 60 may be formed by a method of dispensing glue. Based on the surface tension of the glue, the surface of the insulating glue 60 is arc-shaped, and the height of the insulating glue 60 does not exceed the height of the blocking member 20 . In another application manner, only all the second photoresist layers 102 and the first photoresist layers 101 around the conductive pillars 30 may be removed, that is, part of the first photoresist layers 101 around the blocking member 20 is retained. The method does not require additional insulating glue 60, and the remaining first photoresist layer 101 around the blocking member 20 can protect and limit the blocking member 20 to a certain extent, thereby reducing the packaging cost.

Please refer to FIG. 6b. FIG. 6b is a schematic cross-sectional structure diagram of the above-mentioned step S301 corresponding to an embodiment. FIG. 6b is only schematic. For ease of understanding, only two second chips 200 are shown in FIG. 6b. , one or more second chips 200 may be disposed on the side of the first functional surface 1001 of the first chip 100 . The second chip 200 includes a second functional surface 2001 and a second non-functional surface 2002 disposed opposite to each other, and a plurality of second pads 40 are provided on the second functional surface 2001 of the second chip 200 (only shown in the figure). out two) to receive and/or transmit signals. Specifically, the specific implementation process of the above step S301 includes: disposing at least one second chip 200 on the side of the first functional surface 1001 of the first chip 100 away from the carrier board 50 ; wherein the second functional surface 2001 of the second chip 200 faces The first functional face 1001 of the first chip 100, the second chip 200 spanning at least part of the first chip 100 and at least part of the barrier 20 adjacent to at least part of the first chip 100, and the second function of the second chip 200 The second pads 40 on the surface 2001 are electrically connected to the first pads 10 and the blocking member 20 on the first functional surface 1001 of the first chip 100 at corresponding positions. Based on the electrical connection between part of the second pads 40 of the second chip 200 and part of the first pads 10 of the first chip 100 , the information interaction between the first chip 100 and the second chip 200 can be realized; The blocking member 20 is electrically connected, and the blocking member 20 has electrical conductivity, that is, the blocking member 20 can be electrically connected to the first chip 100 through the second chip 200 , and can be connected to the first chip 100 and the second chip 100 only through the blocking member 20 . Information exchange of the chip 200 . In response to the end of the blocking member 20 facing away from the carrier board 50 being flush with the first functional surface 1001 of the first chip 100 , it can be ensured that the second chip 200 will not be tilted when setting the second chip 200 , thereby ensuring the stability of the second chip 200 .

Further, please continue to refer to FIG. 6b, step S301 further includes: forming an underfill 25 at least between the second functional surface 2001 of the second chip 200 and the carrier board 50, and the blocking member 20 is located in the underfill 25, so as to The first chip 100 , the second chip 200 and the blocking member 20 are fixed and protected to a certain extent. Specifically, in this application, the vertical section of the underfill 25 is a trapezoid, which can improve the stability of the fan-out device; in other applications, the vertical section of the underfill 25 may also be a rectangle or the like. Optionally, the side of the underfill 25 facing away from the carrier board 50 may be flush with the second functional surface 2001 of the second chip 200 , or may be higher than the second functional surface 2001 of the second chip 200 , which is not limited in this application . In addition, in other embodiments, the underfill 25 may not be provided, that is, step S302 is directly performed after the second chip 200 is provided.

S302 : forming a plastic encapsulation layer on the side where the first chip is disposed on the carrier board.

Please refer to FIG. 7a . FIG. 7a is a schematic cross-sectional structure diagram of the above step S302 corresponding to an embodiment. The step includes: forming a plastic sealing layer 130 on the side where the first chip 100 is disposed on the carrier board 50 , and the plastic sealing layer 130 covers the conductive pillars 30 , the gap in the space surrounded by the second chip 200 and the conductive pillar 30 to fix and protect the first chip 100 , the second chip 200 , the blocking member 20 and the conductive pillar 30 . The material of the plastic sealing layer 130 may be epoxy resin or the like, which may be formed by a pressing process.

Further, please refer to FIG. 7b. FIG. 7b is a schematic cross-sectional structure diagram corresponding to an embodiment after step S302. After the plastic sealing layer 130 is formed on the side where the first chip 100 is disposed on the carrier board 50, the plastic sealing layer 130 can be away from the carrier board. The plastic sealing layer 130 is ground on the side 50 , so that the surface of the plastic sealing layer 130 , the conductive pillars 30 and the second chip 200 on the side facing away from the carrier board 50 is flush. In this step, proper grinding of the plastic encapsulation layer 130 can reduce the overall thickness of the packaged chip and improve the heat dissipation effect.

S104: Remove the carrier board.

Please refer to FIG. 8 . FIG. 8 is a schematic cross-sectional structure diagram corresponding to an embodiment of the above step S104 . In an application manner, step S104 specifically includes: removing the carrier board 50, and forming a first redistribution layer 150 and a second redistribution layer 160 on both sides of the conductive column 30 in the length direction respectively; wherein, the first redistribution layer 160 is formed. The layer 150 is located on the side of the first chip 100 away from the second chip 200 , the first redistribution layer 150 is electrically connected to the conductive pillar 30 and the blocking member 20 , and the blocking member 20 is electrically connected to the first chip 100 through the second chip 200 , The first redistribution layer 150 is electrically connected to at least the conductive pillars 30 and the first chip 100 . The second redistribution layer 160 is located on the side of the second chip 200 away from the first chip 100 , and the second redistribution layer 160 is electrically connected to the conductive pillars 30 . Optionally, both the first redistribution layer 150 and the second redistribution layer 160 include a dielectric layer and a patterned metal layer. In addition, the number of layers of the first redistribution layer 150 and the second redistribution layer 160 may be one or more layers, which is not limited in the present application. The electrical connection to the first chip 100 and/or the second chip 200 can be achieved through the first redistribution layer 150 and the second redistribution layer 160 .

Further, a first electrical connector 170 is provided on the side of the first redistribution layer 150 away from the conductive pillar 30 , and a second electrical connector 180 is provided on the side of the second redistribution layer 160 away from the conductive pillar 30 . Optionally, a plurality of solder balls 80 may be formed between the first redistribution layer 150 and the first electrical connector 170 and between the second redistribution layer 160 and the second electrical connector 180 to facilitate the first The connection between the redistribution layer 150 and the first electrical connector 170 , and the connection between the second redistribution layer 160 and the second electrical connector 180 . The first electrical connecting body 170 and the second electrical connecting body 180 can be electrically connected to the substrate or other integrated chips subsequently to realize information exchange.

In the present application, by forming a plurality of blocking members 20 and a plurality of conductive pillars 30 on the periphery of the first chip 100, a three-dimensional vertical interconnection structure is realized, and at the same time, the deformation amount caused by the shrinkage of the plastic sealing compound is also reduced, so as to ensure the stability of the chip. and the design of the blocking member 20 and the conductive post 30 of different heights can also effectively save packaging materials, thereby reducing packaging costs.

Of course, in other embodiments, before step S102 , the first functional surface 1001 of the first chip 100 faces the carrier board 50 ; at this time, please refer to FIG. 9 , which is another embodiment of the fan-out packaging method of the present application. A schematic cross-sectional view of the structure, in response to the fact that the first chip 100 includes the first functional surface 1001 and the first non-functional surface 1002 disposed opposite to each other, in this embodiment, the first functional surface 1001 of the first chip 100 faces the carrier board 50 , A plurality of blocking members 20 and a plurality of conductive pillars 30 are successively formed on the periphery of the first chip 100 through the above step S102 in FIG. 1 . Then, a plastic sealing layer 130 is formed on the side where the first chip 100 is disposed on the carrier board 50 . The plastic sealing layer 130 covers the conductive pillars 30 and the gaps in the space surrounded by the conductive pillars 30 ; wherein, the plastic sealing layer 130 and the conductive pillars 30 are away from the carrier. One side of the board 50 is flush.

Further, the carrier plate 50 is removed, and a first redistribution layer 150 and a second redistribution layer 160 are respectively formed on both sides of the conductive pillar 30 in the length direction. The first redistribution layer 150 is located on the side of the first functional surface 1001 of the first chip 100 , and the second redistribution layer 160 is located on the side of the plastic packaging layer 130 away from the first functional surface 1001 of the first chip 100 . Then, a first electrical connector 170 is provided on the side of the first redistribution layer 150 away from the conductive pillar 30 , and a second electrical connector 180 is provided on the side of the second redistribution layer 160 away from the conductive pillar 30 . Optionally, a plurality of solder balls 80 may be formed between the first redistribution layer 150 and the first electrical connector 170, and between the second redistribution layer 160 and the second electrical connector 180 to facilitate the first redistribution The connection between the layer 150 and the first electrical connector 170 , and the connection between the second redistribution layer 160 and the second electrical connector 180 .

In the above embodiment, the first functional surface 1001 of the first chip 100 faces the carrier board 50, and then the first chip 100 is packaged by the fan-out packaging method proposed in the present application. The deformation amount caused by the shrinkage of the plastic packaging material is reduced, and the stability of the chip is ensured; and the design of the blocking member 20 and the conductive post 30 of different heights can also effectively save packaging materials, thereby reducing packaging costs.

The above description is only an embodiment of the present application, and is not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies Fields are similarly included within the scope of patent protection of this application.

Claims (10)

1. A fan-out packaging method, characterized in that, comprising: providing a carrier board, and disposing the first chip on the carrier board; A plurality of blocking members and a plurality of conductive pillars are successively formed on the periphery of the first chip; wherein, the plurality of conductive pillars are located on the periphery of the plurality of blocking members, and the height of the conductive pillars is greater than that of the blocking members the height of; A plastic encapsulation layer is formed on the side where the first chip is disposed on the carrier, so that the first chip, the blocking member and the conductive column form an integral structure; Remove the carrier plate. 2. The fan-out packaging method according to claim 1, wherein, The blocking member has conductive properties. 3 . The fan-out packaging method according to claim 2 , wherein the step of sequentially forming a plurality of blocking members and a plurality of conductive pillars on the periphery of the first chip comprises: 3 . forming a first photoresist layer on the side where the carrier is provided with the first chip; exposing and developing the first photoresist layer to form a plurality of first via holes on the first photoresist layer, and the plurality of first via holes are located on the periphery of the first chip; forming the blocking member in the first via; forming a second photoresist layer on the side of the first photoresist layer away from the carrier; exposing and developing the first photoresist layer and the second photoresist layer to form a plurality of second via holes on the first photoresist layer and the second photoresist layer, and the plurality of second vias are located on the periphery of the plurality of first vias; The conductive pillars are formed in the second via holes. 4. The fan-out packaging method according to claim 3, wherein, The step of forming the blocking member in the first via hole includes: forming the blocking member in the first via hole by a metal sputtering process; Before the step of forming the second photoresist layer on the side of the first photoresist layer away from the carrier plate, the step includes: removing the sputtering on the surface of the first photoresist layer away from the carrier plate. Shoot metal. 5 . The fan-out packaging method according to claim 3 , wherein before the step of forming a plastic encapsulation layer on the side where the first chip is disposed on the carrier board, the method comprises: 6 . removing all of the first photoresist layer and all of the second photoresist layer; Insulating glue is formed at least on the periphery of the plurality of blocking members. 6 . The fan-out packaging method according to claim 3 , wherein before the step of forming a plastic encapsulation layer on the side where the first chip is disposed on the carrier, the method comprises: 6 . All of the second photoresist layer and the first photoresist layer around the conductive pillars are removed. 7 . The fan-out packaging method according to claim 5 , wherein the first chip comprises a first functional surface and a first non-functional surface arranged opposite to each other, and the first chip of the first chip has a first functional surface and a first non-functional surface. The non-functional surface faces the carrier board; before the step of forming a plastic encapsulation layer on the side where the carrier board is provided with the first chip, the method further includes: At least one second chip is disposed on the side of the first functional surface of the first chip facing away from the carrier board, and underfill is formed at least between the second functional surface of the second chip and the carrier board, and the blocking member is located in the underfill; wherein, the second functional surface of the second chip faces the first functional surface of the first chip, and the second chip spans at least part of the first chip and at least part of the blocking member adjacent to at least part of the first chip, and the second pad on the second functional surface of the second chip corresponds to the first function of the first chip at a position The first pad on the surface is electrically connected to the blocking member. 8 . The fan-out packaging method according to claim 7 , wherein the step of forming a plastic sealing layer on the side where the first chip is arranged on the carrier board comprises: 8 . The plastic sealing layer is formed on the side where the first chip is arranged on the carrier, and the plastic sealing layer covers the gap in the space surrounded by the conductive pillar, the second chip and the conductive pillar; The plastic encapsulation layer is ground from the side of the plastic encapsulation layer away from the carrier, so that the surface of the plastic encapsulation layer, the conductive pillar and the second chip are flush with the side away from the carrier. 9. The fan-out packaging method according to claim 5 or claim 6, wherein, The first chip includes a first functional surface and a first non-functional surface disposed opposite to each other, and the first functional surface of the first chip faces the carrier board; the carrier board is provided with the first functional surface The step of forming a plastic encapsulation layer on one side of the chip includes: forming a plastic encapsulation layer on the side where the first chip is arranged on the carrier, the plastic encapsulation layer covering the conductive pillars and the space surrounded by the conductive pillars the gap; wherein, the plastic sealing layer is flush with the surface of the conductive column on the side facing away from the carrier board. 10 . The fan-out packaging method according to claim 1 , wherein after removing the carrier board, the method further comprises: 10 . A first redistribution layer and a second redistribution layer are respectively formed on both sides in the length direction of the conductive pillar; wherein, the first redistribution layer is at least electrically connected to the conductive pillar and the first chip, so the second redistribution layer is electrically connected to the conductive column; A first electrical connection body is provided on the side of the first redistribution layer away from the conductive column, and a second electrical connection body is provided on the side of the second redistribution layer away from the conductive column.

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