CN114530383A - Fan-out type packaging method - Google Patents

Abstract

The application discloses a fan-out type packaging method, which comprises the following steps: providing a first carrier plate; forming a conductive mechanism on the first carrier plate; dispensing glue on the first carrier plate to form a blocking mechanism; wherein at least part of the conductive means is in contact with the blocking means; arranging a chip on the first carrier plate, and enabling the conductive mechanism and the blocking mechanism to be located on the periphery of the chip; forming a plastic packaging layer on one side of the first carrier plate, which is provided with the chip; the plastic packaging layer at least covers the periphery of the side surfaces of the chip, the blocking mechanism and the conducting mechanism, and the chip, the blocking mechanism and the conducting mechanism form an integral structure through the plastic packaging layer; and removing the first carrier plate. The fan-out type packaging method is simple to operate, deformation generated by shrinkage of the plastic packaging material can be reduced, and stability of the chip is guaranteed.

Description

Fan-Out Packaging Method

technical field

The present application relates to the technical field of semiconductor packaging, and in particular, to a fan-out packaging method.

Background technique

The descriptions in this section merely provide background information related to the disclosure in this specification and do not constitute prior art.

In the traditional fan-out packaging structure, since the plastic packaging material will deform due to shrinkage, it is easy to cause the chip to shift within the packaging structure, so that the plastic-encapsulated chip deviates from the original design position, which affects the stability of the chip.

It should be noted that the above description of the technical background is only for the convenience of clearly and completely describing the technical solutions of the present specification, and for the convenience of understanding of those skilled in the art. It should not be assumed that the above-mentioned technical solutions are known to those skilled in the art simply because they are described in the background section of this specification.

SUMMARY OF THE INVENTION

The main technical problem to be solved by the present application is to provide a fan-out packaging method, which is easy to operate, and can reduce the amount of deformation caused by shrinkage of the plastic packaging material, so as to ensure the stability of the chip.

In order to solve the above technical problems, a technical solution adopted in this application is to provide a fan-out packaging method, including:

provide a first carrier board;

forming a conductive mechanism on the first carrier;

Dispensing glue on the first carrier to form a blocking mechanism; wherein at least part of the conductive mechanism is in contact with the blocking mechanism;

A chip is arranged on the first carrier board, so that the conductive mechanism and the blocking mechanism are located on the periphery of the chip;

A plastic encapsulation layer is formed on the side of the first carrier plate on which the chip is provided; wherein, the plastic encapsulation layer at least covers the side periphery of the chip, the blocking mechanism and the conductive mechanism, and the chip, the The blocking mechanism and the conductive mechanism form an integral structure through the plastic sealing layer;

The first carrier plate is removed.

Further, the step of forming a blocking mechanism by dispensing glue on the first carrier includes:

The conductive mechanism is glued on the side of the conductive mechanism facing away from the first carrier board.

Further, the conductive mechanism includes a plurality of conductive members, and a plurality of the conductive members located on the same side of the chip form a conductive member group; the step of dispensing glue to the conductive mechanism includes:

The dotted colloid is brought into contact with at least part of the outer periphery of the side surfaces of at least part of the adjacent conductive members in the conductive member group.

Further, after the step of dispensing glue to the conductive mechanism, it also includes:

The blocking mechanism is cured by baking.

Further, the surface of the blocking mechanism located in the plastic sealing layer is a curved surface.

Further, the step of forming a conductive mechanism on the first carrier board includes:

forming a conductive layer on one side of the first carrier;

forming a photoresist layer on the side of the conductive layer facing away from the first carrier;

exposing and developing the photoresist layer to form a plurality of through holes on the photoresist layer;

Filling conductive material in the through hole to form the conductive mechanism;

The photoresist layer and the conductive layer are removed.

Further, the chip includes a functional surface and a non-functional surface disposed opposite to each other, and in the step of disposing the chip on the first carrier board, the functional surface is made to face the first carrier board.

Further, the step of forming the plastic encapsulation layer includes:

The plastic sealing layer is formed on the side where the chip is disposed on the first carrier, and the plastic sealing layer covers the conductive mechanism, the blocking mechanism and the gap in the space surrounded by the chip;

The plastic packaging layer is ground from the side of the plastic packaging layer away from the first carrier board, so that the conductive mechanism is exposed on the side away from the first carrier board.

Further, after the step of forming the plastic encapsulation layer and before the step of removing the first carrier board, the method further includes:

A first redistribution layer is formed on the side of the plastic sealing layer facing away from the first carrier board, and the first redistribution layer is electrically connected to an end of the conductive mechanism facing away from the first carrier board;

A first electrical conductor is disposed on the side of the first redistribution layer away from the plastic sealing layer, and the first electrical conductor is electrically connected to the first redistribution layer.

Further, after the step of removing the first carrier board, the method further includes:

A second carrier is arranged on the side of the first conductor facing away from the first redistribution layer;

A second redistribution layer is formed on the side of the plastic packaging layer facing away from the second carrier, the second redistribution layer and the end of the conductive mechanism facing away from the second carrier, the chip electrical connection;

A second conductor is provided on the side of the second redistribution layer away from the plastic sealing layer, and the second conductor is electrically connected to the second redistribution layer;

The second carrier plate is removed.

Different from the situation in the prior art, the beneficial effects of the present application are: the fan-out packaging method provided by the embodiments of the present application has lower cost and is easy to produce. A blocking mechanism is formed by dispensing glue on the periphery of the chip. The operation is simple. The blocking mechanism can be equivalent to a cofferdam retaining wall, which can limit the movement of the plastic sealing compound in the plastic sealing layer, so as to reduce the deformation amount caused by the shrinkage of the plastic sealing material and limit the displacement of the chip. , reduce the probability of chip warping; in addition, a conductive mechanism is also provided on the periphery of the chip, which can realize a three-dimensional vertical interconnection structure, which is beneficial to reduce the height of the fan-out packaging method; in addition, at least part of the conductive mechanism and the blocking mechanism are in contact, The chip, the blocking mechanism and the conductive mechanism form an integral structure through the plastic sealing layer, which greatly enhances the strength of the blocking mechanism and further ensures the stability of the chip.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. in:

1 is a flowchart of steps of a fan-out packaging method provided in this embodiment;

Fig. 2 is the specific step flow chart of step S20 in Fig. 1;

Fig. 3 is a flow chart of the steps between step S50 and step S60 in Fig. 1;

Fig. 4 is the step flow chart after step S60 in Fig. 1;

FIG. 5 is a schematic structural diagram of performing step S201 in FIG. 2 on the first carrier board;

FIG. 6 is a schematic structural diagram of performing step S202 and step S203 in FIG. 2 to FIG. 5;

FIG. 7 is a schematic structural diagram of performing step S204 in FIG. 2 on FIG. 6;

FIG. 8 is a schematic structural diagram of performing step S205 in FIG. 2 on FIG. 7;

FIG. 9 is a schematic structural diagram of performing step S30 in FIG. 1 on FIG. 8;

FIG. 10 is a schematic structural diagram of FIG. 9 after step S30 is performed;

FIG. 11 is a schematic structural diagram of FIG. 10 after step S40 in FIG. 1 is performed;

FIG. 12 is a schematic structural diagram of performing step S501 in FIG. 3 on FIG. 11 ;

FIG. 13 is a schematic structural diagram of performing step S502 in FIG. 3 on FIG. 12;

FIG. 14 is a schematic structural diagram of performing step S503 and step S504 in FIG. 3 to FIG. 13 ;

FIG. 15 is a schematic structural diagram of performing steps S60 and S601 on FIG. 14;

FIG. 16 is a schematic structural diagram of performing step S602 and step S603 in FIG. 4 to FIG. 15;

17 is a schematic structural diagram of performing step S604 in FIG. 4 on FIG. 16 , and FIG. 17 is also a schematic structural diagram of the first fan-out package device provided according to the packaging method of FIG. 1 ;

FIG. 18 is a schematic structural diagram of a second fan-out package device provided according to the packaging method of FIG. 1 .

Description of reference numbers:

1. First carrier board; 2. Conductive mechanism; 3. Blocking mechanism; 4. Chip; 5. Plastic encapsulation layer; 6. Photoresist layer; 7. Through hole; 8. Conductive material; 9. Conductive layer; component; 12, conductive component group; 13, functional surface; 14, non-functional surface; 15, first redistribution layer; 16, first conductor; 17, first insulating layer; 18, second carrier board; 19, The second redistribution layer; 20, the second conductor; 21, the second insulating layer.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening another element may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or it may be intervening with the other element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for the purpose of illustration only and do not represent the only embodiment.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are for the purpose of describing specific embodiments only, and are not intended to limit the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

See Figure 1. Embodiments of the present application provide a fan-out packaging method, including the following steps:

Step S10: providing a first carrier board 1;

Step S20: forming a conductive mechanism 2 on the first carrier board 1;

Step S30: Dispensing glue on the first carrier board 1 to form the blocking mechanism 3; wherein at least part of the conductive mechanism 2 is in contact with the blocking mechanism 3;

Step S40: disposing the chip 4 on the first carrier board 1, so that the conductive mechanism 2 and the blocking mechanism 3 are located at the periphery of the chip 4;

Step S50 : forming a plastic encapsulation layer 5 on the side of the first carrier board 1 where the chip 4 is provided; wherein, the plastic encapsulation layer 5 covers at least the side periphery of the chip 4 , the blocking mechanism 3 and the conductive mechanism 2 , the chip 4 , the blocking mechanism 3 and the conductive mechanism 2 . The mechanism 2 forms an overall structure through the plastic sealing layer 5;

Step S60 : removing the first carrier board 1 .

The fan-out packaging method provided by the embodiment of the present application has lower cost and is easy to produce. The blocking mechanism 3 is formed by dispensing glue on the periphery of the chip 4, and the operation is simple. The blocking mechanism 3 can be equivalent to a cofferdam retaining wall, which can limit the movement of the plastic sealing compound in the plastic sealing layer 5, so as to reduce the deformation amount of the plastic sealing material due to shrinkage. , limit the displacement of the chip 4 and reduce the probability of warping of the chip 4; in addition, a conductive mechanism 2 is also arranged on the periphery of the chip 4, which can realize a three-dimensional vertical interconnection structure, which is beneficial to reduce the height of the fan-out packaging method; The conductive mechanism 2 and the blocking mechanism 3 are in contact, and the chip 4 , the blocking mechanism 3 and the conductive mechanism 2 form an integral structure through the plastic sealing layer 5 , which greatly enhances the strength of the blocking mechanism 3 and further ensures the stability of the chip 4 .

In this embodiment, there may be multiple blocking mechanisms 3, and the multiple blocking mechanisms 3 may be located at different positions on the periphery of the chip 4, so as to block everywhere around the chip 4 and reduce the amount of deformation of the molding compound due to shrinkage. Specifically, the chip 4 may be rectangular, and a blocking mechanism 3 may be provided on the periphery of its four sides. Each of the four corners of the rectangular chip 4 may also be provided with a blocking mechanism 3 .

In step S30 , as shown in FIG. 9 , specifically, glue can be dispensed on the conductive mechanism 2 on the side of the conductive mechanism 2 facing away from the first carrier board 1 . Due to the adhesion of the bumps and the surface tension of the colloid, the colloid does not flow out of the bump area itself, and at the same time, due to the surface tension of the colloid, its surface is curved. The bump refers to the shape formed after the colloid falls into the conductive mechanism 2 on the first carrier board 1 . The blocking mechanism 3 is formed by dispensing glue, so that the surface of the blocking mechanism 3 located in the plastic sealing layer 5 is a curved surface, which can further increase the contact area between the blocking mechanism 3 and the plastic sealing layer 5, and make the combination of the two more closely, which is beneficial to the packaging structure. of stability.

In this embodiment, the conductive mechanism 2 may include a plurality of conductive members 11 , and the plurality of conductive members 11 located on the same side of the chip 4 form a conductive member group 12 . Each of the conductive members 11 may extend in the thickness direction of the chip 4 , that is, each of the conductive members 11 may extend in the vertical direction in FIG. 8 . The step of dispensing glue on the conductive mechanism 2 needs to make the glue dispensed in contact with at least part of the side peripheries of the adjacent conductive members 11 in at least part of the conductive member group 12, so that the space in the packaged device can be effectively utilized, and the blocking mechanism can be strengthened. 3 strength.

In this embodiment, after the step of dispensing glue on the conductive mechanism 2, it may further include the step of baking and curing the blocking mechanism 3, as shown in FIG. 10, so as to form the final blocking mechanism 3 and make the blocking mechanism 3 more stable.

In this embodiment, as shown in FIG. 2 , the step of forming the conductive mechanism 2 on the first carrier board 1 (ie, step S20 ) specifically includes the following steps:

Step S201: forming a conductive layer 9 on one side of the first carrier board 1;

Step S202: forming a photoresist layer 6 on the side of the conductive layer 9 facing away from the first carrier 1;

Step S203 : exposing and developing the photoresist layer 6 to form a plurality of through holes 7 on the photoresist layer 6 ;

Step S204: Filling the conductive material 8 in the through hole 7 to form the conductive mechanism 2;

Step S205 : removing the photoresist layer 6 and the conductive layer 9 .

In step S201 , referring to FIG. 5 , the conductive layer 9 needs to be uniformly deposited on the upper surface of the first carrier plate 1 . In step S203 , as shown in FIG. 6 , the photoresist layer 6 is exposed and developed above the photoresist layer 6 . Preferably, the extending direction of each through hole 7 is parallel and perpendicular to the upper surface of the first carrier board 1 . In step S204 , as shown in FIG. 7 , the height of the conductive material 8 filled in the through hole 7 needs to be less than or equal to the height of the through hole 7 to facilitate subsequent removal of the photoresist layer 6 . In step S205 , the photoresist layer 6 needs to be removed first, and then all the conductive layers 9 except under the conductive material 8 need to be removed.

In this embodiment, the chip 4 includes a functional surface 13 and a non-functional surface 14 arranged opposite to each other. As shown in FIG. 11 , in the step of disposing the chip 4 on the first carrier 1 , the functional surface 13 is made to face the first Carrier board 1. This embodiment does not limit the number of chips 4 , and there is at least one chip 4 to be packaged. The chip 4 may be a digital chip, or an analog chip, or a memory chip, or a passive device, or an active device. If there are multiple chips 4, the chips 4 can be stacked on each other, and the stacking method can be Wafer to wafer (wafer to wafer), chip to wafer (wafer to wafer) or chip to chip (wafer to wafer).

In other embodiments, the non-functional surface 14 of the chip 4 may face the first carrier board 1 . At this time, an electrical structure needs to be provided on the functional surface 13 of the chip 4 so as to lead the functional surface 13 of the chip 4 to the outside of the plastic encapsulation layer 5 . In this embodiment, the setting of the chip 4 in step S40 may be performed before step S20, or may be performed after step S30.

In this embodiment, as shown in FIG. 3 , the step of forming the plastic sealing layer 5 (ie, step S50 ) specifically includes:

Step S501 : forming a plastic sealing layer 5 on the side where the chip 4 is arranged on the first carrier board 1 , and the plastic sealing layer 5 covers the gap in the space surrounded by the conductive mechanism 2 , the blocking mechanism 3 and the chip 4 ;

Step S502 : grinding the plastic sealing layer 5 from the side of the plastic sealing layer 5 away from the first carrier board 1 , so that the side of the conductive mechanism 2 away from the first carrier board 1 is exposed.

The package structure after forming the plastic sealing layer 5 in step S501 is shown in FIG. 12 .

Specifically, after step S502 , as shown in FIG. 13 , the height of the plastic sealing layer 5 , the height of the blocking mechanism 3 , and the height of the conductive mechanism 2 are the same, so that the overall structure is more stable. Both ends of the conductive mechanism 2 in the longitudinal direction are exposed from the plastic encapsulation layer 5 to facilitate the subsequent formation of the rewiring layer. The conductive mechanism 2 , the blocking mechanism 3 and the plastic sealing layer 5 are arranged flush with the functional surface 13 , and the non-functional surface 14 is located in the plastic sealing layer 5 .

In this embodiment, as shown in FIG. 3 , after the step of forming the plastic encapsulation layer 5 and before the step of removing the first carrier 1 , that is, between steps S50 and S60 , the following steps are further included:

Step S503 : forming a first redistribution layer 15 on the side of the plastic sealing layer 5 facing away from the first carrier board 1 , and the first redistribution layer 15 is electrically connected to the end of the conductive mechanism 2 facing away from the first carrier board 1 ;

Step S504 : a first conductor 16 is provided on the side of the first redistribution layer 15 away from the plastic sealing layer 5 , and the first conductor 16 is electrically connected to the first redistribution layer 15 .

In the present embodiment, since the warpage of the packaged device itself and the positional displacement of the chip 4 are limited, the fan-out packaging method can perform high-density wiring of at least one layer. As shown in FIG. 14 , in step S504 , the first insulating layer 17 and the first conductor 16 may be disposed on the side of the first redistribution layer 15 away from the plastic sealing layer 5 at the same time. The first insulating layer 17 is used to protect the first redistribution layer 15 , and the first conductor 16 serves as an electrical lead-out structure to electrically lead out the first redistribution layer 15 .

In this embodiment, as shown in FIG. 4 , after the step of removing the first carrier board 1 (ie, step S60 ), the following steps are further included:

Step S601 : disposing the second carrier 18 on the side of the first conductor 16 facing away from the first redistribution layer 15 ;

Step S602 : forming a second redistribution layer 19 on the side of the plastic sealing layer 5 facing away from the second carrier board 18 , and the second redistribution layer 19 is respectively electrically connected to the end of the conductive mechanism 2 facing away from the second carrier board 18 and the chip 4 ;

Step S603 : disposing a second conductor 20 on the side of the second redistribution layer 19 away from the plastic sealing layer 5 , and the second conductor 20 is electrically connected to the second redistribution layer 19 ;

Step S604 : removing the second carrier board 18 .

The package structure after setting the second carrier board 18 in step S601 is shown in FIG. 15 . As shown in FIG. 16 , in step S603 , the second insulating layer 21 and the second conductor 20 may be simultaneously provided on the side of the second redistribution layer 19 away from the plastic sealing layer 5 . The second insulating layer 21 is used to protect the second redistribution layer 19 , and the second conductor 20 serves as an electrical lead-out structure to electrically lead out the second redistribution layer 19 . The package structure after the second carrier board 18 is removed after step S604 is shown in FIG. 17 .

The conductive mechanism 2 in this embodiment is fabricated by photolithography and electroplating, which can realize high-density arrangement, and with the re-wiring process, it can replace the traditional high-density vertical interconnected transition board structure, thereby realizing the minimization of the package volume, the electrical Minimization of loss and packaging costs.

In this embodiment, the first electrical conductor 16 and the second electrical conductor 20 may both have a Bump (bump) structure, or both may have a UBM (Under Bump Metal, under bump metal layer) structure, or the first electrical conductor 16 One of the second electrical conductors 20 is a Bump structure, and the other is a UBM structure.

In other embodiments, when multiple through holes 7 are formed on the photoresist layer 6 in step S203, only one group of through holes 7 may be formed, so that only one side of the chip 4 is formed with a conductive structure, and the final package structure is shown in FIG. 18 . Show.

It should be noted that in the description of this specification, the terms "first", "second", etc. are only used for the purpose of description and to distinguish similar objects, and there is no sequence between the two, nor can they be understood as indicating or imply relative importance. Also, in the description of this specification, unless otherwise specified, "plurality" means two or more.

Use of the terms "comprising" or "comprising" to describe combinations of elements, ingredients, components or steps herein also contemplates embodiments consisting essentially of those elements, ingredients, components or steps. By use of the term "may" herein, it is intended to indicate that "may" include any described attributes that are optional.

A plurality of elements, components, components or steps can be provided by a single integrated element, component, component or step. Alternatively, a single integrated element, component, component or step may be divided into separate multiple elements, components, components or steps. The disclosure of "a" or "an" used to describe an element, ingredient, part or step is not intended to exclude other elements, ingredients, parts or steps.

The above description is only an embodiment of the present application, and is not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies Fields are similarly included within the scope of patent protection of this application.

Claims (10)

1. A fan-out packaging method, comprising:

providing a first carrier plate;

forming a conductive mechanism on the first carrier plate;

dispensing glue on the first carrier plate to form a blocking mechanism; wherein at least part of the conductive means is in contact with the blocking means;

arranging a chip on the first carrier plate, and enabling the conductive mechanism and the blocking mechanism to be located on the periphery of the chip;

forming a plastic packaging layer on one side of the first carrier plate, which is provided with the chip; the plastic packaging layer at least covers the periphery of the side surfaces of the chip, the blocking mechanism and the conducting mechanism, and the chip, the blocking mechanism and the conducting mechanism form an integral structure through the plastic packaging layer;

and removing the first carrier plate.

2. The fan-out packaging method of claim 1, wherein the step of dispensing a blocking mechanism on the first carrier board comprises:

and dispensing the conductive mechanism at one side of the conductive mechanism back to the first carrier plate.

3. The fan-out packaging method of claim 2, wherein the conductive mechanism comprises a plurality of conductive members, and wherein the plurality of conductive members on the same side of the chip form a conductive member group; the step of dispensing the conductive mechanism comprises:

and enabling the pointed colloid to be in contact with the periphery of the side face of at least part of the adjacent conductive piece in at least part of the conductive piece group.

4. The fan-out packaging method of claim 2, wherein the step of dispensing the conductive mechanism is followed by:

baking and curing the blocking mechanism.

5. The fan-out packaging method of claim 1, wherein a surface of the blocking mechanism located within the plastic encapsulant layer is a curved surface.

6. The fan-out packaging method of claim 1, wherein the step of forming a conductive mechanism on the first carrier board comprises:

forming a conductive layer on one side of the first carrier plate;

forming a light resistance layer on one side of the conducting layer, which is opposite to the first carrier plate;

exposing and developing the photoresist layer to form a plurality of through holes on the photoresist layer;

filling a conductive material into the through hole to form the conductive mechanism;

and removing the light resistance layer and the conductive layer.

7. The fan-out packaging method of claim 1, wherein the chip comprises a functional side and a non-functional side opposite to each other, and the step of disposing the chip on the first carrier places the functional side facing the first carrier.

8. The fan-out packaging method of claim 1, wherein the step of forming a molding layer comprises:

forming the plastic packaging layer on one side of the first carrier plate, which is provided with the chip, and covering the gaps in the space surrounded by the conductive mechanism, the blocking mechanism and the chip with the plastic packaging layer;

and grinding the plastic packaging layer from one side of the plastic packaging layer departing from the first carrier plate so as to expose one side of the conductive mechanism departing from the first carrier plate.

9. The fan-out packaging method according to claim 1, further comprising, after the step of forming a molding layer and before the step of removing the first carrier:

forming a first rewiring layer on one side, back to the first carrier plate, of the plastic packaging layer, wherein the first rewiring layer is electrically connected with one end, back to the first carrier plate, of the conductive mechanism;

and arranging a first conductor on one side of the first rewiring layer, which is far away from the plastic packaging layer, wherein the first conductor is electrically connected with the first rewiring layer.

10. The fan-out packaging method of claim 9, further comprising, after the step of removing the first carrier board:

arranging a second carrier plate on one side of the first conductor, which is opposite to the first rewiring layer;

forming a second rewiring layer on one side, back to the second carrier plate, of the plastic packaging layer, wherein the second rewiring layer is electrically connected with one end, back to the second carrier plate, of the conductive mechanism and the chip respectively;

arranging a second conductor on one side of the second rewiring layer, which is far away from the plastic packaging layer, wherein the second conductor is electrically connected with the second rewiring layer;

and removing the second carrier plate.

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