CN202394881U - Semiconductor package structure for stacking - Google Patents

Abstract

The utility model discloses a semiconductor packaging structure for stacking, which comprises a substrate; the chip is arranged on the upper surface of the substrate; a protective layer arranged on the upper surface of the substrate to cover the chip and having a thermal expansion coefficient similar to that of the substrate; and a plurality of conductive convex columns which penetrate through the protective layer and are correspondingly connected to the upper surface of the substrate. Because the protective layer and the substrate are components made of similar insulating materials, the warping phenomenon of the substrate caused by stress action can be avoided due to the close thermal expansion coefficients of the protective layer and the substrate, and meanwhile, the arrangement distance required by the conductive convex columns is smaller, which is beneficial to improving the overall circuit layout density of the packaging structure.

Description

Semiconductor package structure for stacking

technical field

The utility model relates to a package structure, in particular to a semiconductor package structure for stacking which can avoid warpage of the substrate and help to improve the overall circuit layout density.

Background technique

Nowadays, the semiconductor packaging industry has developed various types of packaging structures to meet various needs. Generally speaking, most of the packaging process is to lay out chips on the substrate. After the chips are installed, they are then covered with encapsulant , various system in package (SIP) design concepts are commonly used in the architecture of high-density packaging structures, one of which is the stacking of packages on packages (package on package, POP).

As shown in FIG. 1 , the structure of the package-on-package (POP) refers to first completing a first package with a first chip 90, a first substrate 91 and a first packaging compound 92, and then on the first package. The upper surface of the encapsulant 92 of the package is stacked with another complete second package having the second chip 80, the second substrate 81 and the second encapsulant 82, wherein the first encapsulant 92 of the first package will Several holes are opened to expose the pads on the upper surface of the first substrate 91; the pads on the lower surface of the second substrate 81 of the second package are electrically connected to the On the first substrate 91 of the first package, thus forming a composite package structure. The pads on the lower surface of the first substrate 91 are further combined with several external solder balls 93 as input/output terminals.

Since the above-mentioned first package body and the second package body are correspondingly connected through the first solder ball 94 and the second solder ball 83, and the diameter of the first solder ball 94 and the second solder ball 83 is usually greater than 100 microns, so the tin Balls often need to form holes with a diameter greater than 100 microns in the first encapsulant 92 of the first package, which affects the number of pads in the circuit and the layout density of the pad spacing.

Furthermore, since the materials of the first encapsulant 92 and the second encapsulant 82 are usually selected from epoxy resin, their coefficient of thermal expansion (CTE) is between 3 and 4; while the first substrate 91 and the second substrate 81 are It is a composite material selected from polypropylene and glass fiber, and its thermal expansion coefficient is about 17. Due to the difference in thermal expansion coefficient, the first encapsulant 92 and the second encapsulant 82 are disposed on the first substrate 91 and the second substrate 81. The thermal expansion and contraction stress will cause the first substrate 91 and the second substrate 81 to warp, which may cause internal circuit breakage (crack), resulting in defective products.

Therefore, it is necessary to provide a semiconductor package structure for stacking to solve the problems existing in the prior art.

Utility model content

In view of this, the utility model provides a semiconductor package structure for stacking to solve the problem that the circuit layout density of the existing package-on-package (POP) structure needs to be improved, and the substrate is prone to warping.

The main purpose of this utility model is to provide a semiconductor package structure for stacking. The protective layer and the substrate for the package are components made of insulating materials with the same thermal expansion coefficient, which can prevent the substrate from warping. At the same time, the inside of the protective layer is Replacing solder balls with conductive bumps also helps to improve the overall circuit layout density of the package structure.

In order to achieve the aforementioned purpose of the utility model, the utility model provides a semiconductor packaging structure for stacking, which includes:

a substrate;

a chip disposed on the upper surface of the substrate;

A protective layer is provided on the upper surface of the substrate to cover the chip, and the difference between the thermal expansion coefficients of the protective layer and the substrate is less than 5; and

Several conductive studs penetrate through the protection layer and are correspondingly connected to the upper surface of the substrate.

In an embodiment of the present invention, the substrate and the protective layer include a prepreg made of glass fiber and epoxy resin.

In an embodiment of the present invention, several electrical connection portions are provided on the upper surface of the substrate, and the conductive protrusions are correspondingly provided on the electrical connection portions of the substrate.

In an embodiment of the present invention, the electrical connection part is a plurality of pads.

In an embodiment of the present invention, the conductive protrusions are connected to the electrical connection portion of the substrate through solder paste.

In an embodiment of the present invention, the conductive protrusions are correspondingly arranged on the electrical connection portion of the substrate through a lamination process, that is, the conductive protrusions can be regarded as passing through the An embedded conductive stud is embedded in the protection layer and pressed onto the electrical connection portion of the substrate.

In an embodiment of the present invention, the conductive studs are selected from copper stud bumps or nickel stud bumps.

In one embodiment of the present invention, the upper surface of the substrate is provided with several chip connection parts; the chip has an active surface, and the active surface faces downward and is provided with several chip pads, wherein the The chip pads are electrically connected to several chip connection portions on the upper surface of the substrate through bumps.

In an embodiment of the present invention, a redistribution layer is provided on the upper surface of the protection layer, and the redistribution layer is integrally connected to the conductive protrusions.

In an embodiment of the present invention, each of the conductive protrusions is disposed in a hole in the protective layer, and the diameter of the hole is less than 100 microns.

Description of drawings

FIG. 1 is a schematic structural view of a conventional package-on-package package structure.

FIG. 2 is a schematic structural view of the semiconductor package structure for stacking according to the first embodiment of the present invention.

FIG. 3A is a schematic diagram of a partial structure of the semiconductor package structure for stacking in FIG. 2 , illustrating a structure in which chips are connected to a substrate.

3B is a partial structural schematic diagram of the semiconductor package structure for stacking in FIG. 2 made following FIG. 3A , showing that the protective layer is disposed on the substrate and covers the chip, and also shows the process of setting the conductive bumps.

FIG. 3C is a partial structural schematic diagram of the semiconductor package structure for stacking in FIG. 2 made following FIG. 3B , showing a structure in which a conductive layer with conductive bumps is laminated on the protective layer.

FIG. 3D is a schematic structural view of a semiconductor package structure for stacking according to a second embodiment of the present invention.

Detailed ways

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the preferred embodiments of the present invention are specifically cited below, together with the accompanying drawings, for a detailed description as follows. Furthermore, the directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc. , are for orientation only with reference to the attached drawings. Therefore, the used directional terms are used to illustrate and understand the present invention, but not to limit the present invention.

Please refer to FIG. 2 , which schematically discloses a structural schematic diagram of a semiconductor package structure for stacking according to a first embodiment of the present invention. The utility model provides a semiconductor packaging structure for stacking, which includes a substrate 10 , a chip 20 , a protective layer 11 and several conductive protrusions 13 .

Please refer to FIG. 2, the substrate 10 is a packaging substrate, which is preferably a member selected from glass fiber and epoxy resin. The upper surface of the substrate 10 is provided with several electrical connection parts 100 and chips. The lower surface of the connecting portion is provided with several welding pads and solder balls 12 connecting the welding pads. The electrical connection part 100 and the chip connection part are preferably several pads made of copper material.

Please refer to Fig. 2, the chip 20 is arranged on the upper surface of the substrate 10. Pads, wherein the chip pads are electrically connected to several chip connection portions on the upper surface of the substrate 10 through the bumps 200 .

Referring to FIG. 2 , the protective layer 11 is disposed on the upper surface of the substrate 10 to cover the chip 20 . The protective layer 11 and the substrate 10 are members made of materials with similar thermal expansion coefficients, and are preferably selected from glass fibers and epoxy resins. The similar thermal expansion coefficients here refer to both The difference in coefficient of thermal expansion is less than 5.

Please refer to FIG. 2, the conductive studs 13 are penetrated in the protective layer 11 and correspondingly connected to the electrical connection portion 100 on the upper surface of the substrate 10. In more detail, the protective layer 11 has several The hole corresponding to the electrical connection portion 100 on the upper surface of the bare substrate 10, and the conductive protrusion 13 is provided on the electrical connection portion 100 of the substrate 10 corresponding to the hole penetrated into the protective layer 11 through a lamination process; Alternatively, the bottom surface of the conductive protrusion 13 is preferably connected to the electrical connection portion 100 of the substrate 10 through the solder paste 130 . Furthermore, the conductive bumps 13 are selected from copper stud bumps or nickel stud bumps; the conductive studs 13 pass through the protection layer 11 with a hole diameter less than 100 microns.

Since the protective layer 11 and the substrate 10 are components made of materials with the same thermal expansion coefficient, they are not affected by the stress of thermal expansion and contraction, thereby preventing the substrate 10 from warping. Furthermore, the hole diameter of the conductive stud 13 pierced through the protective layer 11 is less than 100 microns, which is smaller than the hole diameter required by the existing solder ball arrangement, so it can help to improve the circuit. The number of pads and the layout density of the pad spacing.

Please refer to FIGS. 3A-3C , which respectively schematically disclose the structural schematic diagrams for manufacturing the semiconductor package structure for stacking in the embodiment of FIG. 2 . Please refer to FIG. 3A , first prepare the substrate 10, and set the chip 20 on the upper surface of the substrate 10, wherein the active surface of the chip 20 faces downward, and the chip pads pass through the bumps. 200 corresponds to several chip connection parts electrically connected to the upper surface of the substrate 10; continuing FIG. 3A, please refer to FIG. 3B, the protective layer 11 is formed on the substrate 10 and the chip 20 through a mold, so that The protective layer 11 is disposed on the upper surface of the substrate 10 to cover the chip 20, and the protective layer 11 has holes corresponding to the exposed electrical connection portion 100 of the substrate 10. 13, the conductive layer is carried through a carrier board 30, and is aligned with the hole in the protective layer 11 to perform the lamination process, wherein the bottom surface of the conductive protrusion 13 is coated with solder paste 130; continue 3B, please refer to FIG. 3C, the conductive protrusion 13 of the conductive layer is set in the hole of the protective layer 11 through a lamination process and fills the hole, and then connected to the electrical property of the substrate 10 through the solder paste 130. On the connecting portion 100 ; finally, the conductive layer parts other than the conductive bumps 13 are removed, that is, the semiconductor package structure for stacking as shown in the embodiment shown in FIG. 2 is formed.

Please refer to FIG. 3D , which discloses a schematic structural diagram of a semiconductor package structure for stacking in the second embodiment of the present invention. The semiconductor package structure for stacking in the second embodiment is also formed by the steps in FIGS. The difference of one embodiment is that the conductive layer in FIG. 3C is etched to form circuits, and then the redistribution layer 131 integrally connected with the conductive studs is formed on the upper surface of the protective layer 11 .

As mentioned above, compared with the existing packaging structure of stacking packages on the package, there are technical problems that the circuit layout density is limited due to the size of the solder balls, and the substrate is prone to warping. The utility model provides a stacking A semiconductor packaging structure comprising a substrate; a chip disposed on the upper surface of the substrate; a protective layer disposed on the upper surface of the substrate to cover the chip and made of the same material as the substrate with the same thermal expansion coefficient and several conductive protrusions, which are penetrated in the protective layer and correspondingly connected to the upper surface of the substrate. Since the protective layer and the substrate are made of the same material, the similar thermal expansion coefficient will It can avoid warping of the substrate due to stress, and at the same time, the solder balls are replaced by conductive bumps, which requires a relatively small spacing, and also helps to improve the overall circuit layout density of the packaging structure.

The utility model has been described by the above-mentioned relevant embodiments, but the above-mentioned embodiments are only examples for implementing the utility model. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claims are included in the scope of the present invention.

Claims (10)

1. one kind is piled up and uses semiconductor package, and it is characterized in that: said piling up with semiconductor package comprises:

One substrate;

One chip is located at the upper surface of said substrate;

One protective layer is located at the upper surface of said substrate and is covered said chip, and the difference value of the thermal coefficient of expansion of said protective layer and said substrate is less than 5; And

Several conduction projections are arranged in the said protective layer and correspondence is connected to upper surface of base plate.

2. as claimed in claim 1 piling up used semiconductor package, it is characterized in that: said substrate and said protective layer comprise by glass fiber and pressing sheet that epoxy resin constituted jointly.

3. as claimed in claim 1 piling up used semiconductor package, it is characterized in that: the upper surface of said substrate is provided with several electrical junctions, and said conduction projection is that correspondence is located on the electrical junction of said substrate.

4. as claimed in claim 3 piling up used semiconductor package, it is characterized in that: said electrical junction is several connection pads.

5. as claimed in claim 3 piling up used semiconductor package, it is characterized in that: said conduction projection is connected on the electrical junction of said substrate through tin cream.

6. as claimed in claim 5 piling up used semiconductor package, it is characterized in that: said conduction projection is to be arranged in the said protective layer and to press to the embedded conduction projection on the electrical junction of said substrate.

7. as claimed in claim 6 piling up used semiconductor package, it is characterized in that: said conduction projection is selected from copper post projection or nickel post projection.

8. as claimed in claim 1 piling up used semiconductor package, it is characterized in that: the upper surface of said substrate is provided with several chip connecting portions; Said chip has an active surface, said active surface down and be provided with several chip pad, wherein said chip pad is through corresponding several chip connecting portions that electrically connect the upper surface of said substrate of projection.

9. as claimed in claim 1 piling up used semiconductor package, it is characterized in that: said protective layer upper surface is provided with the layer that reroutes, and the said layer one that reroute connects said conduction projection.

10. as claimed in claim 1 piling up used semiconductor package, it is characterized in that: each said conduction projection is arranged in the hole of said protective layer, and the aperture of described hole is less than 100 microns.

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