CN114497021A

CN114497021A - Integrated circuit device and processing method thereof, electronic equipment and board card

Info

Publication number: CN114497021A
Application number: CN202011168013.1A
Authority: CN
Inventors: 不公告发明人
Original assignee: Anhui Cambricon Information Technology Co Ltd
Current assignee: Anhui Cambricon Information Technology Co Ltd
Priority date: 2020-10-27
Filing date: 2020-10-27
Publication date: 2022-05-13

Abstract

The present disclosure relates to an integrated circuit device and its processing method, electronic equipment and board, wherein the integrated circuit device can be implemented in a combined processing device, and the combined processing device can include a computing processing device and other processing devices. The computing processing device interacts with other processing devices to jointly complete the computing operation specified by the user. The combined processing device may further include a storage device, which is respectively connected to the computing processing device and other processing devices, and is used for storing data of the computing processing device and other processing devices in some application scenarios. The solution of the present disclosure can realize the interconnection and mutual access and interface multiplexing at the die level, and also expand the bandwidth and capacity of the storage in some application scenarios.

Description

Integrated circuit device and processing method thereof, electronic equipment and board card

Technical Field

The present disclosure relates generally to the field of electrical circuits. More particularly, the present disclosure relates to an integrated circuit device, a method of processing the same, an electronic apparatus, and a board card.

Background

Currently, in chip design, various functions expected to be obtained may be divided so as to be implemented by two or more small-sized chips, respectively. Based on this, after each chiplet is designed and taped separately, multiple chiplets are sealed together by a packaging process. Although such chip design and packaging approach improves the yield of the chip and reduces the cost of the whole product to some extent, in some application scenarios, the approach has poor flexibility and extensibility in layout and also fails to fully function as a die-to-die interface for interconnecting chips.

Disclosure of Invention

In view of at least the foregoing technical problems, the present disclosure provides, in various aspects and embodiments thereof, an integrated circuit device, a method of processing the same, an electronic apparatus, and a board card, thereby fully expanding and utilizing a die-to-die interface.

In one aspect, the present disclosure provides an integrated circuit device comprising: a printed circuit board; a first chip disposed on the printed circuit board and having a die-to-die interface, a second chip disposed on the printed circuit board, wherein the first chip is connected with the second chip by the die-to-die interface and via traces of the printed circuit board.

In another aspect, the present disclosure provides a method of processing an integrated circuit device, comprising:

providing a printed circuit board having a first land and a second land thereon and connected via traces of the printed circuit board;

providing a first chip and a second chip, wherein the first chip has a die-to-die interface;

soldering the first chip to the first bond pad and soldering the second chip to a second bond pad such that the first chip is connected with the second chip through a die-to-die interface and via traces of a printed circuit board.

In yet another aspect, the present disclosure provides an electronic device and board card including an integrated circuit device as described above and in the embodiments below.

By utilizing the integrated circuit device and the processing method thereof, the electronic device, and the board of the present disclosure, the die-to-die interface can be multiplexed as a transmission interface having another physical property, for example, as a transmission interface for interfacing with a memory chip. By the multiplexing of the interface, the memory bandwidth and capacity of the chip can be expanded, so that the chip can provide larger computing capacity and obtain optimal operation performance. In addition, the method and the device can also connect the die to the die interface and the interface of another chip by utilizing the routing of the printed circuit board, so that a plurality of chips are interconnected, the application of multi-chip interconnection is realized, and the competitiveness of products is further improved. In summary, the present disclosure realizes a packaging method to achieve the application of multi-chip interconnection. Further, in the context of a single chip application, since the die-to-die interface is multiplexed as a transmission interface (e.g., a storage interface for storage purposes) interfacing with a memory chip, thereby enabling connection of a chip having a die-to-die interface (i.e., a first chip of the present disclosure) to a memory (i.e., a second chip of the present disclosure), the memory bandwidth and capacity of the chip having a die-to-die interface is extended.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 is a schematic diagram illustrating a structure of an integrated circuit device according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram illustrating a single-chip based integrated circuit device according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram illustrating a dual chip based integrated circuit device according to an embodiment of the present disclosure;

FIG. 4 is a flow chart illustrating a method of processing an integrated circuit device according to an embodiment of the present disclosure;

FIG. 5 is a block diagram illustrating a combined treatment device according to an embodiment of the present disclosure; and

fig. 6 is a schematic diagram illustrating a structure of a board card according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, not all embodiments of the present disclosure. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

The details of various embodiments of the present disclosure will be described in detail below with reference to fig. 1-6.

Fig. 1 is a schematic diagram illustrating a structure of an integrated circuit device 100 according to an embodiment of the disclosure. As shown in fig. 1, the integrated Circuit device 100 may include a Printed Circuit Board ("PCB"), and the first chip 101 and the second chip 102 are disposed on the PCB. In one embodiment, the aforementioned first chip and second chip may be packaged chips. In another embodiment, the first chip 101 may have an interface 103. Similarly, the second chip 102 may have an interface 104. The interfaces 103 and 104 may be connected by, for example, PCB traces. In one exemplary implementation scenario, the first Chip 101 may be a System On Chip ("SOC") Chip and the second Chip 102 may be a memory Chip. Alternatively, the second chip may be the same type of chip as the first chip, e.g., both the first chip and the second chip may be system-on-chip chips.

According to aspects of the present disclosure, interface 103 may be a Die-to-Die (D2D) interface for chip interconnection. For example, in some application scenarios, multiple chips (also referred to as dies in the context of the present disclosure) may be interconnected through the D2D interface and processed through semiconductor processing to form an integrated circuit for performing certain functions. In one application scenario, when the second chip 102 is a memory chip (i.e., when based on a single chip design in fig. 2), the interface 103 as a D2D interface may be multiplexed as a transmission interface that interfaces with the memory chip via PCB traces, such as a storage interface for storage purposes. In one embodiment, the memory chip may be a Double data Rate synchronous dynamic random access memory (DDR SDRAM). Correspondingly, the interface 103 may be multiplexed as a DDR interface for storage purposes. In another application scenario, when the second chip 102 is a system-on-chip of the same type as the first chip 101 (i.e., when the design in fig. 3 is based on a dual chip), the interface 103 and the interface 104 may both be D2D interfaces. The single chip and dual chip based designs of the present disclosure will be described in detail below in conjunction with fig. 2 and 3.

FIG. 2 is a schematic diagram illustrating an integrated circuit device 200 based on a single chip architecture according to an embodiment of the disclosure. Here, a single chip architecture means that the integrated circuit device 200 includes only a single chip with a D2D interface. From the above description of fig. 1, those skilled in the art will appreciate that the integrated circuit device 200 shown in fig. 2 may be an implementation of the integrated circuit device 100 shown in fig. 1. Accordingly, certain features and details of the integrated circuit device 100 described above in connection with fig. 1 also apply to the integrated circuit device 200.

As shown in fig. 2, the integrated circuit device 200 may include a PCB (i.e., the PCB shown in fig. 1), and a packaged system-on-chip 201 (which may be regarded as the first chip shown in fig. 1) and a memory chip (which may be regarded as the second chip shown in fig. 1) are disposed on the PCB. In one embodiment, the Memory chip may be a Dynamic Random Access Memory ("DRAM") chip 203 as shown. In one implementation scenario, the packaged system-on-chip 201 may have a D2D-DDR interface 202 and an optional first General Purpose Input Output ("GPIO") 204. As understood by those skilled in the art, a GPIO interface may typically have multiple pins. In some application scenarios, these pins may output or read in a high or low level. By means of these pins, information interaction between chips or between chips and other hardware can be realized to realize various operations. For example, the GPIO interface may control the operation of other chips or hardware, read an operation status signal (e.g., various types of interrupt signals) of the chip or hardware, configure other chips or hardware, and so on.

As shown in the figure, the D2D-DDR interface 202 is a D2D interface and is multiplexed here as a DDR interface. The D2D-DDR interface 202 may interface with the transmission interface of the DRAM203 through, for example, PCB traces, thereby implementing high speed storage of the system-on-chip 201. In one embodiment, the system-on-chip 201 also has a dedicated DDR interface 205 that can interface with another memory chip DRAM 206, thereby expanding the memory space of the system-on-chip and increasing the efficiency of memory access operations. In an implementation scenario, the first GPIO204 may be connected to a peripheral device (not shown), so that operations of communication, configuration, debugging (debug), and the like of the soc chip 201 and the peripheral device may be implemented.

With the foregoing configuration of the present disclosure, after the soc 201 is started, the D2D interface may be configured to be used as a DDR interface through the internal register to complete multiplexing, and at the same time, both the controller of the soc 201 and its physical layer interface are configured to be a DDR function to support communication transmission between the soc 201 and the DRAM 203.

The integrated circuit device 200 of the present disclosure is described above in connection with fig. 2. It can be seen that the D2D interface in the integrated circuit device 200 is multiplexed into the DDR interface. Further, the multiplexed DDR interface provides data or command transport between the system-on-chip 201 and the DRAM 203. Thus, by interconnecting with the memory chip via the D2D interface, the integrated circuit device 200 has expanded memory bandwidth and capacity. In addition, because the D2D interface is multiplexed into the DDR interface, the scheme of the present disclosure also improves the utilization rate of the D2D interface.

Fig. 3 is a schematic diagram illustrating a dual chip architecture based integrated circuit device 300 according to an embodiment of the present disclosure. In contrast to the single-chip architecture described above, the dual-chip architecture herein means that the integrated circuit device 300 includes two chips with D2D interfaces. From the above description of FIG. 1, those skilled in the art will appreciate that the integrated circuit device 300 shown in FIG. 3 may be another implementation of the integrated circuit device 100 shown in FIG. 1. Accordingly, certain features and details of the integrated circuit device 100 described above in connection with fig. 1 also apply to the integrated circuit device 300.

As shown in fig. 3, integrated circuit device 300 may include a PCB (i.e., the PCB shown in fig. 1) and a packaged system-on-chip 201 (i.e., the first chip shown in fig. 1) and a packaged system-on-chip 301 (i.e., the second chip shown in fig. 1) are disposed on the PCB, where system-on-chip 201 and system-on-chip 301 may be the same type of SOC. In one implementation scenario, the system-on-chip 201 may have a DDR interface 202, a D2D interface 205, and an optional first GPIO 204. Correspondingly, the soc chip 301 may also have a DDR interface 302, a D2D interface 305, and an optional second GPIO 304. As shown in the figure, the D2D interface 205 and the D2D interface 305 may be connected by, for example, PCB traces, so as to implement, for example, communication and data interaction between the SOC chip 201 and the SOC chip 301. As also shown in the figure, the DDR interface 202 and the DDR interface 302 may be respectively connected to the DRAM203 and the DRAM 303 through, for example, PCB traces, so as to implement high-speed access between the system-on-chip 201 and the system-on-chip 301.

As further shown in the figure, the first GPIO204 may be connected to the second GPIO 304 through, for example, PCB traces, so that operations such as low-speed communication, configuration, debugging and the like between the two chips can be implemented. In one embodiment, the SoC 201 may be configured as a master chip and the SoC 301 may be configured as a slave chip, for example, by configuring GPIOs to enable master-slave communication between the two.

Based on the foregoing description, after the soc 201 and the soc 301 are booted, the D2D interface may be further configured to be used only as the D2D interface instead of being multiplexed as the DDR interface through the internal register, and the controller of the chip and its physical layer interface are configured as the D2D function, so as to implement interconnection and communication between the soc 201 and the soc 301. In some scenarios, necessary initialization or reset operations may also be performed on the aforementioned master-slave configuration.

The integrated circuit device 300 of the present disclosure is described above in conjunction with fig. 3. As can be seen, the D2D interface of the SOC chip 201 in the IC device 300 is interconnected with the D2D interface of the SOC chip 301 via PCB traces for bi-directional transmission. In addition, a master-slave communication configuration between the system-on-chip 201 and the system-on-chip 301 may be implemented by configuring GPIOs. Thus, the integrated circuit device 300 is equivalent to adding one slave chip, thereby providing greater computing power and performance.

Fig. 4 is a flow chart illustrating a method 400 of processing an integrated circuit device according to an embodiment of the present disclosure. As shown, at step 401, the method 400 provides a printed circuit board and arranges a first land and a second land on the printed circuit board, which may be connected therebetween by, for example, PCB traces. As previously described in connection with fig. 1-3, those skilled in the art will appreciate that the first and second bond pads herein may be adapted to the size and pins of the first chip and the second chip.

At step 402, the method 400 provides a first chip and a second chip, which may be packaged chips. In one implementation scenario, the first chip may be a system-on-chip and the second chip may be a memory chip (e.g., DRAM), in which case the first chip has a D2D interface. In another implementation scenario, the first chip and the second chip may be the same type of system-on-chip, in which both the first chip and the second chip have a D2D interface.

At step 403, the method 400 solders the first chip and the second chip provided in step 402 above to the first bonding pad and the second bonding pad, respectively, described in step 401 above, so as to interconnect the D2D interface of the first chip and the D2D interface of the second chip via PCB traces.

In an exemplary processing scenario, a PCB may be first designed, typically using computer software, including performing signal and power integrity simulation experiments on the PCB and its internal traces, to ensure that various interfaces (e.g., a D2D interface and a DDR interface) can communicate via PCB trace interconnection after subsequent chip soldering. After the simulation results are correct, the first chip and the second chip, and other related devices, may be Mounted on the PCB by Surface mount Technology ("SMT") according to the drawings of the PCB design based on the method 400.

Fig. 5 is a block diagram illustrating a combined processing device 500 according to an embodiment of the present disclosure. As shown in fig. 5, the combined processing device 500 includes a computing processing device 501, other processing devices 503, and a storage device 504. Further, one or more computing devices 502 may be included in the computing processing device, and the computing processing device 501 and other processing devices 503 each include a D2D interface 505 to enable interconnection in accordance with aspects of the present disclosure.

In various embodiments, the computing processing device of the present disclosure may be configured to perform user-specified operations. In an exemplary application, the computing processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included within a computing processing device may be implemented as an artificial intelligence processor core or as part of a hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as artificial intelligence processor cores or as part of a hardware structure of an artificial intelligence processor core, computing processing devices of the present disclosure may be considered to have a single core structure or a homogeneous multi-core structure.

In an exemplary operation, the computing processing device of the present disclosure may interact with other processing devices through a D2D interface to collectively perform user-specified operations. Other Processing devices of the present disclosure may include one or more types of general and/or special purpose processors, such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), and artificial intelligence processors, depending on the implementation. These processors may include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, etc., and the number may be determined based on actual needs. As previously mentioned, the computing processing device of the present disclosure may be considered to have a single core structure or an isomorphic multi-core structure only. However, when considered together, a computing processing device and other processing devices may be considered to form a heterogeneous multi-core structure. In conjunction with the foregoing aspects of the present disclosure, when the computing processing device 501 and the other processing device 503 are connected via a D2D interface, the two may implement die-level interconnect access.

In one or more embodiments, the other processing devices may also interface the computing processing device 501 of the present disclosure with external data and controls, performing basic controls including, but not limited to, data handling, starting and/or stopping of the computing device, and the like. In further embodiments, other processing devices may also cooperate with the computing processing device to collectively perform computational tasks.

In one or more embodiments, the D2D interface may be utilized to transfer data and control instructions between a computing processing device and other processing devices. For example, the computing processing device may obtain input data from other processing devices via the D2D interface, and write the input data into a storage device (or memory) on the computing processing device. Further, the computing processing device may obtain control instructions from other processing devices via the D2D interface and write the control instructions into a control cache on the computing processing device slice. Alternatively or optionally, the D2D interface may also read data in a storage device of the computing processing device and transmit to other processing devices. In conjunction with the scenario of multiplexing the D2D interface as a DDR interface of the present disclosure, when the other processing device 503 is implemented as a DDR SDRAM, the computing processing device 501 may implement operations such as transmission (e.g., storage) of information through the D2D interface multiplexed as a DDR interface.

Additionally or alternatively, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage means is connected to the computing processing means and the further processing means, respectively. In one or more embodiments, the storage device may be used to hold data for the computing processing device and/or the other processing devices. For example, the data may be data that is not fully retained within internal or on-chip storage of a computing processing device or other processing device. In conjunction with aspects of the present disclosure, when the computing processing device 501 is implemented as the first chip of the present disclosure having a D2D interface, information transfer with the storage device 504 (which in this scenario is a DDR SDRAM) may be implemented by multiplexing the D2D interface as a DDR interface.

Fig. 6 is a schematic diagram illustrating a structure of a board 600 according to an embodiment of the disclosure, wherein a Chip 603 may be a System on Chip (SoC) in one implementation. In one implementation scenario, one of the chips 603 may be connected to other related components through an external interface device 604, such as an external device 605 outside the board shown in the figure. The relevant component may be, for example, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface. In some application scenarios, other processing units (e.g., video codecs) and/or interface modules (e.g., DRAM interface and/or D2D interface 505 supporting the aforementioned operations of the present disclosure), etc. may be integrated on the chip 603. The board will be described in detail below with reference to fig. 6.

As shown in fig. 6, the board (including, for example, a PCB of the present disclosure or a portion of a PCB of the present disclosure) includes a memory device 601 for storing data, which includes one or more memory cells 610. The memory device may be connected and data transferred to and from the control device 602 and the plurality of chips 603 described above by means of, for example, a bus. Further, the board includes an external interface device 604 configured to relay or transfer data between the chip and an external device 605 (e.g., a server or a computer). For example, the data to be processed may be transferred to the chip by an external device through an external interface means. For another example, the calculation result of the chip may be transmitted back to an external device via the external interface device. According to different application scenarios, the external interface device may have different interface forms, for example, it may adopt a standard PCIE interface or the like. In conjunction with the D2D interface scheme of the present disclosure, two chips 603 as shown in fig. 6 may be connected through a D2D interface 505 to each other to achieve die-level interconnection. In one scenario, the D2D interface of chip 603 may also be multiplexed into other types of interfaces (e.g., a storage interface) to enable information interaction with the functional unit 612 shown in the figure (which may be, for example, a memory chip with a storage interface).

In one or more embodiments, the control device in the disclosed card may be configured to regulate the state of the chip. Therefore, in an application scenario, the control device may include a single chip Microcomputer (MCU) for controlling the operating state of the chip.

According to different application scenarios, the electronic device or apparatus of the present disclosure may include a server, a cloud server, a server cluster, a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, a terminal of the internet of things, a mobile terminal, a mobile phone, a vehicle recorder, a navigator, a sensor, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a visual terminal, an autopilot terminal, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph. The electronic device or apparatus of the present disclosure may also be applied to the fields of the internet, the internet of things, data centers, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical, and the like. Further, the electronic device or apparatus disclosed herein may also be used in application scenarios related to artificial intelligence, big data, and/or cloud computing, such as a cloud end, an edge end, and a terminal. In one or more embodiments, a computationally powerful electronic device or apparatus according to the present disclosure may be applied to a cloud device (e.g., a cloud server), while a less power-consuming electronic device or apparatus may be applied to a terminal device and/or an edge-end device (e.g., a smartphone or a camera). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and/or the edge device are compatible with each other, so that appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and/or the edge device according to the hardware information of the terminal device and/or the edge device, and uniform management, scheduling and cooperative work of end-cloud integration or cloud-edge-end integration can be completed.

It is noted that for the sake of brevity, the present disclosure describes some methods and embodiments thereof as a series of acts and combinations thereof, but those skilled in the art will appreciate that the aspects of the present disclosure are not limited by the order of the acts described. Accordingly, one of ordinary skill in the art will appreciate that certain steps may be performed in other sequences or simultaneously, in accordance with the disclosure or teachings of the present disclosure. Further, those skilled in the art will appreciate that the embodiments described in this disclosure are capable of alternative embodiments, in which acts or modules are involved, which are not necessarily required to practice one or more aspects of the disclosure. In addition, the present disclosure may focus on the description of some embodiments, depending on the solution. In view of the above, those skilled in the art will understand that portions of the disclosure that are not described in detail in one embodiment may also be referred to in the description of other embodiments.

In particular implementation, based on the disclosure and teachings of the present disclosure, one of ordinary skill in the art will appreciate that the several embodiments disclosed in the present disclosure may be implemented in other ways not disclosed herein. For example, as for the units in the foregoing embodiments of the electronic device or apparatus, the units are divided based on the logic functions, and there may be other dividing manners in actual implementation. Also for example, multiple units or components may be combined or integrated with another system or some features or functions in a unit or component may be selectively disabled. The connections discussed above in connection with the figures may be direct or indirect couplings between the units or components in terms of connectivity between the different units or components. In some scenarios, the foregoing direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

In the present disclosure, units described as separate parts may or may not be physically separate, and parts shown as units may or may not be physical units. The aforementioned components or units may be co-located or distributed across multiple network elements. In addition, according to actual needs, part or all of the units can be selected to achieve the purpose of the solution of the embodiment of the present disclosure. In addition, in some scenarios, multiple units in embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

In some implementation scenarios, the integrated units may be implemented in the form of software program modules. If implemented in the form of software program modules and sold or used as a stand-alone product, the integrated units may be stored in a computer readable memory. In this regard, when aspects of the present disclosure are embodied in the form of a software product (e.g., a computer-readable storage medium), the software product may be stored in a memory, which may include instructions for causing a computer device (e.g., a personal computer, a server, or a network device, etc.) to perform some or all of the steps of the methods described in embodiments of the present disclosure. The Memory may include, but is not limited to, a usb disk, a flash disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

In other implementation scenarios, the integrated unit may also be implemented in hardware, that is, a specific hardware circuit, which may include a digital circuit and/or an analog circuit, etc. The physical implementation of the hardware structure of the circuit may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors, among other devices. In view of this, the various devices described herein (e.g., computing devices or other processing devices) may be implemented by suitable hardware processors, such as CPUs, GPUs, FPGAs, DSPs, ASICs, and the like. Further, the aforementioned storage unit or storage device may be any suitable storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), and may be, for example, a variable Resistive Memory (RRAM), a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), an Enhanced Dynamic Random Access Memory (EDRAM), a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), a ROM, a RAM, or the like.

While various embodiments of the present disclosure have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that various alternatives to the embodiments of the disclosure described herein may be employed in practicing the disclosure. It is intended that the following claims define the scope of the disclosure and that equivalents or alternatives within the scope of these claims be covered thereby.

The foregoing may be better understood in light of the following clauses:

clause a1, an integrated circuit device, comprising:

a printed circuit board;

a first chip disposed on the printed circuit board and having a die-to-die interface,

a second chip disposed on the printed circuit board,

wherein the first chip is connected with the second chip by a die-to-die interface and via traces of a printed circuit board.

Clause a2, the integrated circuit device of clause a1, wherein the first chip is a system-on-chip and the second chip is a memory chip, and the die-to-die interface is multiplexed as a transport interface connected with the memory chip via traces.

Clause A3, the integrated circuit device of clause a2, wherein the memory chip includes a double data rate synchronous dynamic random access memory and the die-to-die interface is multiplexed as a double data rate interface.

Clause a4, the integrated circuit device of clause a1, wherein the first chip and the second chip are the same type of system-on-a-chip and the second chip has a die-to-die interface, and the first chip and second chip are connected to each other by respective die-to-die interfaces and via traces of a printed circuit board.

Clause a5, the integrated circuit device of clause a1, wherein the first chip has a first general purpose input output interface and the second chip has a second general purpose input output interface, and the first general purpose input output interface and the second general purpose input output interface are connected to each other via traces of a printed circuit board.

Clause a6, the integrated circuit apparatus of clause a5, wherein one of the first and second chips is configured as a master via its gpio interface and the other is configured as a slave via its gpio interface to enable master-slave communication between the first and second chips.

Clause a7, an electronic device, comprising the integrated circuit apparatus of any one of clauses a1-a 6.

Clause A8, a board comprising the integrated circuit device of any one of clauses a1-a 6.

Clause a9, a method of fabricating an integrated circuit device, comprising:

Clause a10, the processing method of clause a9, wherein:

the first chip is a system-on-chip and the second chip is a memory chip, and the die-to-die interface is multiplexed to interface with a transmission interface of the memory chip; or the first chip and the second chip are of the same type of system-on-chip and the second chip has a die-to-die interface and the first chip and the second chip are connected to each other by respective die-to-die interfaces and via traces of a printed circuit board.

It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Claims

1. An integrated circuit device comprising:

A printed circuit board;

a first chip arranged on the printed circuit board and having a die-to-die interface,

a second chip, which is arranged on the printed circuit board,

Wherein the first chip is connected to the second chip through a die-to-die interface and via traces of a printed circuit board.

2. The integrated circuit device of claim 1, wherein the first chip is a system-on-chip and the second chip is a memory chip, and the die-to-die interface is multiplexed via the routing The line is connected to the transmission interface of the memory chip.

3. The integrated circuit device of claim 2, wherein the memory chip comprises a double data rate synchronous dynamic random access memory and the die-to-die interface is multiplexed into a double data rate interface.

4. The integrated circuit device of claim 1, wherein the first chip and the second chip are the same type of system-on-chip, and the second chip has a die-to-die interface, and the The first chip and the second chip are connected to each other by respective die-to-die interfaces and via traces of the printed circuit board.

5. The integrated circuit device of claim 1, wherein the first chip has a first general input output interface and the second chip has a second general input output interface, and the first general input output interface and The second general input output interfaces are connected to each other via traces of the printed circuit board.

6. The integrated circuit device of claim 5, wherein one of the first chip and the second chip is configured as a master device via its general-purpose input output interface and the other is configured as a slave device via its general-purpose input output interface, In order to realize the master-slave communication between the first chip and the second chip.

7. An electronic device comprising an integrated circuit arrangement according to any one of claims 1-6.

8. A board comprising the integrated circuit device according to any one of claims 1-6.

9. A method for processing an integrated circuit device, comprising:

providing a printed circuit board having a first bonding pad and a second bonding pad thereon and the first bonding pad and the second bonding pad being connected via traces of the printed circuit board;

The first die is soldered to the first pad and the second die is soldered to the second pad so that the first die passes through the die-to-die interface and via the printed circuit board A wire is connected to the second chip.

10. The processing method according to claim 9, wherein:

the first chip is a system-on-chip and the second chip is a memory chip, and the die-to-die interface is multiplexed as a transport interface that interfaces with the memory chip via the traces; or

The first chip and the second chip are the same type of system-on-chip, and the second chip has a die-to-die interface, and the first and second chips pass through their respective die-to-die The cores interface and are connected to each other via traces of the printed circuit board.