CN111275197B - Operation method, device, computer equipment and storage medium - Google Patents

Abstract

The present disclosure relates to a computing method, device, computer equipment and storage medium. The combined processing device includes: a machine learning computing device, a universal interconnection interface and other processing devices; the machine learning computing device interacts with other processing devices to jointly complete user-specified computing operations, where the combined processing device also includes: a storage device, The storage device is respectively connected to the machine learning computing device and other processing devices, and is used to save data of the machine learning computing device and other processing devices. The computing methods, devices, computer equipment, and storage media provided by the embodiments of the present disclosure have a wide range of applications, and the computing processing efficiency is high and the processing speed is fast.

Description

Computing methods, devices, computer equipment and storage media

Technical field

The present disclosure relates to the field of computer technology, and in particular, to a scalar type conversion instruction operation method, device, computer equipment and storage medium.

Background technique

With the continuous development of science and technology, the use of machine learning, especially neural network algorithms, is becoming more and more widespread. It has been well used in image recognition, speech recognition, natural language processing and other fields. However, due to the increasing complexity of neural network algorithms, the types and quantities of data operations involved continue to increase. In related technologies, scalar type conversion operations on scalar data are inefficient and slow.

Contents of the invention

In view of this, the present disclosure proposes an operation method, device, computer equipment and storage medium to improve the efficiency and speed of scalar type conversion operations on scalar data.

According to a first aspect of the present disclosure, a scalar type conversion instruction processing device is provided, and the device includes:

A control module, configured to parse the obtained scalar type conversion instruction, obtain the operation code and operation domain of the scalar type conversion instruction, and obtain the operations to be performed required to execute the scalar type conversion instruction according to the operation code and the operation domain. Scalar and target address, and determining the target data type and the initial data type of the scalar to be operated;

An operation module, configured to perform a scalar type conversion operation on the to-be-operated scalar of the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The operation result is The data type is the target data type,

Wherein, the operation code is used to indicate that the operation performed on the data by the scalar type conversion instruction is a scalar type conversion operation, and the operation field includes a scalar address to be operated and the target address.

According to a second aspect of the present disclosure, a machine learning computing device is provided, and the device includes:

One or more scalar type conversion instruction processing devices described in the first aspect, used to obtain scalars to be operated and control information from other processing devices, perform specified machine learning operations, and transfer the execution results through the I/O interface to other processing devices;

When the machine learning computing device includes multiple scalar type conversion instruction processing devices, the multiple scalar type conversion instruction processing devices can be connected and transmit data through a specific structure;

Wherein, multiple scalar type conversion instruction processing devices are interconnected and transmit data through the PCIE bus to support larger-scale machine learning operations; multiple scalar type conversion instruction processing devices share the same The control system may have its own control system; the plurality of scalar type conversion instruction processing devices may share memory or have its own memory; the interconnection method of the plurality of scalar type conversion instruction processing devices may be any interconnection topology.

According to a third aspect of the present disclosure, a combined processing device is provided, the device comprising:

The machine learning computing device, universal interconnection interface and other processing devices described in the second aspect above;

The machine learning computing device interacts with the other processing devices to jointly complete calculation operations specified by the user.

According to a fourth aspect of the present disclosure, a machine learning chip is provided. The machine learning chip includes the machine learning computing device described in the second aspect or the combined processing device described in the third aspect.

According to a fifth aspect of the present disclosure, a machine learning chip packaging structure is provided. The machine learning chip packaging structure includes the machine learning chip described in the fourth aspect.

According to a sixth aspect of the present disclosure, a board card is provided, which includes the machine learning chip packaging structure described in the fifth aspect.

According to a seventh aspect of the present disclosure, an electronic device is provided. The electronic device includes the machine learning chip described in the fourth aspect or the board card described in the sixth aspect.

According to an eighth aspect of the present disclosure, a scalar type conversion instruction processing method is provided. The method is applied to a scalar type conversion instruction processing device. The method includes:

Analyze the obtained scalar type conversion instruction to obtain the operation code and operation domain of the scalar type conversion instruction, and obtain the scalar to be operated and the target address required to execute the scalar type conversion instruction based on the operation code and the operation domain, and determining the target data type and the initial data type of the scalar to be operated;

Perform a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The data type of the operation result is the target data type,

Wherein, the operation code is used to indicate that the operation performed on the data by the scalar type conversion instruction is a scalar type conversion operation, and the operation field includes a scalar address to be operated and the target address.

According to a ninth aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above-mentioned scalar type conversion instruction processing method is implemented.

In some embodiments, the electronic equipment includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, Cameras, projectors, watches, headphones, mobile storage, wearable devices, vehicles, home appliances, and/or medical equipment.

In some embodiments, the means of transportation include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical Equipment includes MRI machines, B-ultrasound machines and/or electrocardiographs.

The embodiments of the present disclosure provide a scalar type conversion instruction processing method, device, computer equipment, and storage medium. The device includes a control module and an operation module. The control module is used to parse the obtained scalar type conversion instruction, obtain the operation code and operation domain of the scalar type conversion instruction, and obtain the scalar to be operated and the target address required to execute the scalar type conversion instruction based on the operation code and operation domain. and determining the target data type and the initial data type of the scalar to be operated on. The operation module is used to perform a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The scalar type conversion instruction processing method, device, computer equipment, and storage medium provided by the embodiments of the present disclosure have a wide range of applications, have high processing efficiency and fast processing speed for scalar type conversion instructions, and have high processing efficiency and fast processing speed for scalar type conversion. high speed.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

FIG. 1 shows a block diagram of a scalar type conversion instruction processing device according to an embodiment of the present disclosure.

2a-2f illustrate a block diagram of a scalar type conversion instruction processing device according to an embodiment of the present disclosure.

FIG. 3 shows a schematic diagram of an application scenario of a scalar type conversion instruction processing device according to an embodiment of the present disclosure.

4a and 4b show a block diagram of a combination processing device according to an embodiment of the present disclosure.

Figure 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure.

FIG. 6 shows a flowchart of a scalar type conversion instruction processing method according to an embodiment of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of this disclosure.

It should be understood that the terms "zero", "first", "second", etc. in the claims, description, and drawings of this disclosure are used to distinguish different objects, rather than describing a specific sequence. The terms "comprise" and "include" used in the description and claims of this disclosure indicate the presence of described features, integers, steps, operations, elements and/or components but do not exclude one or more other features, integers , the presence or addition of steps, operations, elements, components and/or collections thereof.

It should also be understood that the terminology used in the specification of the disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the term "and/or" as used in this specification and the claims refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted as "when" or "once" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, to mean "once determined" or "in response to a determination" or "once the [described condition or event] is detected ]" or "in response to detection of [the described condition or event]".

Due to the widespread use of neural network algorithms and the continuous improvement of computer hardware computing capabilities, the types and quantities of data operations involved in practical applications continue to increase. Due to the various types of programming languages, in order to implement the operation process of scalar operations in different language environments, in related technologies, since there is currently no scalar type conversion instruction that can be widely applied to various programming languages, technicians need to customize the corresponding Multiple instructions in its programming language environment are used to implement scalar type conversion, resulting in low efficiency and slow speed of type conversion. The present disclosure provides a type conversion instruction processing method, device, computer equipment and storage medium, which can realize scalar type conversion with only one instruction, and can significantly improve the efficiency and speed of scalar type conversion.

FIG. 1 shows a block diagram of a scalar type conversion instruction processing device according to an embodiment of the present disclosure. As shown in Figure 1, the device includes a control module 11 and an operation module 12.

The control module 11 is used to parse the obtained scalar type conversion instruction, obtain the operation code and operation domain of the scalar type conversion instruction, and obtain the scalar to be operated and the target required to execute the scalar type conversion instruction according to the operation code and operation domain. address, and determines the target data type and the initial data type of the scalar to be operated on. Among them, the operation code is used to indicate that the operation performed on the data by the scalar type conversion instruction is a scalar type conversion operation, and the operation domain includes the scalar address to be operated and the target address.

The operation module 12 is configured to perform a scalar type conversion operation on the scalar to be operated of the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. Among them, the data type of the operation result is the target data type.

In this embodiment, the control module may obtain the scalar to be operated from the address of the scalar to be operated. The control module can obtain the scalar type conversion instructions and the scalar to be operated through the data input and output unit, which can be one or more data I/O interfaces or I/O pins.

In this embodiment, the operation code can be the part of instructions or fields (usually represented by codes) specified in the computer program to perform the operation. It is the instruction sequence number, which is used to inform the device that executes the instruction which instruction needs to be executed. . The operation domain can be the source of all data required to execute the corresponding instruction. All data required to execute the corresponding instruction include parameter data, scalars to be operated, corresponding operation methods, etc. For a scalar type conversion instruction, it must include an opcode and an operation field, where the operation field at least includes the scalar address to be operated on and the target address.

It should be understood that those skilled in the art can set the instruction format of the scalar type conversion instruction as well as the included operation codes and operation fields as needed, and this disclosure does not limit this.

In this embodiment, the device may include one or more control modules and one or more computing modules. The number of control modules and computing modules may be set according to actual needs, and this disclosure does not limit this. When the device includes a control module, the control module can receive scalar type conversion instructions and control one or more operation modules to perform scalar type conversion operations. When the device includes multiple control modules, the multiple control modules can respectively receive scalar type conversion instructions and control one or more corresponding operation modules to perform scalar type conversion operations.

A scalar type conversion instruction processing device provided by an embodiment of the present disclosure includes a control module and an operation module. The control module is used to parse the obtained scalar type conversion instruction, obtain the operation code and operation domain of the scalar type conversion instruction, and obtain the scalar to be operated and the target address required to execute the scalar type conversion instruction based on the operation code and operation domain. and determining the target data type and the initial data type of the scalar to be operated on. The operation module is used to perform a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The scalar type conversion instruction processing device provided by the embodiments of the present disclosure has a wide application range, has high processing efficiency and fast processing speed for scalar type conversion instructions, and has high processing efficiency and fast processing speed for scalar type conversion.

Figure 2a shows a block diagram of a scalar type conversion instruction processing device according to an embodiment of the present disclosure. In a possible implementation, as shown in Figure 2a, the operation module 12 may include multiple scalar operators 120 for performing scalar type conversion operations.

In this implementation, the operation module may also include a scalar operator. The number of scalar operators can be set according to the size of the data required for the scalar type conversion operation, the processing speed, efficiency and other requirements for the scalar type conversion operation, and this disclosure does not limit this.

Figure 2b shows a block diagram of a scalar type conversion instruction processing device according to an embodiment of the present disclosure. In a possible implementation, as shown in FIG. 2b , the operation module 12 may include a main operation sub-module 121 and a plurality of slave operation sub-modules 122. The main operator module 121 may include multiple scalar operators 120 (not shown in the figure).

The main operation sub-module 121 is used to use multiple scalar operators 120 to perform scalar type conversion operations, obtain operation results, and store the operation results in the target address.

In a possible implementation, the control module 11 is also used to parse the obtained computing instruction, obtain the operation domain and operation code of the computing instruction, and obtain the required data required to execute the computing instruction according to the operation domain and the operation code. Compute data. The operation module 12 is also used to perform operations on the data to be operated according to the calculation instructions to obtain the calculation results of the calculation instructions. Wherein, the operation module may include a plurality of operators, used to perform operations corresponding to the operation type of the calculation instruction.

In this implementation, the calculation instructions can be other instructions that perform arithmetic operations, logical operations, and other operations on data such as scalars, vectors, matrices, tensors, etc. Those skilled in the art can set the calculation instructions according to actual needs. This disclosure provides This is not a limitation.

In this implementation, the arithmetic units may include adders, dividers, multipliers, comparators and other arithmetic units that can perform arithmetic operations, logical operations and other operations on data. The type and number of operators can be set according to the size of the data required for the operation, the type of operation, the processing speed of the data operation, efficiency and other requirements, and this disclosure does not limit this.

In a possible implementation, the control module 11 is also configured to parse the calculation instruction to obtain multiple operation instructions, and send the data to be operated and the multiple operation instructions to the main operation sub-module 121 .

The main operation sub-module 121 is used to perform pre-processing on the data to be operated, and to transmit data and operation instructions with multiple slave operation sub-modules 122.

The slave operation sub-module 122 is configured to perform intermediate operations in parallel according to the data and operation instructions transmitted from the main operation sub-module 121 to obtain multiple intermediate results, and transmit the multiple intermediate results to the main operation sub-module 122 .

The main operation sub-module 121 is also used to perform subsequent processing on multiple intermediate results, obtain the calculation results of the calculation instructions, and store the calculation results in the corresponding address.

In this implementation, when the calculation instruction is an operation performed on scalar or vector data, the device can control the main operation sub-module to use the arithmetic unit therein to perform the operation corresponding to the calculation instruction. When the calculation instruction is to perform operations on data with dimensions greater than or equal to 2, such as matrices and tensors, the device can control the operation sub-module to use the arithmetic unit therein to perform operations corresponding to the calculation instructions.

It should be noted that those skilled in the art can set the connection mode between the main operation sub-module and multiple slave operation sub-modules according to actual needs to achieve the architecture setting of the operation module. For example, the architecture of the operation module can be “H”-shaped architecture, array-shaped architecture, tree-shaped architecture, etc., this disclosure does not limit these.

Figure 2c shows a block diagram of a scalar type conversion instruction processing device according to an embodiment of the present disclosure. In a possible implementation, as shown in Figure 2c, the operation module 12 may also include one or more branch operator sub-modules 123, which are used to forward the main operator sub-module 121 and the slave operator sub-module 123. 122 data and/or operation instructions. Among them, the main operator sub-module 121 is connected to one or more branch operator sub-modules 123. In this way, the main operation sub-module, branch operation sub-module and slave operation sub-module in the operation module are connected using an "H" type architecture. Data and/or operation instructions are forwarded through the branch operation sub-module, saving the need for the main operation sub-module. resource usage, thereby increasing the instruction processing speed.

Figure 2d shows a block diagram of a scalar type conversion instruction processing device according to an embodiment of the present disclosure. In a possible implementation, as shown in Figure 2d, multiple slave operator sub-modules 122 are distributed in an array.

Each slave operator sub-module 122 is connected to other adjacent slave operator sub-modules 122. The main operator sub-module 121 is connected to k slave operator sub-modules 122 in multiple slave operator sub-modules 122. The k slave operator sub-modules 122 are : n slave operator modules 122 in the 1st row, n slave operator modules 122 in the mth row, and m slave operator modules 122 in the 1st column.

Among them, as shown in Figure 2d, the k slave operator sub-modules only include n slave operator sub-modules in the first row, n slave operator sub-modules in the m-th row, and m slave operator sub-modules in the first column, that is, The k slave operator sub-modules are the slave operator sub-modules directly connected to the main operator sub-module among the plurality of slave operator sub-modules. Among them, k slave operator sub-modules are used for forwarding data and instructions between the main operator sub-module and multiple slave operator sub-modules. In this way, multiple slave operation sub-modules are distributed in an array, which can increase the speed at which the main operation sub-module sends data and/or operation instructions to the slave operation sub-modules, thereby increasing the instruction processing speed.

Figure 2e shows a block diagram of a scalar type conversion instruction processing device according to an embodiment of the present disclosure. In a possible implementation, as shown in Figure 2e, the operation module may also include a tree sub-module 124. The tree sub-module 124 includes a root port 401 and multiple branch ports 402 . The root port 401 is connected to the main operator sub-module 121, and the plurality of branch ports 402 is connected to the plurality of slave operator sub-modules 122 respectively. Among them, the tree sub-module 124 has a transceiver function and is used to forward data and/or operation instructions between the main operation sub-module 121 and the slave operation sub-module 122. In this way, the operation modules are connected in a tree structure through the function of the tree sub-module, and the forwarding function of the tree sub-module can be used to increase the speed at which the main operation sub-module sends data and/or operation instructions to the slave operation sub-modules, thereby improving The processing speed of instructions.

In a possible implementation, the tree sub-module 124 may be an optional result of the device, and may include at least one layer of nodes. The node is a line structure with forwarding function, and the node itself does not have computing function. The lowest node is connected to the slave operator sub-module to forward data and/or operation instructions between the main operator sub-module 121 and the slave operator sub-module 122 . Specifically, if the tree sub-module has zero-level nodes, the device does not require the tree sub-module.

In a possible implementation, the tree sub-module 124 may include multiple nodes of an n-ary tree structure, and the multiple nodes of the n-ary tree structure may have multiple layers.

For example, FIG. 2f shows a block diagram of a scalar type conversion instruction processing device according to an embodiment of the present disclosure. As shown in Figure 2f, the n-ary tree structure can be a binary tree structure, and the tree sub-module includes 2-layer node 01. The lowest node 01 is connected to the slave operator module 122 to forward data and/or operation instructions between the master operator module 121 and the slave operator module 122 .

In this implementation, the n-ary tree structure may also be a ternary tree structure, etc., and n is a positive integer greater than or equal to 2. Those skilled in the art can set n in the n-ary tree structure and the number of layers of nodes in the n-ary tree structure as needed, and this disclosure does not limit this.

In a possible implementation, the operation domain may also include an initial data type and a target data type. The control module 11 is also used to determine the target data type and the initial data type of the scalar to be operated according to the operation domain.

In one possible implementation, the opcode can also be used to indicate the initial data type and the target data type. The control module 11 is also used to determine the target data type and the initial data type of the scalar to be operated according to the operation code.

In a possible implementation, when the initial data type and/or target data type cannot be determined based on the operation code or operation domain, the initial data type and/or target data type can be determined based on the preset default initial data type and default target data type. or target data type. The preset default initial data type may be determined as the current initial data type of the scalar type conversion instruction, and the preset default target data type may be determined as the current target data type of the scalar type conversion instruction. Those skilled in the art can set the determination method of the target data type and the initial data type according to actual needs, and this disclosure does not limit this.

In a possible implementation, the target data type can include any one of 16-bit floating point numbers, 32-bit floating point numbers, 48-bit floating point numbers, 16-bit integers, 32-bit integers, and 48-bit integers, and the initial data type can Including any one of 16-bit signed number, 32-bit signed number, 48-bit signed number, 16-bit unsigned number, 32-bit unsigned number, 48-bit unsigned number and pointer data type.

In this implementation, the target data type and the initial data type can also be data types such as 64-bit integers. Those skilled in the art can set the target data type and the initial data type according to actual needs, as long as the target data type is consistent with the initial data type. The data types indicated by the data types only need to be different, and this disclosure does not limit this.

In this implementation, the numbers, names and other identifiers (or codes) of the above-mentioned target data type and initial data type can be set to determine the target indicated by the scalar type conversion instruction based on the identifiers (or codes) in the scalar conversion instruction. Data types and initial data types. For example, you can set the flag of 16-bit floating point numbers to cvtf16, the flag of 32-bit floating point numbers to cvtf32, the flag of 48-bit floating point numbers to cvtf48, the flag of 16-bit integers to cvti16, and the flag of 32-bit integers to cvti32 and sets the identity of the 48-bit integer to cvti48. You can set the identity of the 16-bit signed number to s16, the identity of the 32-bit signed number to s32, the identity of the 48-bit signed number to s48, the identity of the 16-bit unsigned number to u16, and the 32-bit unsigned number. The identifier of the number is set to u32, the identifier of the 48-bit unsigned number is set to u48 and the identifier of the pointer data type is set to ptr. Those skilled in the art can set the identification of the target data type and the initial data type according to actual needs, and this disclosure does not limit this.

In a possible implementation, as shown in Figures 2a-2f, the device may also include a storage module 13. The storage module 13 is used to store scalars to be operated.

In this implementation, the storage module may include one or more of a cache and a register. The cache may include a scratch cache, and may also include at least one NRAM (Neuron Random Access Memory). Cache can be used to store data to be operated on, and registers can be used to store scalars to be operated on.

In one possible implementation, the cache may include a neuron cache. The neuron cache, also known as the neuron random access memory, can be used to store neuron data in the data to be operated, and the neuron data can include neuron vector data. The data to be operated on includes data related to scalar type conversion and/or data related to the operation of other calculation instructions.

In a possible implementation, the device may also include a direct memory access module for reading or storing data from the storage module.

In a possible implementation, as shown in Figures 2a-2f, the control module 11 may include an instruction storage sub-module 111, an instruction processing sub-module 112 and a queue storage sub-module 113.

The instruction storage submodule 111 is used to store scalar type conversion instructions.

The instruction processing sub-module 112 is used to parse the scalar type conversion instruction and obtain the operation code and operation domain of the scalar type conversion instruction.

The queue storage submodule 113 is used to store an instruction queue. The instruction queue includes multiple instructions to be executed that are arranged in sequence according to execution order. The multiple instructions to be executed may include scalar type conversion instructions.

In this implementation, the instructions to be executed may also include calculation instructions that are somewhat related or unrelated to the scalar type conversion instructions. Those skilled in the art can set them according to actual needs, and this disclosure does not limit this. The execution sequence of multiple to-be-executed instructions can be arranged according to the reception time, priority level, etc. of the to-be-executed instructions to obtain an instruction queue, so that the multiple to-be-executed instructions can be executed sequentially according to the instruction queue.

In a possible implementation, as shown in Figures 2a-2f, the control module 11 may include a dependency processing sub-module 114.

Dependency processing sub-module 114, configured to cache the first instruction to be executed in the instruction when it is determined that the first instruction to be executed among the instructions to be executed is associated with the zeroth instruction to be executed before the first instruction to be executed. In the storage sub-module 111, after the execution of the zeroth instruction to be executed is completed, the first instruction to be executed is extracted from the instruction storage sub-module 111 and sent to the computing module 12. Wherein, the first instruction to be executed and the zeroth instruction to be executed are instructions among multiple instructions to be executed.

Wherein, the correlation between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes: the first storage address interval for storing the data required for the first instruction to be executed and the data required for storing the zeroth instruction to be executed. The zeroth storage address interval of has overlapping areas. On the contrary, the lack of correlation between the first instruction to be executed and the zeroth instruction to be executed may mean that there is no overlapping area between the first storage address interval and the zeroth storage address interval.

In this way, according to the dependency relationship between the instructions to be executed, after the previous instructions to be executed are executed, the subsequent instructions to be executed can be executed to ensure the accuracy of the operation results.

In a possible implementation, the instruction format of the scalar type conversion instruction can be:

scalar dst src0 opcode.type

Among them, scalar is the opcode of the scalar type conversion instruction, and dst, src0, and opcode.type are the operation fields of the scalar type conversion instruction. Among them, dst is the destination address. src0 is the scalar address to be operated on. The opcode in opcode.type is the target data type, and the type in opcode.type is the initial data type of the scalar to be operated on.

In a possible implementation, the instruction format of the scalar type conversion instruction can also be:

opcode.scalar.type dstsrc0

Among them, opcode.scalar.type is the opcode of the scalar type conversion instruction, and dst and src0 are the operation fields of the scalar type conversion instruction. Among them, opcode in opcode.scalar.type is used to indicate the target data type, type in opcode.scalar.type is used to indicate the initial data type of the scalar to be operated, and scalar in opcode.scalar.type is used to indicate that the instruction is Scalar type conversion instructions. dst is the target address, and src0 is the scalar address to be operated on.

It should be understood that those skilled in the art can set the operation code of the scalar type conversion instruction, the position of the operation code and the operation field in the instruction format as needed, and this disclosure does not limit this.

In a possible implementation, the device can be provided in a graphics processor (Graphics Processing Unit, referred to as GPU), a central processing unit (Central Processing Unit, referred to as CPU), and an embedded neural network processor (Neural-network Processing Unit, (referred to as NPU) one or more.

It should be noted that although the above embodiment is used as an example to introduce the scalar type conversion instruction processing device, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, users can flexibly set each module according to personal preferences and/or actual application scenarios, as long as they comply with the technical solution of the present disclosure.

Application examples

In the following, in conjunction with "Using a scalar type conversion instruction processing device to perform scalar type conversion operations" as an exemplary application scenario, application examples according to embodiments of the present disclosure are given to facilitate understanding of the flow of the scalar type conversion instruction processing device. Those skilled in the art should understand that the following application examples are only for the purpose of facilitating understanding of the embodiments of the present disclosure and should not be regarded as limiting the embodiments of the present disclosure.

FIG. 3 shows a schematic diagram of an application scenario of a scalar type conversion instruction processing device according to an embodiment of the present disclosure. As shown in Figure 3, the process of the scalar type conversion instruction processing device processing the scalar type conversion instruction is as follows:

The control module 11 analyzes the obtained scalar type conversion instruction 1 (for example, the scalar type conversion instruction 1 is scalar 500100 cvtf16.u32), and obtains the operation code and operation domain of the scalar type conversion instruction 1. Among them, the opcode of scalar type conversion instruction 1 is scalar, the target address is 500, the address of the scalar to be operated is 100, the target data type is cvtf16 (that is, 16 is a floating point number), and the initial data type of the scalar to be operated is u32 (also That is, a 32-bit unsigned number). The control module 11 obtains the scalar to be operated from the address 100 of the scalar to be operated.

The operation module 12 performs a scalar type conversion operation on the scalar to be operated of the initial data type according to the target data type (that is, converts the data type of the 32-bit unsigned scalar to be operated into a 16-bit floating point number), obtains the operation result, and performs the operation The result is stored in target address 500.

For the working process of each of the above modules, please refer to the relevant descriptions above.

In this way, the scalar type conversion instruction processing device can process the scalar type conversion instruction efficiently and quickly, and the processing efficiency of the scalar type conversion is high and the processing speed is fast.

The present disclosure provides a machine learning operation device. The machine learning operation device may include one or more of the above-mentioned scalar type conversion instruction processing devices, used to obtain scalars to be operated and control information from other processing devices, and perform specified machine learning operations. . The machine learning computing device can obtain scalar type conversion instructions from other machine learning computing devices or non-machine learning computing devices, and transfer the execution results to peripheral devices (also called other processing devices) through the I/O interface. Peripheral devices such as cameras, monitors, mice, keyboards, network cards, wifi interfaces, and servers. When more than one scalar type conversion instruction processing device is included, the scalar type conversion instruction processing devices can be linked and transmit data through a specific structure, such as interconnection and data transmission through the PCIE bus to support larger-scale neural networks. Operation. At this time, the same control system can be shared, or there can be independent control systems; the memory can be shared, or each accelerator can have its own memory. In addition, its interconnection method can be any interconnection topology.

The machine learning computing device has high compatibility and can be connected to various types of servers through the PCIE interface.

Figure 4a shows a block diagram of a combined processing device according to an embodiment of the present disclosure. As shown in Figure 4a, the combined processing device includes the above-mentioned machine learning computing device, a universal interconnection interface and other processing devices. The machine learning computing device interacts with other processing devices to jointly complete user-specified operations.

Other processing devices include one or more processor types among general/special-purpose processors such as central processing units (CPUs), graphics processors (GPUs), and neural network processors. There is no limit on the number of processors included in other processing devices. Other processing devices serve as the interface between the machine learning computing device and external data and control, including data transfer, to complete basic control such as starting and stopping the machine learning computing device; other processing devices can also cooperate with the machine learning computing device to complete computing tasks.

A universal interconnect interface used to transmit data and control instructions between machine learning computing devices and other processing devices. The machine learning computing device obtains the required input data from other processing devices and writes them into the on-chip storage device of the machine learning computing device; it can obtain control instructions from other processing devices and write them into the on-chip control cache of the machine learning computing device; also Data in the storage module of the machine learning computing device can be read and transmitted to other processing devices.

Figure 4b shows a block diagram of a combined processing device according to an embodiment of the present disclosure. In a possible implementation, as shown in Figure 4b, the combined processing device may also include a storage device, and the storage device is connected to the machine learning computing device and the other processing devices respectively. The storage device is used to store data in the machine learning arithmetic device and the other processing devices, and is particularly suitable for data requiring calculations that cannot be fully stored in the internal storage of the machine learning arithmetic device or other processing devices.

This combined processing device can be used as a SOC system-on-chip for mobile phones, robots, drones, video surveillance equipment and other equipment, effectively reducing the core area of the control part, increasing processing speed, and reducing overall power consumption. In this case, the universal interconnection interface of the combined processing device is connected to certain components of the device. Certain components such as cameras, monitors, mice, keyboards, network cards, and wifi interfaces.

The present disclosure provides a machine learning chip, which includes the above machine learning computing device or combined processing device.

The present disclosure provides a machine learning chip packaging structure, which includes the above machine learning chip.

The present disclosure provides a board card, and FIG. 5 shows a schematic structural diagram of the board card according to an embodiment of the present disclosure. As shown in Figure 5, the board card includes the above-mentioned machine learning chip packaging structure or the above-mentioned machine learning chip. In addition to the machine learning chip 389 , the board card may also include other supporting components, including but not limited to: a storage device 390 , an interface device 391 and a control device 392 .

The storage device 390 is connected to the machine learning chip 389 (or the machine learning chip within the machine learning chip package structure) through a bus for storing data. Memory device 390 may include multiple sets of memory cells 393 . Each group of storage units 393 is connected to the machine learning chip 389 through a bus. It can be understood that each group of storage units 393 can be DDR SDRAM (English: Double Data Rate SDRAM, double rate synchronous dynamic random access memory).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

In one embodiment, memory device 390 may include four sets of memory cells 393. Each group of memory cells 393 may include multiple DDR4 particles (chips). In one embodiment, the machine learning chip 389 may include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of storage units 393, the theoretical bandwidth of data transmission can reach 25600MB/s.

In one embodiment, each group of memory cells 393 includes a plurality of double-rate synchronous dynamic random access memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling DDR is provided in the machine learning chip 389 for controlling data transmission and data storage of each storage unit 393 .

The interface device 391 is electrically connected to the machine learning chip 389 (or the machine learning chip within the machine learning chip package structure). The interface device 391 is used to implement data transmission between the machine learning chip 389 and external devices (such as servers or computers). For example, in one embodiment, the interface device 391 may be a standard PCIE interface. For example, the data to be processed is transferred from the server to the machine learning chip 289 through the standard PCIE interface to realize data transfer. Preferably, when using the PCIE 3.0X 16 interface for transmission, the theoretical bandwidth can reach 16000MB/s. In another embodiment, the interface device 391 can also be other interfaces. This disclosure does not limit the specific expression forms of the above-mentioned other interfaces, as long as the interface device can realize the switching function. In addition, the calculation results of the machine learning chip are still sent back to the external device (such as a server) through the interface device.

The control device 392 is electrically connected to the machine learning chip 389. The control device 392 is used to monitor the status of the machine learning chip 389. Specifically, the machine learning chip 389 and the control device 392 can be electrically connected through an SPI interface. The control device 392 may include a Micro Controller Unit (MCU). For example, the machine learning chip 389 may include multiple processing chips, multiple processing cores, or multiple processing circuits, and may drive multiple loads. Therefore, the machine learning chip 389 can be in different working states such as multi-load and light load. The control device can control the working status of multiple processing chips, multiple processes and/or multiple processing circuits in the machine learning chip.

The present disclosure provides an electronic device, which includes the above machine learning chip or board.

Electronic equipment may include data processing devices, computer equipment, robots, computers, printers, scanners, tablets, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, video cameras, projectors , watches, headphones, mobile storage, wearable devices, transportation, home appliances, and/or medical equipment.

Transportation may include aircraft, ships, and/or vehicles. Household appliances can include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods. Medical equipment may include MRI machines, B-ultrasound machines, and/or electrocardiographs.

FIG. 6 shows a flowchart of a scalar type conversion instruction processing method according to an embodiment of the present disclosure. This method can be applied to computer equipment including a memory and a processor, where the memory is used to store data used in executing the method; the processor is used to perform related processing and operation steps, such as performing the following steps S51 and S52. As shown in Figure 6, this method is applied to the above-mentioned scalar type conversion instruction processing device, and the method includes step S51 and step S52.

In step S51, the control module is used to parse the obtained scalar type conversion instruction to obtain the operation code and operation domain of the scalar type conversion instruction, and obtain the scalar to be operated required to execute the scalar type conversion instruction according to the operation code and operation domain. and the destination address, as well as determining the destination data type and the initial data type of the scalar to be operated on. Among them, the operation code is used to indicate that the operation performed on the data by the scalar type conversion instruction is a scalar type conversion operation, and the operation domain includes the scalar address to be operated and the target address.

In step S52, the operation module is used to perform a scalar type conversion operation on the scalar to be operated of the initial data type according to the target data type to obtain the operation result, and the operation result is stored in the target address. The data type of the operation result is the target data type.

In one possible implementation, a scalar type conversion operation is performed on the scalar of the initial data type to be operated on according to the target data type, which may include:

Use multiple scalar operators in the operation module to perform scalar type conversion operations.

In a possible implementation manner, the operation module includes a main operation sub-module and multiple slave operation sub-modules, and the main operation sub-module includes multiple scalar operators. Among them, step S52 may include:

Use multiple scalar operators in the main operation submodule to perform scalar type conversion operations, obtain the operation results, and store the operation results in the target address.

In a possible implementation, the operation domain may also include an initial data type and a target data type, and step S51 may include: determining the target data type and the initial data type of the scalar to be operated according to the operation domain.

In a possible implementation, the operation code is also used to indicate the initial data type and the target data type. Step S51 may include: determining the target data type and the initial data type of the scalar to be operated according to the operation code.

In a possible implementation, the target data type can include any one of 16-bit floating point numbers, 32-bit floating point numbers, 48-bit floating point numbers, 16-bit integers, 32-bit integers, and 48-bit integers, and the initial data type can Including any one of 16-bit signed number, 32-bit signed number, 48-bit signed number, 16-bit unsigned number, 32-bit unsigned number, 48-bit unsigned number and pointer data type.

In a possible implementation, the method may also include: using a storage module of the device to store the scalar to be calculated,

Wherein, the storage module includes at least one of a register and a cache,

The cache is used to store data to be calculated. The cache includes at least one neuron cache NRAM;

Register, used to store scalars to be operated on;

Neuron cache is used to store neuron data in the data to be operated. Neuron data includes neuron vector data.

In a possible implementation, step S51 may include:

Storage scalar type conversion instructions;

Analyze the scalar type conversion instruction to obtain the operation code and operation domain of the scalar type conversion instruction;

The instruction queue is stored. The instruction queue includes multiple instructions to be executed that are arranged in order of execution. The multiple instructions to be executed may include scalar type conversion instructions.

In a possible implementation, the method may also include:

When it is determined that the first instruction to be executed among the plurality of instructions to be executed is associated with the zeroth instruction to be executed before the first instruction to be executed, the first instruction to be executed is cached, and after it is determined that the execution of the zeroth instruction to be executed is completed , control the execution of the first instruction to be executed,

Among them, the relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes:

The first storage address interval that stores the data required by the first instruction to be executed has an overlapping area with the zeroth storage address interval that stores the data required by the zeroth instruction to be executed.

It should be noted that although the above embodiment is used as an example to introduce the scalar type conversion instruction processing method as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, users can flexibly set each step according to personal preferences and/or actual application scenarios, as long as they comply with the technical solution of the present disclosure.

The scalar type conversion instruction processing method provided by the embodiments of the present disclosure has a wide range of application, has high processing efficiency and fast processing speed for scalar type conversion instructions, and has high processing efficiency and fast processing speed for scalar type conversion.

The present disclosure also provides a non-volatile computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above-mentioned scalar type conversion instruction processing method is implemented.

It should be noted that for the sake of simple description, the foregoing method embodiments are expressed as a series of action combinations. However, those skilled in the art should know that the present disclosure is not limited by the described action sequence. Because certain steps may be performed in other orders or concurrently in accordance with this disclosure. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily necessary for this disclosure.

It should be further noted that although each step in the flowchart of FIG. 6 is shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figure 6 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution of these sub-steps or stages The sequence is not necessarily sequential, but may be performed in turn or alternately with other steps or sub-steps of other steps or at least part of the stages.

It should be understood that the above device embodiments are only illustrative, and the device of the present disclosure can also be implemented in other ways. For example, the division of units/modules in the above embodiments is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units, modules or components may be combined, or may be integrated into another system, or some features may be omitted or not performed.

In addition, unless otherwise specified, each functional unit/module in each embodiment of the present disclosure may be integrated into one unit/module, or each unit/module may exist physically alone, or there may be two or more units/modules. Modules are integrated together. The above integrated units/modules can be implemented in the form of hardware or software program modules.

If the integrated unit/module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of hardware structures includes but is not limited to transistors, memristors, etc. Unless otherwise specified, the above-mentioned storage module can be any appropriate magnetic storage medium or magneto-optical storage medium, such as resistive random access memory RRAM (Resistive Random Access Memory), dynamic random access memory DRAM (Dynamic Random Access Memory). Memory), static random access memory SRAM (Static Random-Access Memory), enhanced dynamic random access memory EDRAM (Enhanced Dynamic Random Access Memory), high-bandwidth memory HBM (High-Bandwidth Memory), hybrid memory cube HMC (Hybrid Memory Cube) and so on.

The integrated unit/module, if implemented in the form of a software program module and sold or used as an independent product, may be stored in a computer-readable memory. Based on this understanding, the technical solution of the present disclosure is essentially or contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, It includes several instructions to cause a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present disclosure. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

In the above embodiments, each embodiment is described with its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, all possible combinations should be used. It is considered to be within the scope of this manual.

The foregoing content can be better understood according to the following terms:

Clause A1, a scalar type conversion instruction processing device, the device includes:

A control module, configured to parse the obtained scalar type conversion instruction, obtain the operation code and operation domain of the scalar type conversion instruction, and obtain the operations to be performed required to execute the scalar type conversion instruction according to the operation code and the operation domain. Scalar and target address, and determining the target data type and the initial data type of the scalar to be operated;

An operation module, configured to perform a scalar type conversion operation on the to-be-operated scalar of the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The operation result is The data type is the target data type,

Wherein, the operation code is used to indicate that the operation performed on the data by the scalar type conversion instruction is a scalar type conversion operation, and the operation field includes a scalar address to be operated and the target address.

Clause A2. The device according to Clause A1, the computing module includes:

A plurality of scalar operators used to perform the scalar type conversion operation.

Clause A3. The device according to Clause A2, the operation module includes a main operator sub-module and a plurality of slave operator sub-modules, the main operator sub-module includes the plurality of scalar operators,

The main operation submodule is configured to use the plurality of scalar operators to perform the scalar type conversion operation, obtain an operation result, and store the operation result in the target address.

Clause A4. The device according to Clause A1, the operation domain also includes an initial data type and a target data type,

Wherein, the control module is further configured to determine the target data type and the initial data type of the scalar to be operated according to the operation domain.

Clause A5. The device according to Clause A1, wherein the operation code is further used to indicate the initial data type and the target data type,

Wherein, the control module is further configured to determine the target data type and the initial data type of the scalar to be operated according to the operation code.

Clause A6. The device according to clause A1, the target data type includes any one of 16-bit floating point number, 32-bit floating point number, 48-bit floating point number, 16-bit integer, 32-bit integer and 48-bit integer, so The initial data types include any one of 16-bit signed numbers, 32-bit signed numbers, 48-bit signed numbers, 16-bit unsigned numbers, 32-bit unsigned numbers, 48-bit unsigned numbers, and pointer data types.

Clause A7. The device according to Clause A1, the device further comprising:

Storage module, used to store the scalar to be calculated,

Wherein, the storage module includes at least one of a register and a cache,

The cache is used to store the data to be calculated, and the cache includes at least one neuron cache NRAM;

The register is used to store the scalar to be operated;

The neuron cache is used to store neuron data in the data to be operated, where the neuron data includes neuron vector data.

Clause A8. The device according to Clause A1, the control module includes:

Instruction storage submodule, used to store the scalar type conversion instructions;

The instruction processing submodule is used to parse the scalar type conversion instruction and obtain the operation code and operation domain of the scalar type conversion instruction;

The queue storage submodule is used to store an instruction queue, where the instruction queue includes a plurality of instructions to be executed that are arranged in sequence according to execution order, and the plurality of instructions to be executed include the scalar type conversion instruction.

Clause A9. The device according to Clause A8, the control module further includes:

Dependency processing submodule, configured to: when it is determined that the first instruction to be executed among the plurality of instructions to be executed is associated with the zeroth instruction to be executed before the first instruction to be executed, the first instruction to be executed is Execution instructions are cached in the instruction storage sub-module. After the execution of the zeroth instruction to be executed is completed, the first instruction to be executed is extracted from the instruction storage sub-module and sent to the operation module,

Wherein, the correlation between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes:

The first storage address interval that stores the data required by the first instruction to be executed has an overlapping area with the zeroth storage address interval that stores the data required by the zeroth instruction to be executed.

Clause A10. A machine learning computing device, the device comprising:

One or more scalar type conversion instruction processing devices as described in any one of Clause A1 to Clause A9, used to obtain scalars and control information to be operated from other processing devices, and perform specified machine learning operations, and pass the execution results through The I/O interface is passed to other processing devices;

When the machine learning computing device includes multiple scalar type conversion instruction processing devices, the multiple scalar type conversion instruction processing devices can be connected and transmit data through a specific structure;

Wherein, multiple scalar type conversion instruction processing devices are interconnected and transmit data through the PCIE bus to support larger-scale machine learning operations; multiple scalar type conversion instruction processing devices share the same The control system may have its own control system; the plurality of scalar type conversion instruction processing devices may share memory or have its own memory; the interconnection method of the plurality of scalar type conversion instruction processing devices may be any interconnection topology.

Clause A11, a combined processing device, the combined processing device includes:

Machine learning computing devices, universal interconnect interfaces and other processing devices as described in Clause A10;

The machine learning computing device interacts with the other processing devices to jointly complete the calculation operations specified by the user,

Wherein, the combined processing device further includes: a storage device, which is connected to the machine learning computing device and the other processing devices respectively, and is used to save data of the machine learning computing device and the other processing devices.

Clause A12, a machine learning chip, the machine learning chip includes:

A machine learning computing device as described in clause A10 or a combined processing device as described in clause A11.

Clause A13, an electronic device, the electronic device includes:

Machine learning chips as described in Clause A12.

Clause A14, a board card, the board card includes: a storage device, an interface device and a control device, and a machine learning chip as described in Clause A12;

Wherein, the machine learning chip is connected to the storage device, the control device and the interface device respectively;

The storage device is used to store data;

The interface device is used to realize data transmission between the machine learning chip and external equipment;

The control device is used to monitor the status of the machine learning chip.

Clause A15. A method for processing scalar type conversion instructions. The method is applied to a scalar type conversion instruction processing device. The device includes a control module and an operation module. The method includes:

Use the control module to parse the obtained scalar type conversion instruction to obtain the operation code and operation domain of the scalar type conversion instruction, and obtain the scalar sum to be operated required to execute the scalar type conversion instruction based on the operation code and the operation domain. The target address, and determine the target data type and the initial data type of the scalar to be operated;

Utilize the operation module to perform a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The data type of the operation result for the target data type,

Wherein, the operation code is used to indicate that the operation performed on the data by the scalar type conversion instruction is a scalar type conversion operation, and the operation field includes a scalar address to be operated and the target address.

Clause A16. According to the method described in clause A15, performing a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, including:

The scalar type conversion operation is performed using multiple scalar operators in the operation module.

Clause A17. The method according to Clause A16, the operation module includes a main operator sub-module and a plurality of slave operator sub-modules, the main operator sub-module includes the plurality of scalar operators,

Wherein, performing a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtaining the operation result, and storing the operation result in the target address, including:

Multiple scalar operators in the main operation sub-module are used to perform the scalar type conversion operation to obtain an operation result, and the operation result is stored in the target address.

Clause A18. According to the method described in Clause A15, the operation domain also includes an initial data type and a target data type,

Among them, determining the target data type and the initial data type of the scalar to be operated includes:

The target data type and the initial data type of the scalar to be operated are determined according to the operation domain.

Clause A19. A method according to Clause A15, said opcode further indicating an initial data type and a target data type,

Among them, determining the target data type and the initial data type of the scalar to be operated includes:

The target data type and the initial data type of the scalar to be operated are determined according to the operation code.

Clause A20. According to the method described in clause A15, the target data type includes any one of 16-bit floating point number, 32-bit floating point number, 48-bit floating point number, 16-bit integer, 32-bit integer and 48-bit integer, so The initial data types include any one of 16-bit signed numbers, 32-bit signed numbers, 48-bit signed numbers, 16-bit unsigned numbers, 32-bit unsigned numbers, 48-bit unsigned numbers, and pointer data types.

Clause A21. Method according to Clause A16, said method further comprising:

Utilize the storage module of the device to store the scalar to be calculated,

Wherein, the storage module includes at least one of a register and a cache,

The cache is used to store the data to be calculated, and the cache includes at least one neuron cache NRAM;

The register is used to store the scalar to be operated;

The neuron cache is used to store neuron data in the data to be operated, where the neuron data includes neuron vector data.

Clause A22. According to the method described in Clause A15, the scalar type conversion instruction is parsed to obtain the operation code and operation domain of the scalar type conversion instruction, including:

store the scalar type conversion instruction;

Analyze the scalar type conversion instruction to obtain the operation code and operation domain of the scalar type conversion instruction;

An instruction queue is stored, and the instruction queue includes a plurality of instructions to be executed sequentially arranged in an execution order, and the plurality of instructions to be executed include the scalar type conversion instruction.

Clause A23. A method according to clause A22, further comprising:

When it is determined that the first instruction to be executed among the plurality of instructions to be executed is associated with the zeroth instruction to be executed before the first instruction to be executed, the first instruction to be executed is cached, and when it is determined that the first instruction to be executed is After the execution of the zeroth instruction to be executed is completed, the execution of the first instruction to be executed is controlled,

Wherein, the correlation between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes:

The first storage address interval that stores the data required by the first instruction to be executed has an overlapping area with the zeroth storage address interval that stores the data required by the zeroth instruction to be executed.

Clause A24. A non-volatile computer-readable storage medium having computer program instructions stored thereon, which when executed by a processor implements the method described in any one of clauses A15 to A23.

The embodiments of the present application have been introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and the core idea of the present application; at the same time, for Those of ordinary skill in the art will have changes in the specific implementation and application scope based on the ideas of the present application. In summary, the content of this description should not be understood as a limitation of the present application.

Claims (22)

1. A scalar type conversion instruction processing device, characterized in that the device includes: A control module, configured to parse the obtained scalar type conversion instruction, obtain the operation code and operation domain of the scalar type conversion instruction, and obtain the operations to be performed required to execute the scalar type conversion instruction according to the operation code and the operation domain. Scalar and target address, and determining the target data type and the initial data type of the scalar to be operated; An operation module, configured to perform a scalar type conversion operation on the to-be-operated scalar of the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The operation result is The data type is the target data type, Wherein, the operation code is used to indicate that the operation performed on the data by the scalar type conversion instruction is a scalar type conversion operation, and the operation field includes the scalar address to be operated and the target address; Wherein, the control module includes: Instruction storage submodule, used to store the scalar type conversion instructions; The instruction processing submodule is used to parse the scalar type conversion instruction and obtain the operation code and operation domain of the scalar type conversion instruction; The queue storage submodule is used to store an instruction queue, where the instruction queue includes a plurality of instructions to be executed that are arranged in sequence according to execution order, and the plurality of instructions to be executed include the scalar type conversion instruction. 2. The device according to claim 1, characterized in that the computing module includes: A plurality of scalar operators used to perform the scalar type conversion operation. 3. The device according to claim 2, wherein the operation module includes a main operation sub-module and a plurality of slave operation sub-modules, and the main operation sub-module includes the plurality of scalar operators, The main operation submodule is configured to use the plurality of scalar operators to perform the scalar type conversion operation, obtain an operation result, and store the operation result in the target address. 4. The device according to claim 1, wherein the operation domain further includes an initial data type and a target data type, Wherein, the control module is further configured to determine the target data type and the initial data type of the scalar to be operated according to the operation domain. 5. The device according to claim 1, wherein the operation code is also used to indicate an initial data type and a target data type, Wherein, the control module is further configured to determine the target data type and the initial data type of the scalar to be operated according to the operation code. 6. The device according to claim 1, wherein the target data type includes any of 16-bit floating point numbers, 32-bit floating point numbers, 48-bit floating point numbers, 16-bit integers, 32-bit integers and 48-bit integers. One, the initial data type includes 16-bit signed number, 32-bit signed number, 48-bit signed number, 16-bit unsigned number, 32-bit unsigned number, 48-bit unsigned number and pointer data type. Any kind. 7. The device of claim 1, further comprising: Storage module, used to store the scalar to be calculated, Wherein, the storage module includes at least one of a register and a cache, The cache is used to store data to be calculated, and the cache includes at least one neuron cache NRAM; The register is used to store the scalar to be operated; The neuron cache is used to store neuron data in the data to be operated, where the neuron data includes neuron vector data. 8. The device according to claim 1, wherein the control module further includes: Dependency processing submodule, configured to: when it is determined that the first instruction to be executed among the plurality of instructions to be executed is associated with the zeroth instruction to be executed before the first instruction to be executed, the first instruction to be executed is Execution instructions are cached in the instruction storage sub-module. After the execution of the zeroth instruction to be executed is completed, the first instruction to be executed is extracted from the instruction storage sub-module and sent to the operation module, Wherein, the correlation between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes: The first storage address interval that stores the data required by the first instruction to be executed has an overlapping area with the zeroth storage address interval that stores the data required by the zeroth instruction to be executed. 9. A machine learning computing device, characterized in that the device includes: One or more scalar type conversion instruction processing devices as claimed in any one of claims 1 to 8, used to obtain scalars and control information to be operated from other processing devices, and perform specified machine learning operations, and pass the execution results through The I/O interface is passed to other processing devices; When the machine learning computing device includes multiple scalar type conversion instruction processing devices, the multiple scalar type conversion instruction processing devices can be connected and transmit data through a specific structure; Wherein, multiple scalar type conversion instruction processing devices are interconnected and transmit data through the PCIE bus to support larger-scale machine learning operations; multiple scalar type conversion instruction processing devices share the same The control system may have its own control system; the plurality of scalar type conversion instruction processing devices may share memory or have its own memory; the interconnection method of the plurality of scalar type conversion instruction processing devices may be any interconnection topology. 10. A combined processing device, characterized in that the combined processing device includes: The machine learning computing device, universal interconnection interface and other processing devices as claimed in claim 9; The machine learning computing device interacts with the other processing devices to jointly complete the calculation operations specified by the user, Wherein, the combined processing device further includes: a storage device, which is connected to the machine learning computing device and the other processing devices respectively, and is used to save data of the machine learning computing device and the other processing devices. 11. A machine learning chip, characterized in that the machine learning chip includes: The machine learning computing device according to claim 9 or the combined processing device according to claim 10. 12. An electronic device, characterized in that the electronic device includes: The machine learning chip according to claim 11. 13. A board card, characterized in that the board card includes: a storage device, an interface device and a control device, and the machine learning chip according to claim 11; Wherein, the machine learning chip is connected to the storage device, the control device and the interface device respectively; The storage device is used to store data; The interface device is used to realize data transmission between the machine learning chip and external equipment; The control device is used to monitor the status of the machine learning chip. 14. A scalar type conversion instruction processing method, characterized in that the method is applied to a scalar type conversion instruction processing device, the device includes a control module and an operation module, and the method includes: Use the control module to parse the obtained scalar type conversion instruction to obtain the operation code and operation domain of the scalar type conversion instruction, and obtain the scalar sum to be operated required to execute the scalar type conversion instruction based on the operation code and the operation domain. The target address, and determine the target data type and the initial data type of the scalar to be operated; Utilize the operation module to perform a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The data type of the operation result for the target data type, Wherein, the operation code is used to indicate that the operation performed on the data by the scalar type conversion instruction is a scalar type conversion operation, and the operation field includes the scalar address to be operated and the target address; Among them, the scalar type conversion instruction is parsed to obtain the operation code and operation domain of the scalar type conversion instruction, including: store the scalar type conversion instruction; Analyze the scalar type conversion instruction to obtain the operation code and operation domain of the scalar type conversion instruction; An instruction queue is stored, and the instruction queue includes a plurality of instructions to be executed sequentially arranged in an execution order, and the plurality of instructions to be executed include the scalar type conversion instruction. 15. The method according to claim 14, characterized in that performing a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type includes: The scalar type conversion operation is performed using multiple scalar operators in the operation module. 16. The method according to claim 15, wherein the operation module includes a main operator sub-module and a plurality of slave operator sub-modules, and the main operator sub-module includes the plurality of scalar operators, Wherein, performing a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtaining the operation result, and storing the operation result in the target address, including: Multiple scalar operators in the main operation sub-module are used to perform the scalar type conversion operation to obtain an operation result, and the operation result is stored in the target address. 17. The method according to claim 14, characterized in that the operation domain also includes an initial data type and a target data type, Among them, determining the target data type and the initial data type of the scalar to be operated includes: The target data type and the initial data type of the scalar to be operated are determined according to the operation domain. 18. The method according to claim 14, characterized in that the operation code is also used to indicate an initial data type and a target data type, Among them, determining the target data type and the initial data type of the scalar to be operated includes: The target data type and the initial data type of the scalar to be operated are determined according to the operation code. 19. The method according to claim 14, wherein the target data type includes any of 16-bit floating point numbers, 32-bit floating point numbers, 48-bit floating point numbers, 16-bit integers, 32-bit integers and 48-bit integers. One, the initial data type includes 16-bit signed number, 32-bit signed number, 48-bit signed number, 16-bit unsigned number, 32-bit unsigned number, 48-bit unsigned number and pointer data type. Any kind. 20. The method of claim 15, further comprising: Utilize the storage module of the device to store the scalar to be calculated, Wherein, the storage module includes at least one of a register and a cache, The cache is used to store data to be calculated, and the cache includes at least one neuron cache NRAM; The register is used to store the scalar to be operated; The neuron cache is used to store neuron data in the data to be operated, where the neuron data includes neuron vector data. 21. The method of claim 14, further comprising: When it is determined that the first instruction to be executed among the plurality of instructions to be executed is associated with the zeroth instruction to be executed before the first instruction to be executed, the first instruction to be executed is cached, and when it is determined that the first instruction to be executed is After the execution of the zeroth instruction to be executed is completed, the execution of the first instruction to be executed is controlled, Wherein, the correlation between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes: The first storage address interval that stores the data required by the first instruction to be executed has an overlapping area with the zeroth storage address interval that stores the data required by the zeroth instruction to be executed. 22. A non-volatile computer-readable storage medium with computer program instructions stored thereon, characterized in that when the computer program instructions are executed by a processor, the method of any one of claims 14 to 21 is implemented.