CN111723920B - Artificial intelligence computing devices and related products - Google Patents

Abstract

The present application provides an artificial intelligence computing device and related products, which are used to perform machine learning calculations. The embodiments of the present application save storage space for the opcodes by using the same opcode in the opcode storage area for repeated instructions in two or more instruction sets that constitute a loop body. The amount of code for each instruction in the instruction set in the second time slice can be reduced, instruction storage space can be saved, and computing efficiency can be improved.

Description

Artificial intelligence computing devices and related products

Technical Field

The present application relates to the field of information processing technology, and in particular to an artificial intelligence computing device and related products.

Background technique

Artificial neural network is a powerful algorithm that has been applied to various fields such as images and language in recent years. The emergence of artificial intelligence computing devices can enable neural networks to be supported by hardware and perform calculations more efficiently. Artificial intelligence computing devices generally have their own instruction sets, which contain a large number of instructions to be executed. It takes a long time to execute all the instructions in the instruction set, which affects efficiency. It also contains repeated instructions. For example, in the process of data loading, if the data scale is large, it needs to be moved multiple times to complete the address space conversion. For example, repeated addition and multiplication operations in template operations. The repeated calculation of the count here is directly expanded in normal operation. Each instruction corresponds to a section of execution code. The code corresponding to the repeated instructions will take up more storage space.

Summary of the invention

The embodiments of the present application provide an artificial intelligence computing device and related products, which can reduce the amount of code in the instruction information of an instruction and improve the efficiency of instruction calculation.

In a first aspect, an artificial intelligence computing device is provided, the artificial intelligence computing device comprising a controller unit and an execution unit; wherein:

The controller unit is used to obtain a first instruction set to be executed; and obtain a second instruction set;

The controller unit is further used to determine whether the first instruction set and the second instruction set form a loop body;

The execution unit is used to execute instructions in the second instruction set according to instruction information of the first instruction set when a loop body is formed between the first instruction set and the second instruction set.

In a second aspect, an embodiment of the present application provides an artificial intelligence computing method, which is applied to an artificial intelligence computing device, and the method includes:

Obtaining a first instruction set to be executed; and, obtaining a second instruction set;

Determine whether the first instruction set and the second instruction set form a loop body;

When a loop body is formed between the first instruction set and the second instruction set, instructions in the second instruction set are executed according to instruction information of the first instruction set.

In a third aspect, an embodiment of the present application provides a machine learning computing device, which includes one or more artificial intelligence computing devices described in the first aspect. The machine learning computing device is used to obtain data to be computed and control information from other processing devices, and perform specified machine learning operations, and transmit the execution results to peripheral devices through an I/O interface;

When the machine learning computing device includes a plurality of computing devices, the plurality of computing devices may be linked and transmit data through a specific structure;

Among them, multiple computing devices are interconnected and transmit data through a PCIE bus to support larger-scale machine learning operations; multiple computing devices share the same control system or have their own control systems; multiple computing devices share memory or have their own memory; the interconnection method of multiple computing devices is any interconnection topology.

In a fourth aspect, an embodiment of the present application provides a combined processing device, which includes a machine learning computing device, a universal interconnection interface, and other processing devices as described in the third aspect. The machine learning computing device interacts with the other processing devices to jointly complete the operations specified by the user. The combined processing device may also include a storage device, which is respectively connected to the machine learning computing device and the other processing devices, and is used to store data of the machine learning computing device and the other processing devices.

In a fifth aspect, an embodiment of the present application provides a neural network chip, which includes the computing device described in the first aspect, the machine learning computing device described in the third aspect, or the combined processing device described in the fourth aspect.

In a sixth aspect, an embodiment of the present application provides a neural network chip packaging structure, wherein the neural network chip packaging structure includes the neural network chip described in the fifth aspect above;

In the seventh aspect, an embodiment of the present application provides a board card, which includes the neural network chip packaging structure described in the sixth aspect.

In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program enables a computer to execute the method steps described in the second aspect.

In a ninth aspect, an embodiment of the present application provides a computer program product, comprising a non-transitory computer-readable storage medium storing a computer program, wherein the computer program is operable to cause a computer to execute the method steps described in the second aspect.

In the tenth aspect, an embodiment of the present application provides an electronic device, which includes the neural network chip described in the fifth aspect or the board described in the seventh aspect.

In some embodiments, the electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

In some embodiments, the means of transportation include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound equipment and/or electrocardiographs.

It can be seen that in the scheme of the embodiment of the present application, the computing device obtains the first instruction set to be executed through the controller unit, obtains the second instruction set, determines whether a loop body is formed between the first instruction set and the second instruction set, and when the execution unit forms a loop body between the first instruction set and the second instruction set, executes the instructions in the second instruction set according to the instruction information of the first instruction set, thereby reducing the amount of code of the instruction information of the instructions and improving the instruction calculation efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1 is a schematic diagram of the structure of an artificial intelligence computing device provided in an embodiment of the present application;

FIG2A is a schematic diagram of a flow chart of an artificial intelligence computing method provided in an embodiment of the present application;

FIG2B is a schematic diagram illustrating instructions in an instruction set for executing a neural network in parallel provided by an embodiment of the present application;

FIG2C is a schematic diagram showing how instructions in an instruction set are arranged in a tree structure according to an embodiment of the present application;

FIG3 is a structural diagram of a combined processing device provided in an embodiment of the present application;

FIG4 is a structural diagram of another combined processing device provided in an embodiment of the present application;

FIG5 is a schematic diagram of the structure of a board provided in an embodiment of the present application.

Detailed ways

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

First, the computing device used in this application is introduced. Referring to FIG1 , an artificial intelligence computing device is provided, which is used to perform machine learning calculations. The computing device includes: a controller unit 11, a storage unit 10, and an execution unit 12, wherein the storage unit 10 is connected to an external storage device, and the execution unit 12 includes a load execution unit 121, a calculation execution unit 122, and a storage execution unit 123; wherein,

The controller unit is used to obtain a first instruction set to be executed; and obtain a second instruction set;

The controller unit is further used to determine whether the first instruction set and the second instruction set form a loop body;

The execution unit is used to execute instructions in the second instruction set according to instruction information of the first instruction set when a loop body is formed between the first instruction set and the second instruction set.

In a possible embodiment, in executing the instructions in the second instruction set according to the instruction information of the first instruction set, the execution unit is specifically configured to:

According to a jump instruction, jump to an opcode storage area of a first instruction in the first instruction set corresponding to a second instruction in the second instruction set, obtain an opcode of the first instruction from the opcode storage area, and use the opcode as the opcode of the second instruction, wherein the opcode includes an identifier of the first instruction.

In a possible embodiment, the first instruction set includes a first load instruction, a first calculation instruction, and a first storage instruction for a first computing task; the second instruction set includes a second load instruction, a second calculation instruction, and a second storage instruction for a second computing task; in determining whether a loop body is formed between the first instruction set and the second instruction set, the controller unit is specifically used to:

Obtaining preset instruction information corresponding to each instruction in the first instruction set and the second instruction set to obtain a plurality of preset instruction information, wherein the preset instruction information includes at least one of the following: instruction type, remaining execution times, and whether parity is flipped;

Compare the first preset instruction information corresponding to the first load instruction with the second preset instruction information corresponding to the second load instruction; compare the third preset instruction information corresponding to the first calculation instruction with the fourth preset instruction information corresponding to the second calculation instruction; compare the fifth preset instruction information corresponding to the first storage instruction with the sixth preset instruction information corresponding to the second storage instruction;

If the first preset instruction information and the second preset instruction information only differ in the number of operations, the third preset instruction information and the fourth preset instruction information only differ in the number of operations, and the fifth preset instruction information and the sixth preset instruction information only differ in the number of operations, it is determined that the first instruction set and the second instruction set constitute a loop body.

In a possible embodiment, the first instruction set includes a first storage instruction for a first computing task, a second calculation instruction for a second computing task, and a third load instruction corresponding to a third computing task; the second instruction set includes a second storage instruction for the second computing task, a third calculation instruction for the third computing task, and a fourth load instruction for a fourth computing task; in determining whether a loop body is formed between the first instruction set and the second instruction set, the controller unit is specifically used to:

Obtaining preset instruction information corresponding to each instruction in the first instruction set and the second instruction set to obtain a plurality of preset instruction information, wherein the preset instruction information includes at least one of the following: instruction type, remaining execution times, and whether parity is flipped;

Compare the fifth preset instruction information corresponding to the first storage instruction with the sixth preset instruction information corresponding to the second storage instruction; compare the seventh preset instruction information corresponding to the second calculation instruction with the eighth preset instruction information corresponding to the third calculation instruction; compare the ninth preset instruction information corresponding to the third load instruction with the tenth preset instruction information corresponding to the fourth load instruction;

If the only difference between the fifth preset instruction information and the sixth preset instruction information is the number of operations, the only difference between the seventh preset instruction information and the eighth preset instruction information is the number of operations, and the only difference between the ninth preset instruction information and the tenth preset instruction information is the number of operations, it is determined that the first instruction set and the second instruction set constitute a loop body.

In a possible embodiment, the controller unit is further configured to:

Determine whether there is an association relationship between the first storage instruction, the second calculation instruction and the third load instruction;

The execution unit is further configured to execute the first storage instruction, the second calculation instruction and the third load instruction in parallel within a first time slice when there is no association relationship between the first storage instruction, the second calculation instruction and the third load instruction.

In a possible embodiment, in determining whether there is an association relationship between the first storage instruction, the second calculation instruction, and the third load instruction, the controller unit is specifically configured to:

Extract the first storage address interval of the data required in the first storage instruction, extract the second storage address interval of the data required in the second calculation instruction, and extract the third storage address interval of the data required in the third loading instruction. If there is no overlapping area between the first storage address interval, the second storage address interval and the third storage address interval, determine that there is no association relationship between the first storage instruction, the second calculation instruction and the third loading instruction.

In a possible embodiment, in determining whether there is an association relationship between the first storage instruction, the second calculation instruction, and the third load instruction, the controller unit is specifically configured to:

Extracting a first write area corresponding to the first storage instruction, extracting a second read area and a second write area corresponding to the second calculation instruction, and extracting a third read area corresponding to the third load instruction;

If there is no overlapping area between the first writing area, the second reading area, the second writing area and the third reading area, it is determined that there is no association relationship between the first storage instruction, the second calculation instruction and the third loading instruction.

In a possible embodiment, the artificial intelligence computing device further includes a storage unit, and the storage unit is connected to an external storage device; the execution unit includes a loading execution unit, a calculation execution unit, and a storage execution unit;

In terms of executing the first storage instruction, the second calculation instruction and the third loading instruction in parallel within the first time slice, the storage execution unit is used to transfer the first calculation result corresponding to the first input data in the first calculation task from the storage unit to the external storage device according to the first storage instruction, the calculation execution unit is used to calculate the second input data in the second calculation task according to the second calculation instruction to obtain the second calculation result; and the loading execution unit is used to transfer the third input data in the third calculation task from the external storage device to the storage unit according to the third loading instruction.

In a possible embodiment, the storage unit includes a first storage area and a second storage area, and in terms of transmitting the third input data in the third computing task from the external storage device to the storage unit according to the third load instruction, the load execution unit is specifically used to:

In the first time slice, a ping-pong operation is performed on the third input data in the third computing task according to the third load instruction, and the data is transferred from the external storage device to the first storage area.

In a possible embodiment, the third input data includes a plurality of third input sub-data, and in terms of performing a ping-pong operation on the third input data in the third computing task and transferring the third input data from the external storage device to the first storage area, the load execution unit is specifically configured to:

estimating a target storage duration of each of the plurality of third input sub-data in the first storage area to obtain a plurality of target storage durations;

The plurality of third input sub-data corresponding to the plurality of target storage durations are transmitted to the first storage area in a descending order of storage durations, and are stored from both ends to the middle of the first storage area.

As shown in FIG. 2A , FIG. 2A is a flow chart of an artificial intelligence computing method provided in an embodiment of the present application, which is applied to an artificial intelligence computing device, wherein the artificial intelligence computing device includes a controller unit, a storage unit, and an execution unit; the storage unit is connected to an external storage device, and the execution unit includes a loading execution unit, a calculation execution unit, and a storage execution unit; the method includes:

201. Obtain a first instruction set to be executed; and obtain a second instruction set.

In an embodiment of the present application, multiple instructions in the instruction set of the neural network can be divided into input and output instructions and calculation instructions, and the input and output instructions can be divided into loading instructions and storage instructions, wherein the execution unit of the artificial intelligence computing device is used to transfer input data from an external storage device to a storage unit on the artificial intelligence computing device according to the loading instruction, and then directly obtain the input data from the storage unit according to the calculation instruction, and perform calculations based on the input data to obtain calculation results, cache the calculation results to the storage unit, and finally transfer the calculation results from the storage unit to the external storage device according to the storage instruction.

Among them, the division of the instruction set of the neural network may not be limited to the three stages of loading instructions, computing instructions and storage instructions, and instructions may also be divided according to other standards, which is not limited in the embodiments of the present application.

Optionally, the first instruction set may include a first load instruction, a first calculation instruction and a first storage instruction of the first computing task; and the second instruction set may include a second load instruction, a second calculation instruction and a second storage instruction of the second computing task. The first load instruction is used to transfer the first input data in the first computing task from the external storage device to the storage unit, the first calculation instruction is used to calculate the first input data in the first computing task and obtain a first calculation result, and the first storage instruction is used to transfer the first calculation result from the storage unit to the external storage device; the second load instruction is used to transfer the second input data in the second computing task from the external storage device to the storage unit, the second calculation instruction is used to calculate the second input data in the second computing task and obtain a second calculation result, and the second storage instruction is used to transfer the second calculation result from the storage unit to the external storage device.

Optionally, the first instruction set may include a first storage instruction for the first computing task, a second calculation instruction for the second computing task, and a third load instruction for the third computing task; the second instruction set includes a second storage instruction for the second computing task, a third calculation instruction for the third computing task, and a fourth load instruction for the fourth computing task. Among them, the first storage instruction is used to transfer the first calculation result from the storage unit to the external storage device, the second calculation instruction is used to calculate the second input data in the second computing task and obtain the second calculation result, and the third load instruction is used to transfer the third input data in the third computing task from the external storage device to the storage unit; the second storage instruction is used to transfer the second calculation result from the storage unit to the external storage device, the third calculation instruction is used to calculate the third input data in the third computing task and obtain the third calculation result, and the fourth load instruction is used to transfer the fourth input data in the fourth computing task from the external storage device to the storage unit.

202. Determine whether the first instruction set and the second instruction set form a loop body.

Optionally, the first instruction set includes a first load instruction, a first calculation instruction and a first storage instruction of a first computing task; the second instruction set includes a second load instruction, a second calculation instruction and a second storage instruction of a second computing task; in the above step 202, determining whether a loop body is formed between the first instruction set and the second instruction set may include the following steps:

Obtaining preset instruction information corresponding to each instruction in the first instruction set and the second instruction set to obtain a plurality of preset instruction information, wherein the preset instruction information includes at least one of the following: instruction type, remaining execution times, and whether parity is flipped;

Compare the first preset instruction information corresponding to the first load instruction with the second preset instruction information corresponding to the second load instruction; compare the third preset instruction information corresponding to the first calculation instruction with the fourth preset instruction information corresponding to the second calculation instruction; compare the fifth preset instruction information corresponding to the first storage instruction with the sixth preset instruction information corresponding to the second storage instruction;

If the first preset instruction information and the second preset instruction information only differ in the number of operations, the third preset instruction information and the fourth preset instruction information only differ in the number of operations, and the fifth preset instruction information and the sixth preset instruction information only differ in the number of operations, it is determined that the first instruction set and the second instruction set constitute a loop body.

The preset instruction information may include at least one of the following information: instruction type, remaining execution times, and whether parity is flipped. The instruction type refers to whether the instruction is a load instruction, a calculation instruction, or a storage instruction, and when the instruction is a calculation instruction, the operator type contained in the calculation instruction, and the operator type may include at least one of the following: addition, subtraction, multiplication, division, convolution, and a combination of the above multiple operators, etc. The remaining execution times refers to the remaining execution times for a repeated operation that needs to be performed multiple times in an operation.

In an embodiment of the present application, the first load instruction, the first calculation instruction and the first storage instruction in the first computing task can be compared with the preset instruction information corresponding to the second load instruction, the second calculation instruction and the second storage instruction of the second computing task to determine that a loop body is formed between the first instruction set and the second instruction set. For example, when operating _Yi =∑( _wxi +b), i=1, 2, 3, ...100, assuming that _Y1 = _wx1 +b is the first computing task and _Y2 = _wx2 +b is the second computing task, the first load instruction, the first calculation instruction and the first storage instruction of the operation _Y1 = _wx1 +b correspond to the first instruction set, and the second load instruction, the second calculation instruction and the second storage instruction of the operation _Y2 = _wx2 +b correspond to the second instruction set. Among the multiple preset instruction information corresponding to the operation Y ₁ =wx ₁ +b, the remaining calculation times of the first calculation instruction corresponding to the operation Y ₁ =wx ₁ +b is 99 times, and the remaining calculation times of the second calculation instruction corresponding to the operation Y ₂ =wx ₂ +b is 98 times. It can be seen that between the instructions in the first instruction set corresponding to the first operation task and the second instruction set corresponding to the second operation task, the first load instruction and the second load instruction are of the same type, but the remaining load times are different, the first storage instruction and the second storage instruction are of the same type, but the remaining storage times are different, and the operator types in the first calculation instruction and the second calculation instruction both include addition and multiplication operators, and the operation order is the same, only the remaining calculation times are different. Therefore, it can be determined that the first instruction set and the second instruction set are loop bodies.

Optionally, the first instruction set includes a first storage instruction of a first computing task, a second calculation instruction of a second computing task, and a third load instruction of a third computing task; the second instruction set includes a second storage instruction of the second computing task, a third calculation instruction of the third computing task, and a fourth load instruction of a fourth computing task; in the above step 202, determining whether a loop body is formed between the first instruction set and the second instruction set may include the following steps:

Obtaining preset instruction information corresponding to each instruction in the first instruction set and the second instruction set to obtain a plurality of preset instruction information, wherein the preset instruction information includes at least one of the following: instruction type, remaining execution times, and whether parity is flipped;

Compare the fifth preset instruction information corresponding to the first storage instruction with the sixth preset instruction information corresponding to the second storage instruction; compare the seventh preset instruction information corresponding to the second calculation instruction with the eighth preset instruction information corresponding to the third calculation instruction; compare the ninth preset instruction information corresponding to the third load instruction with the tenth preset instruction information corresponding to the fourth load instruction;

If the only difference between the fifth preset instruction information and the sixth preset instruction information is the number of operations, the only difference between the seventh preset instruction information and the eighth preset instruction information is the number of operations, and the only difference between the ninth preset instruction information and the tenth preset instruction information is the number of operations, it is determined that the first instruction set and the second instruction set constitute a loop body.

In an embodiment of the present application, the instructions in the instruction set of the neural network can be arranged in a tree structure, please refer to Figure 2B, Figure 2B is a demonstration schematic diagram of arranging the instructions in the instruction set in a tree structure provided by an embodiment of the present application. As shown in Figure 2B, the first layer of numbers in the tree structure is used to represent chip information, for example, "1" represents the first chip, and the second layer of numbers is used to represent time slices, for example, "1" represents the first time slice, "2" represents the second time slice, and so on. The third layer of letters represents the loading instructions, calculation instructions, and storage instructions in each time slice, where L represents the loading instructions, C represents the calculation instructions, and S represents the storage instructions. Each instruction corresponds to a preset instruction information. For example, when operating _Yi =∑( _wxi +b), i=1, 2, 3, ... 100, the value of i will change from 1 to 100, then the operation _Yi = _wxi +b is repeated a total of 100 times, and in the first time slice, the operation _Yi = _wxi is repeated. The total number of times Yi = wxi + b is 100, and addition and multiplication operations are performed each time. Therefore, it can be determined that the 100 operations of _Yi = _wxi + b in the operation are a loop body.

Among them, the loop body corresponding to the instruction set of each time slice can be parsed in advance to obtain the preset instruction information of each node in the tree structure. For the adjacent first time slice and second time slice, it can be determined whether the first instruction set corresponding to the first time slice and the second instruction set corresponding to the second time slice constitute a loop body. Specifically, the fifth preset instruction information corresponding to the first storage instruction of the first computing task is compared with the sixth preset instruction information corresponding to the second storage instruction of the second computing task; the seventh preset instruction information corresponding to the second computing instruction of the second computing task is compared with the eighth preset instruction information corresponding to the third computing instruction of the third computing task; and the ninth preset instruction information corresponding to the third load instruction of the third computing task is compared with the tenth preset instruction information corresponding to the fourth load instruction of the fourth computing task; if the remaining execution times except for are different and the second time slice is If the remaining execution times of the instructions corresponding to the time slice are small and the rest of the information is exactly the same, it can be determined that the second instruction set corresponding to the second time slice and the first instruction set corresponding to the first time slice constitute a loop body. For example, if the first time slice includes loading instructions, calculation instructions and storage instructions, the operators included in the calculation instructions are addition and multiplication, the remaining operation times of the loading instructions are 5 times, the remaining operation times of the calculation instructions are 9 times, and the remaining operation times of the storage instructions are 3 times, and the second instruction set in the second time slice also includes loading instructions, calculation instructions and storage instructions, the operators included in the calculation instructions are addition and multiplication, the remaining operation times of the loading instructions are 4 times, the remaining operation times of the calculation instructions are 8 times, and the remaining operation times of the storage instructions are 2 times, it can be determined that the first instruction set corresponding to the first time slice and the second instruction set corresponding to the second time slice to which the calculation instructions belong constitute a loop body.

Furthermore, it can be determined whether multiple instruction sets corresponding to multiple consecutive time slices constitute a loop body. If multiple instruction sets corresponding to multiple consecutive time slices constitute a loop body, it indicates that instructions of the same type in the multiple consecutive time slices are repeatedly executed instructions. In the loop body, the starting point of the loop body is the time slice where the node with the largest number of remaining operations is located, and the length of the loop body is the difference between the farthest time slice that meets the loop condition and the starting time slice.

203. When a loop body is formed between the first instruction set and the second instruction set, instructions in the second instruction set are executed according to instruction information of the first instruction set.

Among them, the above-mentioned instruction information may include the operation code and operation domain of the instruction. In a specific implementation, if a loop body is formed between the first instruction set and the second instruction set, the operation code and operation domain of the instruction in the first instruction set can be stored. Then, when executing the instruction in the second instruction set, it directly jumps to the operation code of the instruction in the first instruction set corresponding to the instruction in the second instruction set, and then executes the instruction in the second instruction set according to the operation code of the instruction in the first instruction set.

For example, when operating _Yi =∑( _wxi +b), i=1, 2, 3, ...100, the value of i will change from 1 to 100, then the operation _Yi = _wxi +b must be repeated a total of 100 times. In the first time slice, the operation _Yi = _wxi +b must be repeated a total of 100 times, and addition and multiplication operations must be performed each time. Therefore, it can be determined that the 100 operations of _Yi = _wxi +b in the operation are a loop body. In the embodiment of the present application, the operation code corresponding to the first calculation instruction corresponding to the first time slice can be stored in the operation code storage area, and there is no need to repeatedly store the operation codes of multiple instructions corresponding to the 100 operations of _Yi = _wxi +b. During the execution of the second time slice, a jump instruction can be used to jump to the operation code storage area to obtain the operation code of the instruction of the first instruction set corresponding to the second instruction set, so that the operation code of the operation code storage area can be reused, saving the storage space of the operation code, reducing the amount of code of each instruction in the instruction set in the second time slice, saving instruction storage space, and improving computing efficiency.

Optionally, in the embodiment of the present application, it is assumed that Y ₁ =wx ₁ +b is the first operation task, Y ₂ =wx ₂ +b is the second operation task, and Y ₃ =wx ₃ +b is the third operation task. The first instruction set includes a first storage instruction corresponding to the Y ₁ =wx ₁ +b operation, a first calculation instruction corresponding to the Y ₂ =wx ₂ +b operation, and a first load instruction corresponding to the Y ₃ =wx ₃ +b operation. The second instruction set includes a second storage instruction corresponding to the Y ₂ =wx ₂ +b operation, a second calculation instruction corresponding to the Y ₃ =wx ₃ +b operation, and a second load instruction corresponding to the Y ₄ =wx ₄ +b operation. Among them, among the multiple preset instruction information corresponding to the operation Y ₁ =wx ₁ +b, the remaining number of calculations of the calculation instruction corresponding to the operation Y ₁ =wx ₁ +b is 99 times; the remaining number of calculations of the first calculation instruction corresponding to the operation Y ₂ =wx ₂ +b is 98 times. It can be seen that between the instructions in the first instruction set corresponding to the first time slice and the second instruction set in the second time slice, the first load instruction and the second load instruction are of the same type, but the remaining number of loads is different, the first storage instruction and the second storage instruction are of the same type, but the remaining number of storages is different, the operator types in the first calculation instruction and the second calculation instruction both include addition and multiplication operators, and the operation order is the same, only the remaining number of calculations is different. Therefore, it can be determined that the first instruction set and the second instruction set are loop bodies.

Optionally, in the above step 203, executing the instructions in the second instruction set according to the instruction information of the first instruction set may include the following steps:

According to a jump instruction, jump to an opcode storage area of a first instruction in the first instruction set corresponding to a second instruction in the second instruction set, obtain an opcode of the first instruction from the opcode storage area, and use the opcode as the opcode of the second instruction, wherein the opcode includes an identifier of the first instruction.

Optionally, in the embodiment of the present application, the following steps may also be included:

A1 determines whether there is an association relationship between the first storage instruction, the second calculation instruction and the third load instruction;

A2. When there is no association relationship among the first storage instruction, the second calculation instruction and the third load instruction, the first storage instruction, the second calculation instruction and the third load instruction are executed in parallel within a first time slice.

In the embodiments of the present application, load instructions and storage instructions, load instructions and calculation instructions, and storage instructions and calculation instructions can be executed in parallel, but load instructions and load instructions, calculation instructions and calculation instructions, and storage instructions and storage instructions cannot be executed in parallel and need to be executed serially.

Among them, in the process of executing instructions, between two instructions, if the execution of one instruction requires the data of another instruction, it indicates that there is an association relationship between the two instructions. For example, if the execution of a calculation instruction requires the data loaded by a load instruction, it indicates that the calculation instruction can only be executed after the load instruction is executed. It can be determined that the load instruction has an association relationship with the calculation instruction. Therefore, the association relationship between the instructions to be executed can be determined. If it is determined that there is no association relationship between multiple instructions to be executed, the two or three instructions that are not associated are executed in parallel through the loading execution unit, the calculation execution unit and the storage execution unit in the execution unit. In the embodiment of the present application, the situations in which instructions can be executed in parallel include the following: loading instructions and storage instructions can be executed in parallel, loading instructions and calculation instructions can be executed in parallel, storage instructions and calculation instructions can be executed in parallel, and loading instructions, calculation instructions and storage instructions can be executed in parallel. Therefore, in the embodiment of the present application, multiple instructions in the instruction set of the neural network can be arranged in a pipeline manner, please refer to Figure 2C, Figure 2C is a demonstration schematic diagram of a parallel execution of instructions in the instruction set of the neural network provided by the embodiment of the present application, as shown in Figure 2C, L represents a load instruction, C represents a calculation instruction, and S represents a storage instruction, wherein each horizontal row of load instructions, calculation instructions, and storage instructions corresponds to a computing task, which can load the input data, calculate the calculation result, and store the result; each vertical column of load instructions, calculation instructions, and storage instructions corresponds to a time slice, indicating that the load instructions, calculation instructions, and storage instructions that are not associated are executed in parallel. It can be seen that by executing instructions that are not associated in parallel, multiple computing tasks that are not associated can be executed in parallel, thereby saving computing time and improving computing efficiency.

Optionally, in the above step A1, determining whether there is an association relationship between the first storage instruction, the second calculation instruction and the third load instruction may include the following steps:

A11, extracting a first storage address interval of data required in the first storage instruction, extracting a second storage address interval of data required in the second calculation instruction, and extracting a third storage address interval of data required in the third load instruction;

A12: If the first storage address interval, the second storage address interval and the third storage address interval do not have any overlapping areas, determine that there is no association relationship between the first storage instruction, the second calculation instruction and the third load instruction.

Optionally, in the above step A1, determining whether there is an association relationship between the first storage instruction, the second calculation instruction and the third load instruction may include the following steps:

A13, extracting a first write area corresponding to the first storage instruction, extracting a second read area and a second write area corresponding to the second calculation instruction, and extracting a third read area corresponding to the third load instruction;

A14. If there is no overlapping area between the first writing area, the second reading area, the second writing area and the third reading area, determine that there is no association relationship between the first storage instruction, the second calculation instruction and the third loading instruction.

Optionally, the artificial intelligence computing device further includes a storage unit, and the storage unit is connected to an external storage device; in the above step A2, executing the first storage instruction, the second computing instruction and the third loading instruction in parallel within the first time slice may include the following steps:

B1. transmitting the first calculation result corresponding to the first input data in the first calculation task from the storage unit to the external storage device according to the first storage instruction;

B2. Calculate the second input data in the second computing task according to the second computing instruction to obtain a second computing result;

B3. Transferring the third input data in the third computing task from the external storage device to the storage unit according to the third loading instruction.

Optionally, the storage unit includes a first storage area and a second storage area. In the above step B3, transmitting the third input data in the third computing task from the external storage device to the storage unit according to the third load instruction may include the following steps:

In the first time slice, a ping-pong operation is performed on the third input data in the third computing task according to the third load instruction, and the data is transferred from the external storage device to the first storage area.

The storage unit can be divided into a first storage area and a second storage area. When executing the load instruction in the instruction set of the neural network, a ping-pong operation can be performed to transfer the input data from the external storage device to the first storage area and the second storage area for storage in turn. Specifically, in the first time slice, the third input data can be transferred and stored in the first storage area according to the third load instruction. In the second time slice, the fourth input data can be stored in the second storage area according to the fourth load instruction. At this time, the third calculation instruction can be executed in parallel, and the third input data can be obtained from the first storage area according to the third calculation instruction for calculation to obtain the calculation result. In the next time slice, the next input data can be stored in the first storage area, and the next calculation instruction corresponding to the fourth load instruction can be executed in parallel, and the cycle is repeated. Thus, the storage space of the storage unit can be saved.

Optionally, the third input data includes a plurality of third input sub-data, and performing a ping-pong operation on the third input data in the third computing task and transmitting the third input data from the external storage device to the first storage area may specifically include the following steps:

C1. estimating a target storage duration of each of the plurality of third input sub-data in the first storage area to obtain a plurality of target storage durations;

C2, transferring the plurality of third input sub-data corresponding to the plurality of target storage durations to the first storage area in descending order of storage duration, and storing them from both ends of the first storage area to the middle

Among them, the closer the storage position of the input data is to the middle, the longer the time required to read the input data during calculation. Therefore, in the process of storing the above-mentioned multiple third input sub-data, the target storage time of each third input sub-data can be determined first, and then stored from both ends to the middle of the first storage area in descending order of storage time. In this way, in the process of obtaining the third input data for calculation, the reading time of the third input sub-data corresponding to the larger target storage time can be reduced, thereby improving the computing efficiency.

Similarly, in the process of transmitting the input data from the external storage device to the second storage area, the data may be stored from both ends to the middle of the second storage area in descending order of storage duration.

For example, in the process of executing the operation _Yi =∑( _wxi +b), w and b are data that will be repeatedly read, and it can be determined that the storage time corresponding to w and b is longer. w and b can be stored at both ends of the first storage area or the second storage area, and x _i can be stored in the middle of the first storage area or the second storage area. Therefore, when reading data from the first storage area or the second storage area, the time for reading w and b each time is shorter, thereby reducing the time spent on reading data.

To give another example, as shown in FIG2C , each horizontal row of loading instructions, computing instructions, and storage instructions corresponds to a computing task. For example, the first computing task may include a first loading instruction La, a first computing instruction Ca, and a first storage instruction Sa. The first loading instruction La may be used to load input data from an external storage device to the a1 area of the storage unit on the artificial intelligence computing device; then, the first computing instruction Ca may be used to read the input data from the a1 area, calculate the input data, obtain a calculation result, and store the calculation result in the a2 area of the storage unit on the artificial intelligence computing device; finally, the first storage instruction Sa may be used to read the calculation result from the a2 area, and transmit the calculation result from the a2 area of the storage unit to the external storage device. Similarly, the second computing task may include a second loading instruction Lb, a second computing instruction Cb, and a second storage instruction Sb. The third computing task may include a third loading instruction Lc, a third computing instruction Cc, and a third storage instruction Sc. The fourth computing task may include a fourth loading instruction Ld, a fourth computing instruction Cd, and a fourth storage instruction Sd. It can be seen that in the first time slice, if there is no association between the first storage instruction Sa of the first computing task, the second computing instruction Cb of the second computing task and the third loading instruction Lc of the third computing task, the first storage instruction Sa, the second computing instruction Cb and the third loading instruction Lc can be executed in parallel in the first time slice. In addition, if there is no association between the second computing task, the third computing task and the fourth computing task, the second storage instruction Sb of the second computing task, the third computing instruction Cc of the third computing task and the fourth loading instruction Ld of the fourth computing task can also be executed in parallel in the second time slice.

Further, if a first instruction set consisting of a first storage instruction Sa, a second computing instruction Cb, and a third loading instruction Lc executed in parallel in a first time slice and a second instruction set consisting of a second storage instruction Sb, a third computing instruction Cc, and a fourth loading instruction Ld executed in parallel in a second time slice constitute a loop body, when executing instructions in the instruction set corresponding to the second time slice, the jump can be made to the operation code storage area of the instructions corresponding to the first instruction set according to the jump instruction. Specifically, the first operation code of the third loading instruction Lc, the second operation code of the second computing instruction Cb, and the third operation code of the first storage instruction Sa are obtained from the operation code storage area; then, the first operation code is used as the operation code of the fourth loading instruction Ld, the second operation code is used as the operation code of the third computing instruction Cc, and the third operation code is used as the operation code of the second storage instruction Sb; in addition, the first operation domain corresponding to the fourth loading instruction Ld, the second operation domain corresponding to the third computing instruction Cc, and the third operation domain corresponding to the second storage instruction Sb can be obtained.

The technical solution provided by the present application folds repeated instructions in the instruction set of the neural network and executes the repeated instructions through jump instructions, thereby reducing the amount of code for expanding repeated instructions, and improves the efficiency of data acquisition by storing the data in the neural network in different divided areas, thereby improving the computing efficiency of the neural network.

The present application also discloses a machine learning computing device, which includes one or more artificial intelligence computing devices mentioned in the present application, and is used to obtain data to be calculated and control information from other processing devices, perform specified machine learning operations, and transmit the execution results to peripheral devices through I/O interfaces. Peripheral devices include cameras, displays, mice, keyboards, network cards, wifi interfaces, and servers. When more than one artificial intelligence computing device is included, the artificial intelligence computing devices can be linked and data can be transmitted through a specific structure, for example, interconnected and data can be transmitted through a PCIE bus to support larger-scale machine learning operations. At this time, the same control system can be shared, or each independent control system can be provided; memory can be shared, or each accelerator can have its own memory. In addition, the interconnection method can be any interconnection topology.

The machine learning computing device has high compatibility and can be connected to various types of servers through a PCIE interface.

The present application also discloses a combined processing device, which includes the above-mentioned machine learning computing device, a universal interconnection interface, and other processing devices. The machine learning computing device interacts with other processing devices to jointly complete the operation specified by the user. FIG3 is a schematic diagram of the combined processing device.

Other processing devices include one or more types of processors such as central processing unit (CPU), graphics processing unit (GPU), neural network processor, and other general/special processors. There is no limit on the number of processors included in other processing devices. Other processing devices serve as interfaces between the machine learning computing device and external data and control, including data handling, to complete basic control of the machine learning computing device such as starting and stopping; other processing devices can also collaborate with the machine learning computing device to complete computing tasks.

A universal interconnection interface is used to transmit data and control instructions between the machine learning computing device and other processing devices. The machine learning computing device can obtain the required input data from other processing devices and write it into the storage device on the machine learning computing device chip; it can obtain control instructions from other processing devices and write them into the control cache on the machine learning computing device chip; it can also read data in the storage module of the machine learning computing device and transmit it to other processing devices.

Optionally, as shown in FIG4 , the structure may further include a storage device, which is connected to the machine learning operation device and the other processing device, respectively. The storage device is used to store data in the machine learning operation device and the other processing device, and is particularly suitable for data that cannot be fully stored in the internal storage of the machine learning operation device or other processing devices.

The combined processing device can be used as a SOC chip system for mobile phones, robots, drones, video surveillance equipment and other devices, effectively reducing the core area of the control part, improving the processing speed, and reducing the overall power consumption. In this case, the universal interconnection interface of the combined processing device is connected to certain components of the device. Certain components include cameras, displays, mice, keyboards, network cards, and wifi interfaces.

In some embodiments, a chip is also disclosed, which includes the above-mentioned machine learning computing device or combined processing device.

In some embodiments, a chip packaging structure is disclosed, which includes the above-mentioned chip.

In some embodiments, a board is disclosed, which includes the above chip packaging structure. Referring to FIG5 , FIG5 provides a board, which, in addition to the above chip 389, may also include other supporting components, including but not limited to: a storage device 390, an interface device 391 and a control device 392;

The memory device 390 is connected to the chip in the chip package structure through a bus for storing data. The memory device may include multiple groups of storage units 393. Each group of storage units is connected to the chip through a bus. It can be understood that each group of storage units may be DDRSDRAM (English: Double Data Rate SDRAM, double rate synchronous dynamic random access memory).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In one embodiment, the storage device may include 4 groups of storage units. Each group of storage units may include multiple DDR4 particles (chips). In one embodiment, the chip may include 4 72-bit DDR4 controllers, 64 bits of the above 72-bit DDR4 controllers are used for data transmission, and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of storage units, the theoretical bandwidth of data transmission can reach 25600MB/s.

In one embodiment, each group of the storage units includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling DDR is arranged in the chip to control the data transmission and data storage of each of the storage units.

The interface device is electrically connected to the chip in the chip packaging structure. The interface device is used to realize data transmission between the chip and an external device (such as a server or a computer). For example, in one embodiment, the interface device can be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface to realize data transfer. Preferably, when the PCIE3.0X16 interface is used for transmission, the theoretical bandwidth can reach 16000MB/s. In another embodiment, the interface device can also be other interfaces. This application does not limit the specific forms of expression of the above-mentioned other interfaces. The interface unit can realize the switching function. In addition, the calculation results of the chip are still transmitted back to the external device (such as a server) by the interface device.

The control device is electrically connected to the chip. The control device is used to monitor the state of the chip. Specifically, the chip and the control device can be electrically connected via an SPI interface. The control device may include a single-chip microcomputer (Micro Controller Unit, MCU). For example, the chip may include multiple processing chips, multiple processing cores or multiple processing circuits, which can drive multiple loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and/or multiple processing circuits in the chip.

In some embodiments, an electronic device is applied for, which includes the above-mentioned board.

Electronic devices include data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, vehicles, household appliances, and/or medical devices.

The transportation means include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound machines and/or electrocardiographs.

It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be electrical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software program module.

If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a memory, including a number of instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

A person skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, and the memory can include: a flash drive, a read-only memory (English: Read-Only Memory, abbreviated as: ROM), a random access memory (English: Random Access Memory, abbreviated as: RAM), a magnetic disk or an optical disk, etc.

The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims (16)

1. An artificial intelligence computing device, characterized in that the artificial intelligence computing device comprises a controller unit and an execution unit; wherein: The controller unit is used to obtain a first instruction set to be executed; and obtain a second instruction set; The controller unit is further used to determine whether the first instruction set and the second instruction set form a loop body; The execution unit is configured to execute instructions in the second instruction set according to instruction information of the first instruction set when a loop body is formed between the first instruction set and the second instruction set; The first instruction set includes a first load instruction, a first calculation instruction and a first storage instruction for a first computing task; the second instruction set includes a second load instruction, a second calculation instruction and a second storage instruction for a second computing task; in determining whether a loop body is formed between the first instruction set and the second instruction set, the controller unit is specifically used to: Obtaining preset instruction information corresponding to each instruction in the first instruction set and the second instruction set to obtain a plurality of preset instruction information, wherein the preset instruction information includes at least one of the following: instruction type, remaining execution times, and whether parity is flipped; Compare the first preset instruction information corresponding to the first load instruction with the second preset instruction information corresponding to the second load instruction; compare the third preset instruction information corresponding to the first calculation instruction with the fourth preset instruction information corresponding to the second calculation instruction; compare the fifth preset instruction information corresponding to the first storage instruction with the sixth preset instruction information corresponding to the second storage instruction; If the first preset instruction information and the second preset instruction information differ only in the number of operations, the third preset instruction information and the fourth preset instruction information differ only in the number of operations, and the fifth preset instruction information and the sixth preset instruction information differ only in the number of operations, it is determined that the first instruction set and the second instruction set constitute a loop body; or, The first instruction set includes a first storage instruction for a first computing task, a second calculation instruction for a second computing task, and a third load instruction corresponding to a third computing task; the second instruction set includes a second storage instruction for the second computing task, a third calculation instruction for the third computing task, and a fourth load instruction for a fourth computing task; in terms of determining whether a loop body is formed between the first instruction set and the second instruction set, the controller unit is specifically used to: Obtaining preset instruction information corresponding to each instruction in the first instruction set and the second instruction set to obtain a plurality of preset instruction information, wherein the preset instruction information includes at least one of the following: instruction type, remaining execution times, and whether parity is flipped; Compare the fifth preset instruction information corresponding to the first storage instruction with the sixth preset instruction information corresponding to the second storage instruction; compare the seventh preset instruction information corresponding to the second calculation instruction with the eighth preset instruction information corresponding to the third calculation instruction; compare the ninth preset instruction information corresponding to the third load instruction with the tenth preset instruction information corresponding to the fourth load instruction; If the only difference between the fifth preset instruction information and the sixth preset instruction information is the number of operations, the only difference between the seventh preset instruction information and the eighth preset instruction information is the number of operations, and the only difference between the ninth preset instruction information and the tenth preset instruction information is the number of operations, it is determined that the first instruction set and the second instruction set constitute a loop body. 2. The device according to claim 1, wherein, in executing the instructions in the second instruction set according to the instruction information of the first instruction set, the execution unit is specifically configured to: According to a jump instruction, jump to an opcode storage area of a first instruction in the first instruction set corresponding to a second instruction in the second instruction set, obtain an opcode of the first instruction from the opcode storage area, and use the opcode as the opcode of the second instruction, wherein the opcode includes an identifier of the first instruction. 3. The device according to claim 1, characterized in that the controller unit is further used for: Determine whether there is an association relationship between the first storage instruction, the second calculation instruction and the third load instruction; The execution unit is further configured to execute the first storage instruction, the second calculation instruction and the third load instruction in parallel within a first time slice when there is no association relationship between the first storage instruction, the second calculation instruction and the third load instruction. 4. The device according to claim 3, characterized in that, in determining whether there is an association relationship between the first storage instruction, the second calculation instruction and the third load instruction, the controller unit is specifically configured to: Extract the first storage address interval of the data required in the first storage instruction, extract the second storage address interval of the data required in the second calculation instruction, and extract the third storage address interval of the data required in the third loading instruction. If there is no overlapping area between the first storage address interval, the second storage address interval and the third storage address interval, determine that there is no association relationship between the first storage instruction, the second calculation instruction and the third loading instruction. 5. The device according to claim 3, characterized in that, in determining whether there is an association relationship between the first storage instruction, the second calculation instruction and the third load instruction, the controller unit is specifically configured to: Extracting a first write area corresponding to the first storage instruction, extracting a second read area and a second write area corresponding to the second calculation instruction, and extracting a third read area corresponding to the third load instruction; If there is no overlapping area between the first writing area, the second reading area, the second writing area and the third reading area, it is determined that there is no association relationship between the first storage instruction, the second calculation instruction and the third loading instruction. 6. The device according to any one of claims 3 to 5, characterized in that the artificial intelligence computing device further comprises a storage unit, and the storage unit is connected to an external storage device; the execution unit comprises a loading execution unit, a calculation execution unit and a storage execution unit; In terms of executing the first storage instruction, the second calculation instruction and the third loading instruction in parallel within the first time slice, the storage execution unit is used to transfer the first calculation result corresponding to the first input data in the first calculation task from the storage unit to the external storage device according to the first storage instruction, the calculation execution unit is used to calculate the second input data in the second calculation task according to the second calculation instruction to obtain the second calculation result; and the loading execution unit is used to transfer the third input data in the third calculation task from the external storage device to the storage unit according to the third loading instruction. 7. The device according to claim 6, characterized in that the storage unit comprises a first storage area and a second storage area, and in the aspect of transmitting the third input data in the third computing task from the external storage device to the storage unit according to the third load instruction, the load execution unit is specifically used for: In the first time slice, a ping-pong operation is performed on the third input data in the third computing task according to the third load instruction, and the data is transferred from the external storage device to the first storage area. 8. The device according to claim 7, wherein the third input data comprises a plurality of third input sub-data, and in terms of performing a ping-pong operation on the third input data in the third computing task and transferring the third input data from the external storage device to the first storage area, the load execution unit is specifically configured to: estimating a target storage duration of each of the plurality of third input sub-data in the first storage area to obtain a plurality of target storage durations; The plurality of third input sub-data corresponding to the plurality of target storage durations are transmitted to the first storage area in a descending order of storage durations, and are stored from both ends to the middle of the first storage area. 9. An artificial intelligence computing method, characterized in that it is applied to an artificial intelligence computing device, the method comprising: Obtaining a first instruction set to be executed; and, obtaining a second instruction set; Determine whether the first instruction set and the second instruction set form a loop body; When a loop body is formed between the first instruction set and the second instruction set, the instructions in the second instruction set are executed according to the instruction information of the first instruction set; The first instruction set includes a first load instruction, a first calculation instruction, and a first storage instruction for a first computing task; the second instruction set includes a second load instruction, a second calculation instruction, and a second storage instruction for a second computing task; and determining whether a loop body is formed between the first instruction set and the second instruction set includes: Obtaining preset instruction information corresponding to each instruction in the first instruction set and the second instruction set to obtain a plurality of preset instruction information, wherein the preset instruction information includes at least one of the following: instruction type, remaining execution times, and whether parity is flipped; Compare the first preset instruction information corresponding to the first load instruction with the second preset instruction information corresponding to the second load instruction; compare the third preset instruction information corresponding to the first calculation instruction with the fourth preset instruction information corresponding to the second calculation instruction; compare the fifth preset instruction information corresponding to the first storage instruction with the sixth preset instruction information corresponding to the second storage instruction; If the first preset instruction information and the second preset instruction information differ only in the number of operations, the third preset instruction information and the fourth preset instruction information differ only in the number of operations, and the fifth preset instruction information and the sixth preset instruction information differ only in the number of operations, it is determined that the first instruction set and the second instruction set constitute a loop body; or, The first instruction set includes a first storage instruction of a first computing task, a second calculation instruction of a second computing task, and a third load instruction of a third computing task; the second instruction set includes a second storage instruction of the second computing task, a third calculation instruction of the third computing task, and a fourth load instruction of the fourth computing task; and determining whether a loop body is formed between the first instruction set and the second instruction set includes: Obtaining preset instruction information corresponding to each instruction in the first instruction set and the second instruction set to obtain a plurality of preset instruction information, wherein the preset instruction information includes at least one of the following: instruction type, remaining execution times, and whether parity is flipped; Compare the fifth preset instruction information corresponding to the first storage instruction with the sixth preset instruction information corresponding to the second storage instruction; compare the seventh preset instruction information corresponding to the second calculation instruction with the eighth preset instruction information corresponding to the third calculation instruction; compare the ninth preset instruction information corresponding to the third load instruction with the tenth preset instruction information corresponding to the fourth load instruction; If the only difference between the fifth preset instruction information and the sixth preset instruction information is the number of operations, the only difference between the seventh preset instruction information and the eighth preset instruction information is the number of operations, and the only difference between the ninth preset instruction information and the tenth preset instruction information is the number of operations, it is determined that the first instruction set and the second instruction set constitute a loop body. 10. The method according to claim 9, wherein executing the instructions in the second instruction set according to the instruction information of the first instruction set comprises: According to a jump instruction, jump to an opcode storage area of a first instruction in the first instruction set corresponding to a second instruction in the second instruction set, obtain an opcode of the first instruction from the opcode storage area, and use the opcode as the opcode of the second instruction, wherein the opcode includes an identifier of the first instruction. 11. The method according to claim 9, characterized in that the method further comprises: Determine whether there is an association relationship between the first storage instruction, the second calculation instruction and the third load instruction; The execution unit is further configured to execute the first storage instruction, the second calculation instruction and the third load instruction in parallel within a first time slice when there is no association relationship between the first storage instruction, the second calculation instruction and the third load instruction. 12. The method according to claim 11, wherein determining whether there is an association relationship between the first storage instruction, the second calculation instruction and the third load instruction comprises: Extract the first storage address interval of the data required in the first storage instruction, extract the second storage address interval of the data required in the second calculation instruction, and extract the third storage address interval of the data required in the third loading instruction. If there is no overlapping area between the first storage address interval, the second storage address interval and the third storage address interval, determine that there is no association relationship between the first storage instruction, the second calculation instruction and the third loading instruction. 13. The method according to claim 11, wherein determining whether there is an association relationship among the first storage instruction, the second calculation instruction and the third load instruction comprises: Extracting a first write area corresponding to the first storage instruction, extracting a second read area and a second write area corresponding to the second calculation instruction, and extracting a third read area corresponding to the third load instruction; If there is no overlapping area between the first writing area, the second reading area, the second writing area and the third reading area, it is determined that there is no association relationship between the first storage instruction, the second calculation instruction and the third loading instruction. 14. The method according to any one of claims 11 to 13, characterized in that the artificial intelligence computing device further comprises a storage unit, and the storage unit is connected to an external storage device; the parallel execution of the first storage instruction, the second computing instruction and the third loading instruction in the first time slice comprises: transmitting a first calculation result corresponding to the first input data in the first calculation task from the storage unit to the external storage device according to the first storage instruction; Calculate the second input data in the second computing task according to the second computing instruction to obtain a second computing result; The third input data in the third computing task is transferred from the external storage device to the storage unit according to the third loading instruction. 15. The method according to claim 14, wherein the storage unit comprises a first storage area and a second storage area, and the transferring of the third input data in the third computing task from the external storage device to the storage unit according to the third load instruction comprises: In the first time slice, a ping-pong operation is performed on the third input data in the third computing task according to the third load instruction, and the data is transferred from the external storage device to the first storage area. 16. The method according to claim 15, wherein the third input data comprises a plurality of third input sub-data, and the performing a ping-pong operation on the third input data in the third computing task and transferring the third input data from the external storage device to the first storage area comprises: estimating a target storage duration of each of the plurality of third input sub-data in the first storage area to obtain a plurality of target storage durations; The plurality of third input sub-data corresponding to the plurality of target storage durations are transmitted to the first storage area in a descending order of storage duration, and are stored from both ends to the middle of the first storage area.