CN114464534B - A superjunction high voltage device structure and manufacturing method - Google Patents
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Abstract
本发明公开了一种超结高压器件结构及制造方法，属于半导体分立器件技术领域，解决了现有技术中超结MOSFET器件雪崩击穿时寄生BJT引起的二次击穿效应的问题。本发明具体技术方案为，通过在超结高压器件的trench Gate之间增加了并联的二极管结构，且此二极管结构采用了逆向的浓度掺杂分布，形成两个间隔的P+区以弱化轻掺杂P型区的电场。本发明改善了超结MOSFET二极管导通状态下的注入效率，减少了少子注入，反向回复时间和反向回复电荷都得到有效降低；一定程度上避免了寄生NPN结构的开启导致的雪崩耐量降低，提高了抗浪涌能力。
The present invention discloses a superjunction high-voltage device structure and a manufacturing method, which belongs to the technical field of semiconductor discrete devices, and solves the problem of secondary breakdown effect caused by parasitic BJT during avalanche breakdown of superjunction MOSFET devices in the prior art. The specific technical solution of the present invention is to add a parallel diode structure between the trench gates of the superjunction high-voltage device, and this diode structure adopts a reverse concentration doping distribution to form two spaced P+ regions to weaken the electric field of the lightly doped P-type region. The present invention improves the injection efficiency of the superjunction MOSFET diode in the on state, reduces minority carrier injection, and effectively reduces the reverse recovery time and reverse recovery charge; to a certain extent, it avoids the reduction of avalanche tolerance caused by the opening of the parasitic NPN structure, and improves the surge resistance.
Description
技术领域Technical Field
本发明属于半导体分立器件技术领域，涉及一种超结高压器件结构及制造方法。The present invention belongs to the technical field of semiconductor discrete devices, and relates to a superjunction high voltage device structure and a manufacturing method.
背景技术Background Art
超结VDMOS是一种发展迅速、应用广泛的新型功率半导体器件。它在普通垂直双扩散金属氧化物半导体（VDMOS）基础上，引入超结（Superjunction）结构，使之即具有VDMOS输入阻抗高、开关速度快、工作频率高、电压控制、热稳定性好、驱动电路简单，又克服了VDMOS的导通电阻与击穿电压成2 .5次方关系急剧增加的缺点。目前超结VDMOS已广泛应用于电脑、手机、照明以及液晶或等离子电视机和游戏机等消费电子产品的电源或适配器。Superjunction VDMOS is a new type of power semiconductor device that is developing rapidly and widely used. It introduces a superjunction structure based on the ordinary vertical double diffused metal oxide semiconductor (VDMOS), which makes it have high input impedance, fast switching speed, high operating frequency, voltage control, good thermal stability, and simple driving circuit of VDMOS, and overcomes the disadvantage that the on-resistance of VDMOS increases sharply with the breakdown voltage to the power of 2.5. At present, superjunction VDMOS has been widely used in power supplies or adapters for consumer electronic products such as computers, mobile phones, lighting, LCD or plasma TVs, and game consoles.
尽管超结VDMOS器件相对与传统功率半导体器件具有显著的优势，但是也存在固有的缺陷，除了具有生产工艺难度大的先天缺点外，同时反向恢复特性相对与传统功率半导体器件差，主要表现为反向恢复峰值电流大，反向恢复系数高，反向恢复电荷大等，目前主要手段是通过增加辐照调节少子寿命的方式来调整。Although super junction VDMOS devices have significant advantages over traditional power semiconductor devices, they also have inherent defects. In addition to the inherent disadvantage of difficult production process, the reverse recovery characteristics are relatively poor compared to traditional power semiconductor devices, mainly manifested in large reverse recovery peak current, high reverse recovery coefficient, large reverse recovery charge, etc. The current main means of adjustment is to increase irradiation to adjust the minority carrier lifetime.
不论是传统高压平面VDMOS还是超结MOSFET器件雪崩击穿时寄生BJT引起的二次击穿效应严重制约了器件的雪崩能力，Pbody区附近不可避免地寄生着一个双极型晶体管BJT，Pbody区构成寄生BJT的基区，同时寄生BJT的集电极与发射极也分别为VDMOS的漏极和源极，此外寄生BJT存在从VDMOS源极到Pbody区的等效电阻RB。当VDMOS处于阻断状态时，随着漏源电压的增加，器件内部电场逐渐增大，泄漏电流也随之增大。部分泄漏电流流过BJT体区时，等效电阻RB两端产生压降，该压降等于寄生三极管BJT的VBE，VDMOS接近雪崩击穿时，泄漏电流急剧增大，如果RB上的压降足够使得寄生三极管开启，寄生BJT将引起二次击穿效应，导致器件烧毁失效。Whether it is a traditional high-voltage planar VDMOS or a super-junction MOSFET device, the secondary breakdown effect caused by the parasitic BJT during avalanche breakdown seriously restricts the avalanche capability of the device. A bipolar transistor BJT is inevitably parasitic near the Pbody region. The Pbody region constitutes the base region of the parasitic BJT. At the same time, the collector and emitter of the parasitic BJT are also the drain and source of the VDMOS respectively. In addition, the parasitic BJT has an equivalent resistance RB from the source of VDMOS to the Pbody region. When VDMOS is in a blocking state, as the drain-source voltage increases, the internal electric field of the device gradually increases, and the leakage current also increases. When part of the leakage current flows through the BJT body region, a voltage drop is generated across the equivalent resistance RB, which is equal to the VBE of the parasitic transistor BJT. When VDMOS is close to avalanche breakdown, the leakage current increases sharply. If the voltage drop on RB is sufficient to turn on the parasitic transistor, the parasitic BJT will cause a secondary breakdown effect, causing the device to burn out and fail.
发明内容Summary of the invention
基于现有技术中存在的上述问题，本发明具体提供了一种超结高压器件结构及制造方法。Based on the above problems existing in the prior art, the present invention specifically provides a super junction high voltage device structure and a manufacturing method.
一种超结高压器件的制造方法，具体包括以下步骤：A method for manufacturing a superjunction high voltage device comprises the following steps:
步骤1. 在N+衬底上生长一层外延层N-；Step 1. growing an epitaxial layer N- on an N+ substrate;
步骤2. 在外延层N-表面注入P型杂质硼，并退火形成PWELL区；Step 2. P-type impurity boron is implanted into the N-surface of the epitaxial layer and annealed to form a PWELL region;
步骤3. 在PWELL区的表面，通过Trench光刻板，刻蚀出深沟槽后生长一定浓度的P型外延，使之填充满沟槽，进行CMP工艺，将沟槽外的P型外延去掉，形成N柱P柱相交替的超结结构；Step 3. On the surface of the PWELL area, a deep trench is etched through a Trench lithography board, and then a certain concentration of P-type epitaxy is grown to fill the trench. The P-type epitaxy outside the trench is removed by a CMP process to form a super junction structure with alternating N-columns and P-columns;
步骤4. 在PWELL区的中心区域，通过光刻板刻蚀出寄生的二极管区域（4）；Step 4. In the central area of the PWELL region, a parasitic diode region (4) is etched out by photolithography.
步骤5.通过光刻及离子注入P型杂质硼；Step 5. P-type impurity boron is implanted by photolithography and ion implantation;
步骤6.通过外延工艺形成P型外延P-，使之填满二极管区域，进行CMP工艺，将表面多余的P型外延去掉，退火使步骤5注入的P型杂质硼形成两个间隔的重掺杂P+区域；Step 6. Form a P-type epitaxial P- through an epitaxial process to fill the diode area, perform a CMP process to remove the excess P-type epitaxial on the surface, and anneal to form two spaced heavily doped P+ regions with the P-type impurity boron injected in step 5;
步骤7.通过Trench Gate光刻版刻蚀出栅极区域的沟槽，氧化生长一层薄牺牲氧化层后将之去除，生长栅氧化层，淀积多晶硅并刻蚀后形成器件的栅极；Step 7. Etch a trench in the gate region using a Trench Gate photolithography plate, oxidize and grow a thin sacrificial oxide layer and then remove it, grow a gate oxide layer, deposit polysilicon and etch to form the gate of the device;
步骤8.利用N+源区光刻版注入并退火形成器件的源极，淀积ILD介质层）,通过接触孔光刻刻蚀出器件的源极接触孔，淀积金属形成器件的正面金属化。Step 8. Use the N+ source region photomask to implant and anneal to form the source of the device, deposit the ILD dielectric layer), etch the source contact hole of the device through contact hole photolithography, and deposit metal to form the front metallization of the device.
步骤4中，所述刻蚀深度小于Trench Gate的刻蚀深度。In step 4, the etching depth is less than the etching depth of the trench gate.
步骤5中，P型杂质硼注入位置为二极管区域底部。In step 5, the P-type impurity boron is implanted at the bottom of the diode region.
步骤5中，P型杂质硼在二极管区域底部两侧对称注入。In step 5, P-type impurity boron is implanted symmetrically on both sides of the bottom of the diode region.
步骤7中，栅极区域的沟槽的位置为二极管区域与PWELL区交界，刻蚀深度大于步骤6所述的重掺杂P+区域。In step 7 , the position of the trench in the gate region is the boundary between the diode region and the PWELL region, and the etching depth is greater than that of the heavily doped P+ region described in step 6 .
步骤8中，所述源极接触孔的位置为中心区域。In step 8, the source contact hole is located in the central area.
如上述制造方法制得的一种超结高压器件。A superjunction high voltage device manufactured by the above manufacturing method.
相较于现有技术，本发明具有以下有益效果：Compared with the prior art, the present invention has the following beneficial effects:
本发明通过在超结MOSFET的Trench Gate之间增加二极管结构，改善了超结MOSFET二极管导通状态下的注入效率，减少了少子注入，反向回复时间和反向回复电荷都得到有效降低；同时由于增加的二极管结构不包含N+源区，发生雪崩时分走了部分雪崩电流，一定程度上避免了寄生NPN结构的开启导致的雪崩耐量降低，提高了抗浪涌能力。The present invention improves the injection efficiency of the super junction MOSFET diode in the on state by adding a diode structure between the trench gates of the super junction MOSFET, reduces minority carrier injection, and effectively reduces the reverse recovery time and the reverse recovery charge; at the same time, because the added diode structure does not include an N+ source region, part of the avalanche current is diverted when an avalanche occurs, which to a certain extent avoids the reduction in avalanche tolerance caused by the opening of a parasitic NPN structure, and improves the surge resistance.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为本发明步骤1的示意图。FIG1 is a schematic diagram of step 1 of the present invention.
图2为本发明步骤2的示意图。FIG. 2 is a schematic diagram of step 2 of the present invention.
图3为本发明步骤3的示意图。FIG. 3 is a schematic diagram of step 3 of the present invention.
图4为本发明步骤4的示意图。FIG. 4 is a schematic diagram of step 4 of the present invention.
图5为本发明步骤5的示意图。FIG. 5 is a schematic diagram of step 5 of the present invention.
图6为本发明步骤6的示意图。FIG. 6 is a schematic diagram of step 6 of the present invention.
图7为本发明步骤7的示意图。FIG. 7 is a schematic diagram of step 7 of the present invention.
图8为本发明步骤8的示意图。FIG. 8 is a schematic diagram of step 8 of the present invention.
图中，1-外延层N-，2-PWELL区，3-P型外延，4-二极管区域，5-P型杂质硼，6- P型外延P-，7-栅氧化层，8-栅极，9-源极，10-ILD介质层，11-正面金属化。In the figure, 1-epitaxial layer N-, 2-PWELL region, 3-P-type epitaxy, 4-diode region, 5-P-type impurity boron, 6-P-type epitaxy P-, 7-gate oxide layer, 8-gate, 9-source, 10-ILD dielectric layer, 11-front metallization.
具体实施方式DETAILED DESCRIPTION
本发明提供了一种超结高压器件结构及制造方法，通过在超结高压器件的trenchGate之间增加了并联的二极管结构，且此二极管结构采用了逆向的浓度掺杂分布，形成两个间隔的P+区以弱化轻掺杂P型区的电场。The present invention provides a super junction high voltage device structure and a manufacturing method, by adding a parallel diode structure between the trench gates of the super junction high voltage device, and the diode structure adopts a reverse concentration doping distribution to form two spaced P+ regions to weaken the electric field of the lightly doped P-type region.
一种超结高压器件结构及制造方法，具体实现方法如下：A superjunction high voltage device structure and manufacturing method, the specific implementation method is as follows:
1. 在N+衬底上生长一层外延层N- 1。1. Grow an epitaxial layer N-1 on the N+ substrate.
2. 在外延层N-1最表面注入P型杂质硼，并退火形成PWELL区2。2. P-type impurity boron is implanted into the outermost surface of the epitaxial layer N-1 and annealed to form PWELL region 2.
3. 在PWELL区2的表面，通过Trench光刻板，刻蚀出深沟槽后生长一定浓度的P型外延3，使之填充满沟槽，进行CMP工艺，将沟槽外的P型外延去掉，形成N柱P柱相交替的超结结构。3. On the surface of the PWELL area 2, a deep trench is etched through a Trench lithography board, and then a certain concentration of P-type epitaxy 3 is grown to fill the trench. A CMP process is performed to remove the P-type epitaxy outside the trench to form a super junction structure with alternating N-columns and P-columns.
4. 在PWELL区2的中心区域，通过光刻板刻蚀出寄生的二极管区域4，刻蚀深度小于Trench Gate的刻蚀深度。4. In the central area of the PWELL area 2, a parasitic diode area 4 is etched out through a photolithography board, and the etching depth is less than the etching depth of the Trench Gate.
5.通过光刻及离子注入P型杂质硼5。5. P-type impurity boron 5 is implanted by photolithography and ion implantation.
6.通过外延工艺形成P型外延P- 6，使之填满二极管区域，进行CMP工艺，将表面多余的P型外延去掉，适当退火使步骤5注入的P型杂质硼形成两个间隔的重掺杂P+区域5。6. Form a P-type epitaxial P-6 through an epitaxial process to fill the diode area, perform a CMP process to remove the excess P-type epitaxial on the surface, and perform appropriate annealing to allow the P-type impurity boron injected in step 5 to form two spaced heavily doped P+ regions 5.
7.通过Trench Gate光刻版刻蚀出栅极区域的沟槽，氧化生长一层薄牺牲氧化层后将之去除，生长栅氧化层7，淀积多晶硅并刻蚀后形成器件的栅极8。7. A trench in the gate region is etched using a Trench Gate photolithography plate, a thin sacrificial oxide layer is grown by oxidation and then removed, a gate oxide layer 7 is grown, polysilicon is deposited and etched to form the gate 8 of the device.
8.利用N+源区光刻版注入并退火形成器件的源极9，淀积ILD介质层10,通过接触孔光刻刻蚀出器件的源极接触孔，淀积金属形成器件的正面金属化11。8. Use the N+ source region photomask to implant and anneal to form the source 9 of the device, deposit the ILD dielectric layer 10, etch the source contact hole of the device through contact hole photolithography, and deposit metal to form the front metallization 11 of the device.
本发明所制备得到的超结高压器件结构，两个P+区之间的间隔区域刻蚀接触孔，既保证了击穿电压的大小，又有效的减小了少子的注入效率，使反向恢复特性得到改善。同时雪崩时此并联二极管起到分流作用，一定程度上避免了寄生NPN结构的开启，提高了雪崩耐量。The superjunction high-voltage device structure prepared by the present invention has a contact hole etched in the interval area between the two P+ regions, which not only ensures the size of the breakdown voltage, but also effectively reduces the injection efficiency of minority carriers, thereby improving the reverse recovery characteristics. At the same time, during avalanche, the parallel diode plays a shunt role, which to a certain extent avoids the opening of the parasitic NPN structure and improves the avalanche tolerance.
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明主要技术方案的精神实质所做的修饰，都应涵盖在本发明的保护范围之内。The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any modifications made according to the spirit of the main technical solution of the present invention should be included in the protection scope of the present invention.
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