CN206742247U - Semiconductor devices - Google Patents

Abstract

The utility model discloses a kind of semiconductor devices, the device includes active region, terminal area, epitaxial layer and the N-type region domain formed on said epitaxial layer there；Multiple groove structures are disposed with the N-type region domain, wherein being the terminal area close to a groove region of the N-type edges of regions, remaining groove region is the active region.Semiconductor devices effectively reduces the conduction voltage drop of trench gate Schottky diode in the prior art in the utility model, and its epitaxy technique is simple, and precision is easily controllable；The pressure-resistant robustness for being more than cellular voltage, enhancing device of device terminal can be realized.

Description

Semiconductor device

technical field

The utility model relates to the technical field of semiconductors, in particular to a semiconductor device.

Background technique

Schottky diodes are widely used as power rectification devices in switching power supplies and other high-speed power switching devices. Compared with PN junction diodes, Schottky diodes have a lower conduction voltage drop, and because they are unipolar carrier devices, they have faster switching frequencies, so Schottky diodes are used in low-voltage, high-frequency applications Range has great advantages.

Due to the barrier lowering effect of Schottky itself, Schottky will generate a large leakage current at high voltage, which is the main reason for limiting the application of Schottky diodes in high voltage fields. In recent years, with the successful marketization of TMBS (Trench MOS Barrier Schottky Rectifier, trench gate Schottky diode), the Schottky voltage application range has reached 300V. Compared with the planar gate Schottky diode, by introducing a trench structure, The surface barrier lowering effect of the Schottky is well suppressed, and the leakage current of the device is reduced. Another factor that limits the application of high-voltage trench-gate Schottky diodes is that the resistivity of bulk silicon is very large. The higher the withstand voltage of the device, the greater the resistivity of bulk silicon required, which makes the forward voltage drop of the device larger.

In order to obtain a lower conduction voltage drop, the prior art adopts a vertically variable doping structure, and the vertical electric field in the body is flat when the device reverses the withstand voltage, so that the device has a higher withstand voltage, and the device obtains a higher voltage under the same breakdown voltage. Low VF (conduction voltage drop). However, in order to obtain this vertically variable doping device structure, the required epitaxy process is complex, the precision is difficult to control, and the practical application is difficult.

Contents of the invention

In order to overcome the above defects, the technical problem to be solved by the utility model is to provide a semiconductor device for reducing the conduction voltage drop of the trench gate Schottky diode.

In order to solve the above technical problems, a semiconductor device in the utility model, the device includes an active region, a terminal region, an epitaxial layer and an N-type region formed on the epitaxial layer; the N-type region is arranged in an arrangement There are a plurality of groove structures, wherein the region where a groove near the edge of the N-type region is located is the terminal region, and the regions where other grooves are located are the active region.

Optionally, the trench width of the termination region is larger than any trench width of the active region.

Optionally, each trench is provided with a gate oxide layer, and a polysilicon layer is provided on the gate oxide layer.

Specifically, the thickness of the gate oxide layer is determined by a preset withstand voltage value of the semiconductor device.

Optionally, the device further includes a metal layer disposed on the surface.

Optionally, the N-type region has a Gaussian distribution.

Optionally, the doping concentration of the N-type region is greater than that of the epitaxial layer.

Optionally, the trench in the terminal region is provided with a passivation layer.

Specifically, the material of the passivation layer is one or a combination of the following: silicon nitride and silicon dioxide.

Optionally, the trench width of the termination region is determined by a preset withstand voltage value of the semiconductor device.

The beneficial effects of the utility model are as follows:

The semiconductor device in the utility model effectively reduces the turn-on voltage drop of the trench grid Schottky diode in the prior art, and its epitaxial process is simple, and the precision is easy to control; it can realize that the withstand voltage of the device terminal is greater than the cell voltage, and the robustness of the device is enhanced. Stickiness.

Description of drawings

Fig. 1 is the sectional view of semiconductor device in the utility model embodiment;

Fig. 2 is the flow chart of the manufacturing method of semiconductor device in the utility model embodiment;

3-7 are cross-sectional views of semiconductor materials corresponding to each step in the manufacturing method in the embodiment of the present invention;

8-9 are schematic diagrams of the simulation effect of the semiconductor device in the embodiment of the present invention.

detailed description

In order to solve the problems of the prior art, the utility model provides a semiconductor device and a manufacturing method. The utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model, not to limit the utility model.

As shown in FIG. 1 , an embodiment of the present invention provides a semiconductor device, which includes an active region 10, a termination region 11, an epitaxial layer 2, and an N-type region 5 formed on the epitaxial layer; the N A plurality of trench structures are arranged on the N-type region 5 , where a trench near the edge of the N-type region 5 is located in the terminal region 11 , and other trenches are located in the active region 10 . Furthermore, the N-type region 5 is photoetched with a plurality of groove structures arranged in a ring.

Optionally, each trench is provided with a gate oxide layer 6 , and a polysilicon layer 7 is provided on the gate oxide layer 6 ; wherein the trench width of the terminal region is larger than any trench width of the active region. Furthermore, a gate oxide layer 6 is grown in each trench, and an anti-etched polysilicon layer 7 is deposited in each trench in the active region, and an anti-etched polysilicon layer is also deposited on the sidewall of the trench in the terminal region. .

Specifically, the thickness of the gate oxide layer is determined by a preset withstand voltage value of the semiconductor device.

Optionally, the device further includes a metal layer 9 disposed on the surface;

The N-type region has a Gaussian distribution;

The doping concentration of the N-type region is greater than the doping concentration of the epitaxial layer;

The trenches of the termination region are provided with a passivation layer 8 .

Wherein, the doping concentration of the N-type region is greater than that of the epitaxial layer, which can effectively reduce the JFET effect between adjacent trenches in the active region 10 and reduce the on-voltage drop of the device.

Furthermore, a metal layer is sputtered on the surface of the semiconductor device, thereby forming a Schottky contact with the semiconductor N-type region in the active region, and serving as a metal field plate in the terminal region.

Specifically, the material of the passivation layer is one or a combination of the following: silicon nitride and silicon dioxide.

Optionally, the trench width of the termination region is determined by a preset withstand voltage value of the semiconductor device.

The semiconductor device in the embodiment of the utility model effectively reduces the conduction voltage drop of the trench gate Schottky diode in the prior art, the epitaxy process is simple, and the precision is easy to control; the terminal withstand voltage of the device can be greater than the cell voltage, and the device's performance is enhanced. robustness.

Briefly describe the manufacturing method of semiconductor device in the utility model below, as shown in Figure 2, described method comprises:

S101, performing ion implantation on the surface of the semiconductor material to form an N-type region on the epitaxial layer of the semiconductor material;

S102 , performing wafer trench etching on the N-type region to form an active region with a plurality of trenches arranged and a terminal region of one trench.

The epitaxial process of the embodiment of the utility model is simple, and the precision is easy to control. The semiconductor device manufactured by it can effectively reduce the conduction voltage drop of the trench gate Schottky diode in the prior art; the robustness of the device.

Optionally, the ion implantation energy is between 30KEV-120KEV; the ion implantation meter is between 10 ¹¹ and 10 ¹³ cm ⁻² ; the ions are N-type dopant sources or P-type dopant sources.

Optionally, the N-type region has a Gaussian distribution; the doping concentration of the N-type region is greater than the doping concentration of the epitaxial layer;

The ion implantation on the surface of the semiconductor material to form an N-type region on the epitaxial layer of the semiconductor material includes:

growing a first oxide layer on the epitaxial layer of semiconductor material;

Ion implantation is performed on the surface of the oxide layer, and high-temperature annealing is performed to activate, so that an N-type region and a second oxide layer are formed on the epitaxial layer.

Wherein the trench width of the termination region is larger than any trench width of the active region.

Further, performing wafer trench etching on the N-type region to form an active region with a plurality of trenches arranged and a terminal region of a trench, including:

Using the second oxide layer as an etching barrier layer, photoetching a plurality of trenches in the N-type region;

growing a gate oxide layer on each trench according to a preset thickness;

After the growth of the gate oxide layer is completed, polysilicon deposition is performed;

Reverse etching the deposited polysilicon, leaving a polysilicon layer in the trench of the active region, and leaving a polysilicon layer on the sidewall of the trench in the terminal region;

A passivation layer is deposited on the active region and the terminal region, and the passivation layer of the active region is etched away to serve as a Schottky contact point.

That is to say, in the embodiment of the present invention, a passivation layer is deposited on the surface of the device, photolithography and etching processes are performed, the passivation layer in the terminal area is retained, and the passivation layer in the active region is etched away as the Schottky Contact point.

Further, after depositing the passivation layer in the trench of the terminal region, it further includes:

A metal layer is sputtered on the surface of the semiconductor device.

That is to say, a metal layer is sputtered on the semiconductor device to form a Schottky contact with the semiconductor N-type region in the active region, and serve as a metal field plate in the terminal region.

The above method will be described in detail below.

Based on the research on the prior art, the inventors of the present application found that for the trench-gate Schottky diode, when conducting forward conduction, the entire bulk silicon in the MESA (platform) region participates in the transport of current, and the gap between the adjacent trenches is The bulk silicon region can form a JFET (Junction Field-Effect Transistor) region. Therefore, the use of high-concentration ion implantation technology in the JFET region can significantly reduce the on-resistance in this region, thereby reducing the on-voltage drop of the device.

Specifically:

Step 1, first grow an oxide layer 1 (i.e. the first oxide layer) of about 500 Å on the epitaxial layer 2 of the semiconductor material as a buffer layer for ion implantation, as shown in Figure 3, the semiconductor material includes highly doped single Crystalline substrate 3 (N+) and low doped epitaxial layer 2 (N-).

Step 2, perform ion implantation on the surface of the epitaxial layer 2. For N-type Schottky, the ion source can be PH3, AsH3, etc., the ion implantation energy is between 30KEV-120KEV, and the ion implantation dose is between 1011～1013cm-2 . Then thermal annealing pushes the junction, as shown in Figure 4, forms a moderately doped N layer 5 (ie N-type region) with a Gaussian distribution on the low-doped epitaxial layer 2, and grows a thick oxide layer at the same time during the push-junction process 4 (ie the second oxide layer). Wherein, the doping concentration of the N-type region is between the N+ layer and the N-layer, that is, the N-layer has the lowest doping concentration.

Step 3: Carry out the photolithography of the trench structure for the first time on the semiconductor, and use the thick oxide layer 4 as an etching barrier layer to etch out a ring-shaped regularly arranged trench structure as shown in Figure 5. The semiconductor The structural trench depth does not have to be greater than the highly doped N layer 5 . For example, the interval width between the trenches is the same, and the width of each trench in the active region is the same.

Step 4, grow a gate oxide layer 6 on each trench, the thickness of the gate oxide layer is determined by the withstand voltage of the device, and then perform polysilicon deposition and reverse etching to form as shown in Figure 6. polysilicon layer 7 .

Step 5, deposit a passivation layer 8 on the surface of the semiconductor device, the passivation layer can be silicon nitride or silicon dioxide, and then hole photolithography, etching out the terminal region 11, as shown in Figure 7, in the edge Region 10 is also partially covered by passivation layer 8 .

Step 6, sputtering the metal layer 9 on the semiconductor material, then photolithography and etching, and the final morphology is as shown in Figure 1, thus completing the manufacture.

In the method of the embodiment of the present invention, a layer of ion implantation is performed on the surface before the wafer groove etching process. The ion source can be N-type dopant source PH ₃ , AsH ₃ , or P-type dopant source BF ₃ , BCl ₃ , etc., the ion implantation energy is between 30KEV-120KEV, and the ion implantation dose is 10 ¹¹ ~ 10 ¹³ cm Between ^-2 .

That is to say, the method in the embodiment of the present invention is mainly to perform ion implantation on the chip, and form a layer of moderately doped N-type region with Gaussian distribution doping on the surface of the N-region of the epitaxial layer, which will significantly reduce the gap between the trenches. The resistance of the JFET in the MESA region between them will reduce the turn-on voltage drop of the device. Taking the 100V trench gate Schottky diode as an example, the ion implantation dose is 10 ¹² cm ^-2 , the implantation energy is 80KEV, and the electrical characteristics of the conventional device and the device of the utility model are simulated by the device simulation software. Figure 8 shows the VF of the two devices Comparing the characteristic curves, it can be seen that compared with conventional devices, the turn-on voltage of the device of the utility model is greatly improved. Fig. 9 is a comparison of the BV characteristic curves of two devices, and the leakage current of the device of the utility model is basically the same as that of the conventional device. Therefore, the semiconductor device proposed by the utility model can significantly improve the turn-on voltage drop of the device and has little influence on other characteristics of the device.

Compared with the conventional trench gate Schottky diode process, the method proposed by the embodiment of the utility model only needs to add an ion implantation process, and the process is simple and easy to implement.

The method proposed by the embodiment of the utility model can improve the reliability performance of the device. Combined with the wide-groove terminal structure 11 in Figure 1, the terminal structure digs out the ion implantation enhancement region 5 in the active region 10, which can achieve a device terminal withstand voltage greater than the cell voltage and enhance the robustness of the device.

Although the application describes specific examples of the present invention, those skilled in the art can devise variations of the present invention without departing from the concept of the present invention. Under the inspiration of the technical concept of the utility model, those skilled in the art can also make various improvements to the utility model without departing from the content of the utility model, which still falls within the protection scope of the utility model.

Claims (10)

1. A semiconductor device, characterized in that the device comprises an active region, a terminal region, an epitaxial layer, and an N-type region formed on the epitaxial layer; a plurality of grooves are arranged on the N-type region structure, wherein the area where a trench near the edge of the N-type area is located is the terminal area, and the area where other trenches are located is the active area. 2. The device of claim 1, wherein a trench width of the termination region is greater than any trench width of the active region. 3. The device according to claim 1, wherein each trench is provided with a gate oxide layer, and a polysilicon layer is provided on the gate oxide layer. 4. The device according to claim 3, wherein the thickness of the gate oxide layer is determined by a preset withstand voltage value of the semiconductor device. 5. The device according to any one of claims 1-4, further comprising a metal layer disposed on the surface. 6. The device according to any one of claims 1-4, wherein the N-type region has a Gaussian distribution. 7. The device according to any one of claims 1-4, wherein the doping concentration of the N-type region is greater than the doping concentration of the epitaxial layer. 8. The device according to any one of claims 1-4, wherein a passivation layer is provided in the trench of the terminal region. 9. The device according to claim 8, wherein the material of the passivation layer is one or a combination of the following: silicon nitride and silicon dioxide. 10. The device according to any one of claims 1-4, wherein the trench width of the termination region is determined by a preset withstand voltage value of the semiconductor device.