CN103560086B - The preparation method of the super-junction semiconductor device of avalanche capacity can be improved - Google Patents

Abstract

The invention relates to a preparation method of a super junction semiconductor device capable of improving avalanche capability. The traditionally higher doping concentration of the P-column aggravates the lateral diffusion and increases the on-resistance accordingly, and the charge imbalance between the P-column and the N-column reduces the breakdown voltage. The present invention utilizes the epitaxial process to form an N-type epitaxial layer; performs boron ion implantation to form a P-type N-type epitaxial layer; the dose of boron ion implantation increases successively, and then pushes the junction at a high temperature to form a P-type and N-type alternate epitaxial layer; implants boron Ions form the Pbody region; use dry etching polysilicon to form polysilicon gate electrodes; implant arsenic ions to form N+ source regions; deposit a layer of aluminum on the upper surface of the entire device, and etch the aluminum to form source metal electrodes, and back metallization to form drain electrode. The super junction semiconductor device obtained by the invention improves the avalanche capability of the super junction semiconductor device and reduces the on-resistance at the same time.

Description

Preparation method of super junction semiconductor device capable of improving avalanche capability

technical field

The invention belongs to the field of semiconductor devices and process manufacturing, and in particular relates to a preparation method of a super junction semiconductor device capable of improving avalanche capability.

Background technique

Super junction VDMOS is a new type of power semiconductor device with rapid development and wide application. It introduces a superjunction (Superjunction) structure on the basis of ordinary vertical double-diffused metal oxide semiconductor (VDMOS), so that it has VDMOS high input impedance, fast switching speed, high operating frequency, voltage control, good thermal stability, and drive The circuit is simple, and overcomes the shortcoming that the on-resistance of VDMOS and the breakdown voltage increase sharply in the relationship of 2.5 powers. At present, super-junction VDMOS has been widely used in power supplies or adapters of consumer electronics products such as computers, mobile phones, lighting, LCD or plasma TVs and game consoles.

For power semiconductor devices, avalanche energy is usually measured under the condition of unclamped inductive switching UIS. There are two modes of avalanche damage under UIS operating conditions, thermal damage and parasitic transistor conduction damage. Thermal damage is the burning failure of power devices due to the increase in power consumption caused by the increase in junction temperature under the action of power pulses, and the junction temperature rises to the critical value allowed by the characteristics of the silicon chip.

The secondary breakdown effect caused by the parasitic BJT during VDMOS avalanche breakdown seriously restricts the avalanche capability of VDMOS devices. See Figure 1 for the structure of super-junction VDMOS and the schematic diagram of parasitic triodes. A bipolar transistor BJT is inevitably parasitic near the Pbody region. , the Pbody region constitutes the base region of the parasitic BJT, and the collector and emitter of the parasitic BJT are also the drain and source of the VDMOS respectively. In addition, the parasitic BJT has an equivalent resistance _RB from the source of the VDMOS to the Pbody region. When VDMOS is in the blocking state, as the drain-source voltage increases, the internal electric field of the device gradually increases, and the leakage current also increases. When part of the leakage current flows through the body region of the BJT, a voltage drop occurs at both ends of the equivalent resistance _RB , which is equal to the V _BE of the parasitic transistor BJT. When _VDMOS is close to avalanche breakdown, the leakage current increases sharply. The voltage drop is enough to turn on the parasitic triode, and the parasitic BJT will cause secondary breakdown effect. The equivalent resistance _RB increases with temperature, and the turn-on voltage V _BE of the emitter and base decreases with the increase of temperature. Therefore, the avalanche capability of VDMOS decreases with the increase of temperature. Unlike the secondary breakdown of bipolar transistors, the secondary breakdown of VDMOS generally only occurs when it is in a high-voltage, high-current working state, and there is no local hot spot.

When the avalanche breakdown of VDMOS occurs and the parasitic triode is activated and turned on to cause secondary breakdown, VDMOS also has a sharp heating phenomenon. When avalanche breakdown occurs, the temperature of the device is related to the magnitude of the current and the performance of the device itself. When the device undergoes avalanche breakdown, if there is no proper buffering and suppression improvement measures, as the voltage and current increase, the heat dissipation capability of the device will become worse and worse, and the temperature will rise sharply, which will cause damage to the device. The parasitic triode may also cause the single event burnout (SEB) phenomenon of the power MOSFET. The so-called single event burnout refers to the local avalanche breakdown phenomenon formed by the internal parasitic triode being opened under the induction of the heavy ion ionization track. This effect seriously threatens aerospace. and the safety of satellite electronic systems.

The main measures to suppress the secondary breakdown of VDMOS are: increase the junction depth and concentration of Pbody, and reduce the resistance _RB . For parasitic BJT, by increasing the concentration of Pbody, the net doping concentration Q _B of the base region is increased, and by increasing the junction depth of Pbody, for parasitic BJT, that is, the width W of the undepleted base region is increased. It can reduce the current amplification factor β, and the secondary breakdown point increases with the increase of Pbody concentration. The traditional solution is to implant P ⁺ ions deeply into the P body region, but this structure makes the junction depth of the P body region deeper and increases the on-resistance of VDMOS. In 1995, K. Fischer and K. Shenai published an article, which proposed that adding a self-aligned shallow surface diffusion P ⁺ region can effectively suppress the parasitic transistor effect, and reduce the current gain and base resistance without consuming Additional epi layer thickness. However, it should be pointed out that although the self-aligned shallow surface diffusion P ⁺ region suppresses the parasitic effect and does not increase the cell area, it increases the possibility of punch-through breakdown, so the production needs to be weighed in combination with the specific device working conditions.

Avalanche breakdown occurs in the cell region than in the terminal region to obtain better reliability, and the breakdown voltage of the cell region can be designed and realized more easily than that of the terminal region. Therefore, in order to improve the super junction device Therefore, it is easier to appropriately reduce the design margin of the breakdown voltage of the cell region than to further increase the breakdown voltage of the terminal region. Using a higher P-column doping concentration can appropriately improve the avalanche capability of power semiconductor devices, but a higher P-column doping concentration intensifies the lateral diffusion and increases the on-resistance accordingly, and the charge imbalance between the P-column and N-column resulting in a reduction in breakdown voltage.

Contents of the invention

The technical problem to be solved by the present invention is to provide a preparation method of a super junction semiconductor device that can improve the avalanche capability, and the super junction semiconductor device obtained by this method improves the avalanche capability of the super junction semiconductor device while reducing the conduction resistance.

In order to solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a method for preparing a super junction semiconductor device capable of improving avalanche capability, which is special in that it is realized by the following steps:

Step 1. Using an epitaxial process, a layer of 3-10 μm N-type epitaxial layer is formed on the N ⁺ substrate;

Step 2, using the P-pillar mask to perform boron ion implantation to form a P-type N-type epitaxial layer with a thickness of 3-6 μm;

Step 3: Repeat step 1 and step 2 5-10 times respectively, while increasing the dose of boron ion implantation by 2%-8% step by step, and then push the junction at 900-1200°C to form a P-type and N-type with a thickness of 30-40μm Alternating epitaxial layers, wherein the doping concentration range of the N-type epitaxial layer is 0.5~2.5×10 ¹⁵ cm ^-3 , and the doping concentration range of the P column in the cell area is 1.0~5.5×10 ¹⁵ cm ^-3 ;

Step 4: Using 50~200KeV energy implantation dose as 2~8×10 ¹³ cm ^-2 boron ions, and pushing the junction at a high temperature of 900~1200°C for 60~200 minutes to form the Pbody region;

Step 5, growing a gate oxide layer (6) with a thickness of 50 to 200 nm in dry oxygen for 90 minutes at a temperature of 1000 to 1200 ° C, and then depositing polysilicon with a thickness of 200 to 800 nm, and etching the polysilicon by dry method to form a polysilicon gate electrode;

Step 6, using 80KeV energy to implant arsenic ions with a dose of 3×10 ¹⁵ cm ⁻² , and pushing the junction at 900° C. for 30 minutes to form an N ⁺ source region;

Step 7, depositing a 2-4 μm thick BPSG layer, reflowing for 30-60 minutes under a nitrogen atmosphere at 900-1000°C, and etching to form a contact hole;

Step 8: Deposit a layer of aluminum on the upper surface of the entire device, etch the aluminum to form a source metal electrode, passivate, and metallize the back to form a drain electrode.

In the third step, the doping concentration of boron ions in different regions of the P-pillar is controlled by adjusting the mask plate of the P-pillar. The doping concentration in the middle of the P-pillar is the highest, and the doping concentration decreases toward both sides;

In the step 3, the doping concentration in the longitudinal direction of the P column is controlled by increasing the implantation dose of boron ions successively, the doping concentration at the bottom of the P column is the lowest, and the doping concentration gradually increases from bottom to top;

The P-pillar mask of each P-pillar is composed of a group of adjacent patterns, and the interval between different P-pillars is greater than the width of the P-pillar;

The pattern of the ion implantation region of each set of P-pillar mask plates is a manufacturable regular pattern.

The width of the pattern of the ion implantation region of each set of P-pillar mask plates gradually decreases from the center of the P-pillar to both sides.

The manufacturable regular pattern is strip, circle or square.

Compared with prior art, the beneficial effect of the present invention:

A method for preparing a super-junction semiconductor device of the present invention gradually increases the vertical doping concentration of the P-column of the super-junction VDMOS device from bottom to top, thereby reducing the equivalent resistance _RB of the parasitic BJT below the source metal electrode Resistance value, and make the avalanche current transfer from the base area of the parasitic BJT to the body along the P column, thereby greatly inhibiting the opening of the emitter junction of the parasitic BJT and avoiding the secondary breakdown caused by the parasitic BJT; and the The P column uses a mask to adjust the implantation dose in the middle and edge of the P column, which reduces the doping concentration in the edge area of the P column, thereby reducing the doping concentration gradient at the edge of the P column, effectively reducing the lateral diffusion. Therefore, the effective width of the conductive channel when the device is turned on is increased, thereby reducing the on-resistance while improving the avalanche capability of the superjunction semiconductor device; the present invention is compatible with the existing multiple epitaxy and multiple injection processes, and improves The avalanche capability does not increase the process manufacturing cost and process steps.

Description of drawings

FIG. 1 is a schematic diagram of the structure of an existing super-junction semiconductor device and the equivalent structure of a parasitic triode;

Fig. 2 is a schematic cross-sectional structure diagram of a super junction semiconductor device formed by multiple epitaxy and multiple implantation processes of the present invention;

Fig. 3 is a schematic structural diagram of a P-pillar photolithography mask plate in the cell region of the present invention;

Fig. 4 is the net doping concentration distribution figure along AA ' line in Fig. 2;

Fig. 5 is a diagram of net doping concentration distribution along line BB' in Fig. 2 .

Among them, 1. N ⁺ substrate, 2, N-type epitaxial layer, 3, P column, 4, Pbody region, 5, N ⁺ source region, 6, gate oxide layer, 7, polysilicon gate electrode, 8, BPSG dielectric layer , 9, source metal electrode, 10, boron ion implantation region.

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

A method for preparing a super junction semiconductor device capable of improving avalanche capability, which is realized by the following steps:

Step 1. Using an epitaxial process, a layer of 3-10 μm N-type epitaxial layer 2 is formed on the N ⁺ substrate 1;

Step 2, using the P-pillar mask to perform boron ion implantation to form a P-type N-type epitaxial layer with a thickness of 3-6 μm;

Step 3: Repeat step 1 and step 2 5-10 times respectively, while increasing the dose of boron ion implantation by 2%-8% step by step, and then push the junction at 900-1200°C to form a P-type and N-type with a thickness of 30-40μm Alternating epitaxial layers, wherein the doping concentration range of the N-type epitaxial layer 2 is 0.5~2.5×10 ¹⁵ cm ^-3 , and the doping concentration range of the P column in the cell region is 1.0~5.5×10 ¹⁵ cm ^-3 ;

Step 4: Using 50-200KeV energy implant dose to be 2-8×10 ¹³ cm ^-2 boron ions, and pushing the junction at a high temperature of 900-1200°C for 60-200 minutes to form Pbody region 4;

Step 5, growing a gate oxide layer 6 with a thickness of 50 to 200 nm in dry oxygen for 90 minutes at a temperature of 1000 to 1200 ° C, and then depositing polysilicon with a thickness of 200 to 800 nm, and etching the polysilicon by dry method to form a polysilicon gate electrode 7 ;

Step 6: Implanting arsenic ions with a dose of 3×10 ¹⁵ cm ^-2 with an energy of 80 KeV, and pushing the junction at 900° C. for 30 minutes to form an N ⁺ source region 5 ;

Step 7, depositing a 2-4 μm thick BPSG layer, reflowing for 30-60 minutes under a nitrogen atmosphere at 900-1000°C, and etching to form a contact hole;

Step 8: Deposit a layer of aluminum on the upper surface of the entire device, etch the aluminum to form a source metal electrode, passivate, and metallize the back to form a drain metal electrode 9 .

In the third step, the doping concentration of boron ions in different regions of the P-pillar is controlled by adjusting the mask plate of the P-pillar.

In the third step, the doping concentration in the longitudinal direction of the P column is controlled by increasing the implantation dose of boron ions successively, the doping concentration at the bottom of the P column is the lowest, and the doping concentration gradually increases from bottom to top.

The P-pillar mask of each P-pillar is composed of a group of adjacent patterns, and the interval between different P-pillars is greater than the width of the P-pillar.

The pattern of the ion implantation area of each group of P-pillar mask plates can be strip, circle or square or other manufacturable regular patterns.

The width of the pattern of the ion implantation region of each set of P-pillar mask plates gradually decreases from the center of the P-pillar to both sides.

By adjusting the size, number and spacing of the ion implantation patterns of the P-pillar mask, the boron ion doping concentration in different regions of the P-pillar is controlled. The strip pattern in the middle of the P-pillar mask is the widest, and the width of the pattern extends to both sides of the P-pillar. Decrease in order, so that the number of ions obtained after doping is the largest in the middle, and then decrease to both sides.

The working principle of the present invention is: the doping concentration at the top of the P column below the source metal electrode 9 is the highest, thereby reducing the resistance value of the equivalent resistance _RB of the parasitic BJT below the source metal electrode 9, and making the avalanche current flow from the parasitic BJT The base region of the P-pillar is transferred to the body along the P-pillar, thereby greatly suppressing the opening of the emitter junction of the parasitic BJT and avoiding the secondary breakdown caused by the parasitic BJT; by adjusting the pattern of the P-pillar mask, different The continuous pattern of the mask makes the dose of boron ions implanted in the middle of the P-pillar 3 the largest, and its lateral doping concentration gradually decreases to both sides through long-term high-temperature push junction, and the doping concentration in the middle of the P-pillar and the edge of the P-pillar is adjusted. The lateral diffusion is effectively reduced, and the effective width of the conduction channel when the device is turned on is increased, thereby improving the avalanche capability of the super junction semiconductor device and reducing the on-resistance at the same time.

See Figure 1. In the structure of the super-junction VDMOS, there is an intrinsically parasitic bipolar transistor NPN structure. In order to prevent the parasitic transistor from being turned on, the voltage drop across the base equivalent resistance _RB must be reduced so that the emitter junction cannot be turned on. .

Referring to Fig. 2, the super junction device of the present invention adopts a non-uniformly doped P column, and the doping concentration of the P column is not uniform along the directions of the AA' line and the BB' line.

Referring to Fig. 3, the mask of the unevenly doped P-column used in the superjunction device of the present invention adopts a discontinuous mask pattern, and by adjusting the pattern of the P-column mask, due to the use of negative photoresist, Therefore, the ion implantation area in the middle of the P column is the largest, so that the dose of boron ions implanted in the middle of the P column is the largest. After a long time and high temperature, the lateral doping concentration gradually decreases from the middle to both sides. The filling area in the figure is boron ion implantation. area.

See Figure 4. The doping concentration of the P column gradually decreases from the middle to both sides after the AA' line shown in Figure 1 has been pushed for a long time at high temperature, and the doping concentration in the middle of the P column and the edge of the P column is adjusted to effectively reduce the The lateral diffusion increases the effective width of the conduction channel when the device is turned on, thereby improving the avalanche capability of the super junction semiconductor device and reducing the on-resistance at the same time.

Referring to Fig. 5, the doping concentration of the P-pillar indicated by line BB' in Fig. 1 gradually decreases from the surface to the body, and the doping concentration at the top of the P-pillar under the source metal electrode is the highest, thereby reducing the parasitic under the source metal electrode. The resistance value of the equivalent resistance R _B of the BJT, and makes the avalanche current transfer from the base area of the parasitic BJT to the body along the P column, thereby greatly inhibiting the opening of the emitter junction of the parasitic BJT and avoiding the parasitic BJT cause secondary breakdown.

Example:

This embodiment is described using a MOSFET having a superjunction structure, but the present invention is not limited to MOSFETs.

1. Substrate material preparation, using an N ⁺ zone-fused monocrystalline silicon substrate 1 with a resistivity of 0.001Ω·cm, and its crystal orientation is <100>;

2. Epitaxially grow a 5 μm N-type epitaxial layer with a resistivity of 4Ω·cm on the N ⁺ substrate as a buffer layer between the P column and the N ⁺ substrate;

3. Epitaxial growth of a 5 μm N-type epitaxial layer with a resistivity of 4Ω·cm on the surface of the silicon wafer;

4. Deposit 6 μm negative photoresist on the surface of the silicon wafer (i.e., perform boron ion implantation where there is a P-pillar pattern), use a P-pillar mask to expose and develop, and then perform four high-energy boron ion implantations. The energy of boron ions is 3.5MeV, 2.5MeV, 1.2KeV and 200KeV in sequence, and the dose of implanted boron ions is 6×10 ¹¹ cm ^-2 ;

5. Repeat step 3 and step 4 6 times, but the dose of boron ions implanted when repeating step 4 is increased by 5% of the dose of boron ions on the basis of the previous implantation each time, and finally carried out in a nitrogen atmosphere at a temperature of 1100 ° C for 30 minutes The high-temperature pushing junction forms a continuous P column with a length of about 35 μm, where the typical doping concentration of the N-type epitaxial layer is 1.1×10 ¹⁵ cm ^-3 , and the typical doping concentration of the P column in the cell region is 3.6×10 ¹⁵ cm ^{- 3} ;

6. The energy implant dose of 120KeV is 5.2×10 ¹³ cm ^-2 boron ions, and the Pbody region 4 is formed at a high temperature of 1000°C for 120 minutes;

7. Dry oxygen growth of a gate oxide layer 6 with a thickness of 100 nm at a temperature of 1100° C. for 90 minutes, and then deposit polysilicon with a thickness of 400 nm, and dry-etch the polysilicon to form a polysilicon gate electrode 7;

8. Using 80KeV energy to implant arsenic ions with a dose of 3×10 ¹⁵ cm ^-2 , and pushing the junction at 900° C. for 30 minutes to form N ⁺ source region 5 ;

9. Deposit a BPSG layer 8 with a thickness of 2 μm, reflow for 30 minutes under a nitrogen atmosphere at 950° C., and etch to form a contact hole;

10. Deposit a layer of aluminum on the upper surface of the entire device, etch the aluminum to form the source metal electrode 9, passivate, and metallize the back to form the drain electrode.

The present invention can form a P column whose doping concentration gradually decreases from the surface of the source end to the interior of the epitaxial layer, so that the parasitic triode effect is suppressed, thereby improving the avalanche capability of the super junction semiconductor device, and effectively reducing the lateral diffusion of the P column , increasing the lateral width of the conductive channel when the device is turned on, so that the on-resistance of the device is reduced.

Claims (6)

1. A method for preparing a superjunction semiconductor device capable of improving avalanche capability, characterized in that: it is realized by the following steps: Step 1. Using an epitaxial process, a layer of 3-10 μm N-type epitaxial layer (2) is formed on the N ⁺ substrate (1); Step 2, using the P-pillar mask to perform boron ion implantation to form a P-type region with a thickness of 3-6 μm; Step 3: Repeat step 1 and step 2 5-10 times respectively, while increasing the dose of boron ion implantation by 2%-8% step by step, and then push the junction at 900-1200°C to form a P-type and N-type with a thickness of 30-40μm Alternating epitaxial layers, wherein the doping concentration of the N-type epitaxial layer (2) ranges from 0.5 to 2.5×10 ¹⁵ cm ^-3 , and the doping concentration of P columns in the cell region ranges from 1.0 to 5.5×10 ¹⁵ cm ^-3 ; Step 4: Using 50~200KeV energy implantation dose as 2~8×10 ¹³ cm ^-2 boron ions, and pushing the junction at a high temperature of 900~1200°C for 60~200 minutes to form the Pbody region (4); Step 5. Dry oxygen growth of 50-200nm thick gate oxide layer (6) at a temperature of 1000-1200°C for 90 minutes, and then deposit polysilicon with a thickness of 200-800nm, and dry-etch the polysilicon to form a polysilicon gate electrode (7 ); Step 6: Implanting arsenic ions with a dose of 3×10 ¹⁵ cm ⁻² with 80 KeV energy, and pushing the junction at 900° C. for 30 minutes to form an N ⁺ source region ( 5 ); Step 7, depositing a 2-4 μm thick BPSG layer, reflowing for 30-60 minutes under a nitrogen atmosphere at 900-1000°C, and etching to form a contact hole; Step 8. Deposit a layer of aluminum on the upper surface of the entire device, etch the aluminum to form a source metal electrode (9), passivate, and metallize the back to form a drain electrode; In the third step, the doping concentration of boron ions in different regions of the P-pillar (3) is controlled by adjusting the mask plate of the P-pillar. 2. The method for manufacturing a super-junction semiconductor device capable of improving avalanche capability according to claim 1, characterized in that: in the third step, the doping in the vertical direction of the P column (3) is controlled by increasing the implantation dose of boron ions successively Concentration, the doping concentration at the bottom of the P column (3) is the lowest, and the doping concentration gradually increases from bottom to top. 3. The method for manufacturing a super-junction semiconductor device capable of improving avalanche capability according to claim 1 or 2, characterized in that: the P-pillar mask of each P-pillar (3) is composed of a group of adjacent patterns , the interval between different P columns is greater than the width of the P column (3). 4 . The method for manufacturing a superjunction semiconductor device capable of improving avalanche capability according to claim 3 , wherein the pattern of the ion implantation region of each group of P-pillar mask plates is a manufacturable regular pattern. 5. The method for preparing a superjunction semiconductor device capable of improving avalanche capability according to claim 4, characterized in that: the width of the pattern of the ion implantation region of each group of P-pillar mask plates gradually decreases from the center of the P-pillar to both sides . 6 . The method for manufacturing a super junction semiconductor device capable of improving avalanche capability according to claim 4 , wherein the manufacturable regular patterns are strips, circles or squares.