CN114388041A - Instance measurement method of critical path replication based on test element group pattern - Google Patents

Abstract

The application discloses a critical path replication instance measuring method based on a test element group pattern, which comprises the following steps: selecting a critical path in the circuit design of a semiconductor memory device product; copying the critical path to obtain a critical path copy example; laying out the copied example of the critical path to form a pattern of a test element group; the test element group pattern is measured under the same processing conditions as those in the test of the actual memory device product circuit, and the measurement result is obtained. The method obtains the key path copy example by copying, lays out the key path copy example to form the test element group pattern, measures the test element group pattern under the same processing condition as that of the actual circuit of the storage device product when testing, obtains the measurement result, can complete the measurement process before the function test of the storage device product, reduces the measurement cost and improves the working efficiency.

Description

Instance measurement method of critical path replication based on test element group pattern

technical field

The present application relates to the field of semiconductor technology, and in particular, to a method for measuring a critical path replication instance based on a test element group pattern.

Background technique

With the gradual refinement of the manufacturing process of semiconductor devices, when speed binning and timing trimming are performed in the final testing stage of semiconductor memory device products, the modeling difference from the actual design is getting bigger and bigger. The test cost at the end increases. Due to the refinement of the process, the manufactured semiconductor products have become complicated, and the cost of binning to differentiate the products in the later-stage engineering (back-end) has also increased.

SUMMARY OF THE INVENTION

The purpose of this application is to provide a method for measuring critical path replication instances based on test element group patterns. In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended to be an extensive review, nor is it intended to identify key/critical elements or delineate the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the detailed description that follows.

According to an aspect of the embodiments of the present application, a method for measuring a critical path replication instance based on a test element group pattern is provided, including:

Select critical paths in circuit design of semiconductor memory device products;

Copy the critical path to obtain a critical path replication instance;

Layout the critical path replication instance to form a test element group pattern;

The test element group pattern is measured under the same processing conditions as when the actual memory device product circuit is tested, and the measurement result is obtained.

According to another aspect of the embodiments of the present application, an electronic device is provided, including a semiconductor storage device, a processor, and a computer program stored on the semiconductor storage device and executable on the processor, the processor executing The program is used to realize the above-mentioned method for measuring the critical path replication example based on the pattern of the test element group.

According to another aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored, and the program is executed by a processor to implement the above-mentioned method for measuring a critical path replication instance based on a test element group pattern .

The technical solution provided by one aspect of the embodiments of the present application may include the following beneficial effects:

The method for measuring the critical path replica instance based on the test element group pattern provided by the embodiment of the present application, the critical path replica instance is obtained by copying, the critical path replica instance is laid out, and the test element group pattern is formed, which is consistent with the actual storage device product circuit. The pattern of the test element group is measured under the same processing conditions during the test to obtain the measurement result, and the measurement process can be completed before the function test of the storage device product, which reduces the measurement cost and improves the work efficiency.

Other features and advantages of the present application will be set forth in the description that follows, and, in part, will become apparent from the description, or may be inferred or unambiguously determined from the description, or may be implemented by practice of the present application. example to understand. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description, claims, and drawings.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in this application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 shows a flow chart of a method for measuring an example of critical path replication based on a test element group pattern according to an embodiment of the present application;

FIG. 2 shows a flow chart of steps for measuring a TEG pattern under the same processing conditions as when testing an actual storage device product circuit, and obtaining a measurement result, according to an embodiment of the present application;

FIG. 3 shows a schematic diagram of a processing process for measuring TEG patterns under the same processing conditions as when testing an actual memory device product circuit according to an embodiment of the present application;

FIG. 4 shows a timing diagram of a process of measuring a TEG pattern under the same process conditions as when testing an actual memory device product circuit according to an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It should also be understood that terms, such as those defined in a general dictionary, should be understood to have meanings consistent with their meanings in the context of the prior art and, unless specifically defined as herein, should not be interpreted in idealistic or overly formal meaning to explain.

In the testing phase, if the classification of the pre-process (front-end or front-end) can be realized, the cost of a lot of testing can be reduced. A large amount of data on speed grading in semiconductor memory device products can be produced after completing the speed function test. This problem is usually discovered after the testing process is over, but the cost has already been paid. The methods of the embodiments of the present application can solve these problems.

As shown in FIG. 1 , an embodiment of the present application provides a method for measuring a critical path replication instance based on a test element group pattern, including:

S1. Select the most representative critical path in the circuit design of the semiconductor memory device product.

The critical path is the logic path with the longest delay from input to output in a circuit design. Optimizing the critical path is an effective way to increase the speed of your design work. In general, the delay from input to output depends on the path with the largest delay that the signal travels, and has nothing to do with other paths with less delay. The critical path method can be used repeatedly in the optimization design process until it is impossible to reduce the critical path delay. Synthesizers and design analyzers in EDA tools usually provide critical path information for designers to improve designs and increase speed.

S2. Copy the critical path to obtain a critical path replication instance. For example, copy the critical path from the address buffer to the segment word line decoding output to obtain a copy instance, and the word line also uses the copy instance to copy the load transistor of the transistor junction load of a single cell and the required output part. connect.

S3. Layout the critical path replication instance to form a test element group pattern.

Specifically, a pattern called TEG (test element group) is formed on a predetermined portion of the wafer or on a separate blank wafer.

In order to smoothly draw the critical dimensions of the actual product to be made, the main circuit is used as usual, and if the bus is a long-path bus, the bus is detoured into a maze or comb shape. Iteratively lay out the desired shapes until the entire critical path has been laid out for the duplicated instance.

The replicated instances are repeatedly arranged according to the same layout, to ensure that the pattern of the formed test element group is the same as each gate terminal of the critical path in the circuit design of the semiconductor memory device product, and the output fan-shaped branch and the length of the bus are also the same. Test the module array. When the copy layout shape is repeatedly arranged, the original bus path shape is deformed and corrected to another metal layer arrangement shape.

There are several important TEG patterns in developing semiconductor devices. TEG, test element group, test element group. However, the most important of these is a TEG pattern called a defective cell array made under the same conditions as actual semiconductor memory device cells. Such a TEG pattern has approximately the same structure as the memory cells of an actual device wafer. In the case of changing the design rule or the material used in the memory cell, in order to determine the internal short circuit or open circuit defect caused by the connection of each conductive layer to the outside, the reliability, stability, etc. are evaluated by measuring the resistance or compatibility of the TEG pattern. performance and process margins.

S4 , measuring the TEG pattern under the same processing conditions as when testing the actual memory device product circuit to obtain a measurement result.

Based on the measurement results, the corresponding device characteristics can be evaluated.

In some embodiments, as shown in Figure 2, step S4 specifically includes:

S41 , input a test signal to the TEG pattern, and generate a short pulse signal in a self-reset manner according to the delay value of the critical path replication instance.

Specifically, as shown in FIGS. 3 and 4 , a single test enable signal is input into the TEG pattern; after the critical path replication instance in the TEG pattern is delayed, the short pulse generator generates a short pulse signal in a self-resetting manner.

S42, divide the frequency of the short pulse signal, and measure the pulse amplitude of the frequency-divided short pulse signal by using the PAD.

As shown in Figure 3 and Figure 4, the short pulse signal is divided by a frequency divider, and the short pulse signal after frequency division is input to the measurement PAD for measurement.

In the digital circuit test element group (DC TEG) test stage before the formal functional test of the chip, parameters such as the delay value and distribution value of the critical path of the product are known. The frequency is multiplied by a divider within an appropriate period of time that matches the test environment. In some embodiments, the frequency of the short pulse signal can be modified to several megahertz to several tens of megahertz by using a multiplying circuit composed of F/F.

In some embodiments, step S4 specifically includes:

A test signal is input into the TEG pattern to convert the high-frequency output pulses of the test module array; in order to produce results during the TEG test in the frequency test phase, a ring oscillator is set for frequency test, and the test result is obtained through the frequency test. Wherein, the test signal input into the TEG pattern is exactly the same as the test signal used when testing the actual memory device product circuit.

The method for measuring the critical path replica instance based on the test element group pattern provided by the embodiment of the present application, the critical path replica instance is obtained by copying, the critical path replica instance is laid out, and the test element group pattern is formed, which is consistent with the actual storage device product circuit. The pattern of the test element group is measured under the same processing conditions during the test to obtain the measurement result, and the measurement process can be completed before the function test of the storage device product, which reduces the measurement cost and improves the work efficiency.

Another embodiment of the present application provides an electronic device including a semiconductor memory device, a processor, and a computer program stored on the semiconductor memory device and executable on the processor, the processor executing the program to implement the above-mentioned method of measuring the critical path replication example based on the pattern of the test element group.

Another embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and the program is executed by a processor to implement the above-mentioned method for measuring a critical path replication instance based on a test element group pattern.

It should be noted:

The algorithms and displays provided herein are not inherently related to any particular computer, virtual appliance, or other device. Various general-purpose devices may also be used with the teachings based on this. The structure required to construct such a device is apparent from the above description. Furthermore, this application is not directed to any particular programming language. It is to be understood that the content of the application described herein can be implemented using a variety of programming languages and that the descriptions of specific languages above are intended to disclose the best mode of the application.

Similarly, it is to be understood that in the above description of exemplary embodiments of the application, various features of the application are sometimes grouped together into a single embodiment, figure, or its description. This disclosure, however, should not be interpreted as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this application.

It should be understood that although the various steps in the flowchart of the accompanying drawings are sequentially shown in the order indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order and may be performed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution sequence is also It does not have to be performed sequentially, but may be performed alternately or alternately with other steps or at least a portion of sub-steps or stages of other steps.

The above-mentioned embodiments only represent the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the scope of the present application. It should be noted that, for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the present application should be determined by the appended claims.

Claims (10)

1. a critical path replication instance measurement method based on test element group pattern, is characterized in that, comprises: Select critical paths in circuit design of semiconductor memory device products; Copy the critical path to obtain a critical path replication instance; Layout the critical path replication instance to form a test element group pattern; The test element group pattern is measured under the same processing conditions as when the actual memory device product circuit is tested, and the measurement result is obtained. 2. The method according to claim 1, wherein the measurement of the test element group pattern with the same processing conditions as when the actual storage device product circuit is tested to obtain a measurement result, comprising: inputting a test signal to the test element group pattern, and generating a short pulse signal in a self-reset manner according to the delay value of the critical path replica instance; The short pulse signal is frequency-divided, and the pulse amplitude of the frequency-divided short pulse signal is measured. 3 . The method according to claim 2 , wherein the frequency division of the short pulse signal comprises frequency division by a frequency divider. 4 . 4 . The method according to claim 2 , wherein the dividing the frequency of the short pulse signal comprises dividing the frequency of the short pulse signal by a multiplication circuit composed of F/F. 5 . 5. The method according to claim 1, characterized in that, performing layout on the critical path replication instance to form a test element group pattern, comprising: The critical path replica instance is laid out on a predetermined portion of the wafer or on a separate blank wafer to form a pattern of test element groups. 6. The method according to claim 1, characterized in that, performing layout on the critical path replication instance to form a test element group pattern, comprising: Repeatedly adjust the layout of the critical path replication example to ensure that the formed test element group pattern is the same as each gate terminal of the critical path in the circuit design of the semiconductor memory device product, the output fan-shaped bifurcation and the length of the bus line, thereby obtaining Test the module array. 7. The method according to claim 6, wherein the measurement of the test element group pattern with the same processing conditions as when testing the actual storage device product circuit to obtain a measurement result, comprising: The test signal is input into the test element group pattern, the high-frequency output pulse of the test module array is converted, and the test result is obtained through the frequency test; wherein, the test signal is the same as the test used when testing the actual storage device product circuit. The signal is the same. 8 . The method according to claim 1 , wherein the critical path is a path from the address buffer to the segment word line decoding output. 9 . 9. An electronic device, comprising a semiconductor storage device, a processor, and a computer program stored on the semiconductor storage device and executable on the processor, the processor executing the program to A method as claimed in any of claims 1-8 is implemented. 10. A computer-readable storage medium on which a computer program is stored, characterized in that the program is executed by a processor to implement the method according to any one of claims 1-8.

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