CN118501676B - A method for graphically scanning digital vector parameters - Google Patents
A method for graphically scanning digital vector parameters Download PDFInfo
- Publication number
- CN118501676B CN118501676B CN202410799214.3A CN202410799214A CN118501676B CN 118501676 B CN118501676 B CN 118501676B CN 202410799214 A CN202410799214 A CN 202410799214A CN 118501676 B CN118501676 B CN 118501676B
- Authority
- CN
- China
- Prior art keywords
- parameter
- scanning
- value
- vector
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000013598 vector Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000012360 testing method Methods 0.000 claims abstract description 12
- 230000008569 process Effects 0.000 claims abstract description 10
- 239000000872 buffer Substances 0.000 claims abstract description 4
- 230000000694 effects Effects 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- 238000012800 visualization Methods 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 2
- 238000010998 test method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 10
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000010845 search algorithm Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
本发明公开了一种图形化扫描数字向量参数的方法，包括以下具体步骤：确认被测数字电路连接正确后，运行测试程序，确保被测数字电路各Pin脚与PE模块正确连接，并且电源Pin脚正确上电，打开数字向量参数扫描工具，配置扫描参数，参数扫描工具自动完成参数扫描过程，缓冲中间数据，根据缓存的中间数据，绘制所有维度的参数扫描结果，根据扫描结果获取数字向量参数取值范围，调试结束。本发明在扫描范围内使用取值算法的方式，替代了原本使用定值常数为向量参数赋值的方法，这样做的好处是能够根据精度要求，一次性在目标范围内获取所有满足向量正确运行的参数值，免去了反复修改测试程序的麻烦和对示波器等辅助工具的依赖。
The present invention discloses a method for graphically scanning digital vector parameters, including the following specific steps: after confirming that the digital circuit under test is correctly connected, running the test program, ensuring that each pin of the digital circuit under test is correctly connected to the PE module, and the power pin is correctly powered on, opening the digital vector parameter scanning tool, configuring the scanning parameters, the parameter scanning tool automatically completes the parameter scanning process, buffers the intermediate data, and plots the parameter scanning results of all dimensions according to the buffered intermediate data, and obtains the digital vector parameter value range according to the scanning results, and the debugging ends. The present invention uses a value algorithm within the scanning range to replace the original method of using a fixed constant to assign values to vector parameters. The advantage of this is that all parameter values that meet the correct operation of the vector can be obtained within the target range at one time according to the accuracy requirements, eliminating the trouble of repeatedly modifying the test program and the dependence on auxiliary tools such as oscilloscopes.
Description
Technical Field
The invention relates to the technical field of digital vector parameter scanning, in particular to a method for graphically scanning digital vector parameters.
Background
In the original scheme, the digital vector parameters can only use constant values, once the digital vector operation result has fail, an oscilloscope is needed to be used for checking the waveform of the digital signal to judge whether the corresponding vector parameters need to be adjusted, then a test program is modified, vector parameter values are reset, a vector file is operated, the process needs repeated attempts to determine an available value of the vector parameters, and if the accuracy requirement of the vector parameters is high, the debugging efficiency is obviously reduced.
When the original scheme is used for debugging the multi-parameter linkage change requirement, each related parameter needs to be modified in sequence in the test program, for example, when the debugging needs to ensure that the difference between the high level and the low level of two Pin digital signals is unchanged and the requirement of a high level value capable of enabling the digital signals to stably operate is searched, the vector DriveHi value needs to be synchronously modified DriveLow value each time when the test program is modified, errors are easy to occur when the parameters are involved in the modification, maintainability of the test program also becomes poor, and the test program needs to be rewritten according to the debugging requirement for different DUTs and digital vector files, so that the reusability of the test scheme is poor.
Disclosure of Invention
The present invention is directed to a method for graphically scanning digital vector parameters, so as to solve the above-mentioned problems in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions: a method for graphically scanning digital vector parameters, comprising the following specific steps:
S1: after confirming that the tested digital circuit is connected correctly, running a test program;
s2: in the test procedure, each Pin of the tested digital circuit is ensured to be correctly connected with the PE module, and the Pin of the power supply is correctly electrified;
s3: opening a digital vector parameter scanning tool and configuring scanning parameters;
s4: the parameter scanning tool automatically completes the parameter scanning process and buffers intermediate data:
s5: drawing parameter scanning results of all dimensions according to the cached intermediate data;
s6: and acquiring the numerical vector parameter value range according to the scanning result, and ending the debugging.
Preferably, the step S4 of automatically completing the parameter scanning process by the parameter scanning tool includes the following specific steps:
S4.1: judging whether the current dimension parameter scanning is finished or not:
s4.2: if not, acquiring the next iteration value according to the configured scanning algorithm:
s4.3: all pins and TimeSet needing modification are obtained:
s4.4: if the scan parameter type is Level, modifying the Level value:
s4.5: if the scan parameter type is Edge/Period, modifying the timing value:
S4.6: if the scan parameter type is AC Spec, modifying all timing values:
s4.7: if the scan parameter type is DC Spec, modify all level values:
s4.8: if the scan parameter type is Global Spec, modifying all timing and level values:
s4.9: running a digital vector:
s4.10: recording the current running result:
s4.11: and judging whether the parameter scanning of all the dimensions is completed, and if not, selecting the next dimension.
Preferably, the defined digital vector parameters in S3 include a Type target parameter Type, a Name target parameter Name and a PARAMETER RANGE parameter range, where the Type target parameter Type content includes a Level, edge timing, period, an intermediate variable of DC Spec for a Level value, an intermediate variable of AC Spec for a timing value, and an intermediate variable of Global Spec for both a Level value and a timing value, after the Name target parameter Name selects a Type, a specific debug parameter is determined by the Name, when type=level, names DriveHi, driveLow, compareHi and CompareLow are selected by the Name, when type=edge, a Name selects DriveOn, driveData, driveReturn, driveOff and Open, and the PARAMETER RANGE parameter range includes a start point, an end point, a step number and a step length of the parameter, steps of which are shown as reference numbers 1,2,3, 4 and 5 in fig. 3, step number 1 is a target parameter Name, step number 2 is a defined parameter range, step number 3 is a parameter value algorithm, step 4 is a required target Pin, and step number 5 is a start or end.
Preferably, after the step S4.10 records the result of the current operation, the step S4.1 is returned to determine whether the current dimension parameter scanning is completed, and then whether the current dimension parameter scanning is completed is performed, if not completed, the step S4.2 is repeated, if the step S4.11 is completed to determine whether the parameter scanning of all the dimensions is completed, if not completed, the next dimension is selected, the step S4.1 is returned again to determine whether the current dimension parameter scanning is completed, and when the parameter scanning of all the dimensions is completed, the step S5 is entered to draw the result.
Preferably, the scanning Algorithm in S4.2 includes Algorithm, pins and TimeSet, the algoritm parameter value Algorithm combines a starting point, an ending point, a step number and a step length of the parameter, determines a specific value used by the target parameter, and the algoritm parameter value Algorithm includes, but is not limited to, one or more than one of a Binary, a Linear, a Jump Linear and a List, wherein the next point value of the Binary is half of the starting point and the ending point, the ending point is updated, the next point of the Linear is the starting point plus the step length, the Jump Linear is ignored by Argument input box, and the List uses only the value in the Argument input box as the iteration value.
Preferably, the Pins need to be validated target Pins, defaults to all Pins used by the vector file, the TimeSet needs to be validated time sequence, and the sum of Edge and Period time parameters defaults to all TimeSet used by the vector file.
Preferably, the digital signal generated by the digital vector on the input Pin of the DUT is a square wave with a period of 1us, the digital vector expects to detect a high level at 500ns of each period on the output Pin of the DUT, the current test target is to adjust the influence of the high level start time of the input signal on the test vector result, the target parameter DRIVEDATA is set at a starting point of 250ns, the ending point is 650ns, the step size is 50ns, the value algorithm selects Linear, DRIVEDATA starts from 250ns, the digital vector file is gradually increased by 50ns, the digital signal generated each time is repeatedly executed, the high level duration in each period is gradually reduced, when DRIVEDATA is greater than 500ns, the output Pin can only detect a low level at 500ns, and the vector result is fail.
Preferably, the input Pin digital signal is high for one quarter of the period throughout each period, and to meet this requirement, an AC Spec intermediate variable named BaseEdge can be defined, and DRIVEDATA and DriveReturn are associated with BaseEdge by the following formula
Then, the target parameter is set to BaseEdge, and the other configurations are unchanged, so that the debugging requirement can be met.
Preferably, the step S5 of drawing the parameter scan results of all dimensions involves visualization of multi-dimensional data, and adopts a software scatter diagram matrix and multi-dimensional data dimension reduction visualization software.
The invention has the technical effects and advantages that:
(1) The method uses a value algorithm in the scanning range to replace the original method for assigning the value constant to the vector parameter, and has the advantages that all parameter values meeting the correct operation of the vector can be obtained in the target range at one time according to the precision requirement, so that the trouble of repeatedly modifying the test program and the dependence on auxiliary tools such as an oscilloscope are avoided.
(2) The invention provides a solution for simplifying multi-parameter association debugging. The vector parameters to be debugged are related with intermediate variables by using formulas, and then the intermediate variables are used as target parameters, so that the mode that the original scheme needs to manually search and modify parameters in the test program one by one before running the vector each time is replaced. For parameters without direct correlation, the invention provides a multidimensional parameter debugging mode, and debugging information can be respectively and independently configured for a plurality of parameters.
(3) The invention provides a set of general solution for scanning digital vector parameters by using a graphical configuration interface mode, the tool encapsulates business logic of digital vector test, and the mode of using the graphical configuration interface to expose parameters needing to be changed to a user.
Drawings
FIG. 1 is a schematic block diagram of the flow chart of the present invention.
FIG. 2 is a diagram of the digital vector parameters of the present invention.
FIG. 3 is a diagram of a digital vector debug configuration interface according to the present invention.
FIG. 4 is a schematic diagram of an algorithm scan DRIVEDATA of the present invention.
FIG. 5 is a diagram showing the result of the digital vector parameter scan according to the present invention.
FIG. 6 is a schematic diagram of an example of a two-dimensional parameter joint debugging result according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a method for graphically scanning digital vector parameters, which is shown in fig. 1-6, and comprises the following specific steps:
S1: after confirming that the tested digital circuit is connected correctly, running a test program;
S2: in the test program, each Pin of the tested digital circuit is ensured to be correctly connected with the PE module, and the Pin of the power supply is correctly electrified, so that the running stability of the test program is ensured;
S3: turning on a digital vector parameter scanning tool, configuring scanning parameters, as shown in fig. 3, and defining digital vector parameters in S3 to include a Type target parameter Type, a Name target parameter Name and a PARAMETER RANGE parameter range, wherein the Type target parameter Type content includes a Level, edge time sequence, period, intermediate variables of DC Spec for Level values, intermediate variables of AC Spec for time sequence values, global Spec for both Level values and intermediate variables of time sequence values, after the Name target parameter Name selects a Type, determining a specific debugging parameter through the Name, when the type=level, the Name selects DriveHi, driveLow, compareHi and CompareLow, and when the type=edge, the Name selects DriveOn, driveData, driveReturn, driveOff and Open, and the PARAMETER RANGE parameter range comprises the starting point, the ending point, the step number and the step length of the parameters;
s4: the parameter scanning tool automatically completes the parameter scanning process and buffers intermediate data:
S5: drawing parameter scanning results of all dimensions according to the cached intermediate data so as to facilitate visual display of the parameter scanning results;
S6: and acquiring the numerical vector parameter value range according to the scanning result, and ending the debugging, thereby outputting the parameter scanning result.
In particular, the parameter scanning tool in S4 automatically completes the parameter scanning process, which includes the following specific steps:
S4.1: judging whether the current dimension parameter scanning is finished or not:
s4.2: if not, acquiring the next iteration value according to the configured scanning algorithm:
s4.3: all pins and TimeSet needing modification are obtained:
s4.4: if the scan parameter type is Level, modifying the Level value:
s4.5: if the scan parameter type is Edge/Period, modifying the timing value:
S4.6: if the scan parameter type is AC Spec, modifying all timing values:
s4.7: if the scan parameter type is DC Spec, modify all level values:
s4.8: if the scan parameter type is Global Spec, modifying all timing and level values:
s4.9: running a digital vector:
s4.10: recording the current running result:
s4.11: and judging whether the parameter scanning of all the dimensions is completed, and if not, selecting the next dimension.
Further, after the current running result is recorded in the step S4.10, returning to the step S4.1 to determine whether the current dimensional parameter scanning is completed, and then performing the step of determining whether the current dimensional parameter scanning is completed, if not, repeating the step S4.2 to determine whether the current dimensional parameter scanning is completed in the step S4.2, wherein in one dimension, if not, determining whether the parameter scanning is completed in the step S4.11, and if not, selecting the next dimension, entering the step S4.1 again to determine whether the current dimensional parameter scanning is completed, determining whether the parameter scanning is completed in the step S4.1, scanning the parameters in all dimensions, and when the parameter scanning is completed in all dimensions, entering the step S5 to draw the result, and automatically completing the parameter scanning process by the step S4 parameter scanning tool is shown in fig. 1.
Specifically, the scanning Algorithm in S4.2 includes Algorithm, pins and TimeSet, the algoritm parameter value Algorithm combines the starting point, the ending point, the step number and the step length of the parameter to determine the specific value used by the target parameter, the algoritm parameter value Algorithm includes, but is not limited to, binary two, linear, jump Linear and List, the next point of Binary two is half of the starting point and the ending point, and updates the ending point, binary two search, also called Binary search, is an Algorithm for searching specific elements in the ordered array, the basic idea is to compare the target value with the middle element of the array, if the target value is equal to the middle element, find the target value, if the target value is smaller than the middle element, continue to search in the first half of the array, if the target value is larger than the middle element, continue to search in the second half of the array, by reducing the search range by half each comparison, the target value can be found or the target value can be determined to be absent within the time complexity of O (log n), the Linear next point is the starting point plus the step size, the Linear search is a simple and intuitive search Algorithm, also called sequential search, which examines each element in the array or List one by one until the target element is found or the entire dataset is traversed, a simple but less efficient search Algorithm with the time complexity of O (n), where n is the size of the dataset, and since it needs to examine each element one by one, the performance is relatively poor in large-scale data, in general, the Linear search is applicable to cases where small datasets or datasets are not arranged in a specific order, the Linear search with Jump ignores Argument the iteration value specified by the input box, the List only uses the value in Argument input boxes as an iteration value, pins need to be validated target Pins, defaults to all Pins used by the vector file, timeSet needs to be validated time sequence, and the sum of Edge and Period time parameters defaults to all TimeSet used by the vector file.
In particular, the digital signal generated by the digital vector on the input Pin of the DUT is a square wave with a period of 1us, the digital vector expects to detect a high level at 500ns in each period on the output Pin of the DUT, the current test target is to adjust the influence of the high level start time of the input signal on the test vector result, the target parameter DRIVEDATA is set at a starting point of 250ns, the ending point is 650ns, the step size is 50ns, if the precision needs to be improved, the step size can be reduced, the value-taking algorithm selects Linear, the tool operation debugging process is as shown in fig. 4, DRIVEDATA starts from 250ns, gradually increases for 50ns, and re-executes the digital vector file, the high level duration in each period gradually decreases, the output Pin can only detect a low level at 500ns after DRIVEDATA is greater than 500ns, and the vector result is fail.
Further, for multi-parameter joint debugging, the target parameter can be set as an intermediate variable, the input Pin digital signal always lasts for one quarter of a period in each period, to meet the requirement, an AC Spec intermediate variable named BaseEdge can be defined, and DRIVEDATA and DriveReturn are associated with BaseEdge by the following formula
Then, the target parameter is set to BaseEdge, and the other configurations are unchanged, so that the debugging requirement can be met, for example, fig. 5 and 6 are respectively a digital vector parameter scanning result schematic diagram and a two-dimensional parameter joint debugging result schematic diagram, the abscissa in fig. 5 refers to the debugging quantity in one-dimensional parameters, the abscissa in fig. 6 refers to the debugging quantity in one-dimensional parameters, and the ordinate in fig. 6 refers to the dimension quantity debugged in two-dimensional parameters.
Specifically, the step S5 of drawing the parameter scan results of all dimensions involves visualization of multi-dimensional data, and adopts a software scatter diagram matrix and multi-dimensional data dimension reduction visualization software, such data is usually collected by running a model or experiment under different parameter combinations, and each parameter may have a different value range.
Finally, it should be noted that: the foregoing description is only illustrative of the preferred embodiments of the present invention, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements or changes may be made without departing from the spirit and principles of the present invention.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410799214.3A CN118501676B (en) | 2024-06-20 | 2024-06-20 | A method for graphically scanning digital vector parameters |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410799214.3A CN118501676B (en) | 2024-06-20 | 2024-06-20 | A method for graphically scanning digital vector parameters |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118501676A CN118501676A (en) | 2024-08-16 |
| CN118501676B true CN118501676B (en) | 2024-11-12 |
Family
ID=92247183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410799214.3A Active CN118501676B (en) | 2024-06-20 | 2024-06-20 | A method for graphically scanning digital vector parameters |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118501676B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109406916A (en) * | 2018-12-14 | 2019-03-01 | 武汉精鸿电子技术有限公司 | A kind of test platform for semiconductor memory ageing tester |
| CN112305400A (en) * | 2020-01-04 | 2021-02-02 | 成都华微电子科技有限公司 | Parameter rapid scanning test device and method |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104486708B (en) * | 2014-11-04 | 2018-04-13 | 福州瑞芯微电子股份有限公司 | Audio system parameters method to set up and device |
| CN106409264B (en) * | 2016-12-09 | 2019-02-12 | 深圳市华星光电技术有限公司 | A kind of timing adjusting method and system, driving circuit of LCD panel |
| CN111220900A (en) * | 2020-03-02 | 2020-06-02 | 南京英锐创电子科技有限公司 | Chip scan chain test method and system |
| CN112444731B (en) * | 2020-10-30 | 2023-04-11 | 海光信息技术股份有限公司 | Chip testing method and device, processor chip and server |
| CN112363045A (en) * | 2020-10-30 | 2021-02-12 | 海光信息技术股份有限公司 | Chip scanning test method and device, processor chip and server |
| CN113641545B (en) * | 2021-10-14 | 2022-02-08 | 南京宏泰半导体科技有限公司 | Automatic learning method and system for digital test vectors |
| CN113849419B (en) * | 2021-12-02 | 2022-04-05 | 上海燧原科技有限公司 | Method, system, equipment and storage medium for generating test vector of chip |
| CN114356682A (en) * | 2021-12-10 | 2022-04-15 | 上海华虹集成电路有限责任公司 | Self-learning selection method for optimal parameters of chip module |
| CN114035031B (en) * | 2022-01-11 | 2022-03-15 | 南京宏泰半导体科技有限公司 | Device and method for realizing analog waveform acquisition based on digital vector test |
| CN114564728B (en) * | 2022-04-29 | 2022-12-06 | 成都无糖信息技术有限公司 | Code-free process visualization vulnerability detection method and system |
| CN115202947B (en) * | 2022-08-02 | 2023-05-23 | 无锡众星微系统技术有限公司 | Chip test vector generation method based on debug interface |
| CN115389955A (en) * | 2022-08-24 | 2022-11-25 | 苏州清研精准汽车科技有限公司 | A pressure difference prediction method and device for battery internal and external total pressure test |
| CN117234831B (en) * | 2023-11-14 | 2024-01-26 | 鹏钛存储技术(南京)有限公司 | Chip function test method and system based on multi-core CPU |
| CN117787155B (en) * | 2023-12-28 | 2024-08-20 | 上海合芯数字科技有限公司 | Chip testability code dynamic simulation test system and test method |
| CN117805593B (en) * | 2024-01-08 | 2025-03-28 | 深圳市杰驰电子有限公司 | Integrated circuit scan test method and system |
-
2024
- 2024-06-20 CN CN202410799214.3A patent/CN118501676B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109406916A (en) * | 2018-12-14 | 2019-03-01 | 武汉精鸿电子技术有限公司 | A kind of test platform for semiconductor memory ageing tester |
| CN112305400A (en) * | 2020-01-04 | 2021-02-02 | 成都华微电子科技有限公司 | Parameter rapid scanning test device and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118501676A (en) | 2024-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5867395A (en) | Gate netlist to register transfer level conversion tool | |
| US8762123B2 (en) | Method and system for implementing circuit simulators | |
| CN113568662A (en) | Code change influence range analysis method and system based on calling relationship | |
| CN118780221A (en) | Chip verification method, device, equipment and storage medium | |
| CN113504463A (en) | Probe signal multiplexing method in FPGA prototype verification | |
| CN114239459A (en) | Processing method, device, equipment and medium for FPGA prototype design file | |
| CN115659700B (en) | Waveform automatic contrast analysis method, apparatus and medium based on signal dependency relationship | |
| CN118501676B (en) | A method for graphically scanning digital vector parameters | |
| CN118364781B (en) | Clock diagnosis and repair method, device and equipment in integrated circuit test mode | |
| US6532573B1 (en) | LSI verification method, LSI verification apparatus, and recording medium | |
| US20030070154A1 (en) | Computer readable medium with definition of interface recorded thereon, verification method for feasibility to connect given circuit and method of generating signal pattern | |
| CN116431582B (en) | Method for automatically expanding hardware design circuit resources | |
| CN111177014B (en) | Software automatic test method, system and storage medium | |
| CN110489349B (en) | JSON configuration file-based interface test method | |
| TWI879674B (en) | Measurement system and measurement method | |
| TWI855624B (en) | Measurement system and measurement method | |
| CN111414330B (en) | Data editing method and system, data processing device and storage medium | |
| CN114388041A (en) | Instance measurement method of critical path replication based on test element group pattern | |
| JP2001202391A (en) | Logic circuit simulation method | |
| Jain et al. | Automated verification system for functional coverage extraction | |
| CN119720886A (en) | Method and device for storing timing delay and calculating accurate timing report | |
| CN112464608A (en) | Method, system and medium for automatically adding ground level measuring point in PCB | |
| CN115935514A (en) | An interface form generation system and method based on MBSE model | |
| Hirase | Test time reduction through minimum execution of tester-hardware setting instructions | |
| JP2000113006A (en) | Function logic verification for electronic circuit support system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |