CN114361250A - Metal-oxide-semiconductor field-effect transistors with enhanced high-frequency performance - Google Patents

Abstract

The present invention provides a metal oxide semiconductor field effect transistor with enhanced high frequency performance, comprising a semiconductor substrate serving as a drain region and an epitaxial region disposed on an upper surface of the substrate. The MOSFET device includes a plurality of body regions and a plurality of source regions formed in an epitaxial region. The body regions are disposed adjacent an upper surface of the epitaxial region and are laterally spaced apart from one another, and each source region is disposed in a corresponding body region proximate the upper surface of the body region. The MOSFET device includes a gate structure having a plurality of planar gates and a trench gate. Each planar gate is disposed on an upper surface of the epitaxial region and overlaps a corresponding body region. The trench gate is formed partially through the epitaxial regions and between the body regions, with an upper surface of the trench gate recessed below an upper surface of the epitaxial regions.

Description

Metal-oxide-semiconductor field-effect transistors with enhanced high-frequency performance

technical field

The present invention relates generally to electrical, electronic and computer technology, and more particularly to power transistor devices and methods of manufacture.

Background technique

Power transistors, such as power metal-oxide-semiconductor field-effect transistors (MOSFETs), are typically designed to maintain a high source-to-drain current density in the on-state and maintain a high source-to-drain current density in the off-state High blocking voltage between drain and source. There are many transistor device types, such as lateral and vertical devices, planar and trench gate, unipolar and bipolar transistors, each designed for a specific application. Many design parameters are mutually exclusive such that improvement in one parameter leads to degradation in another. Therefore, there are specific performance trade-offs in different transistor designs.

Transistor design and performance criteria can be measured by several properties, including drain-source breakdown voltage (BV _ds ), characteristic on-resistance (R _sp ), gate capacitance (C _g ), and gate-drain capacitance (C _gd ). These performance characteristics are highly dependent on factors such as transistor design, structure, and material selection. Furthermore, these transistor performance characteristics typically follow opposite trends on key design parameters such as gate length, channel and drift region doping concentrations, drift region length, overall gate width, etc., allowing transistor device designs with challenge. For example, increasing the doping concentration of the drift region in a transistor reduces the characteristic on-resistance and also reduces the breakdown voltage, which may prevent the transistor device from meeting the breakdown voltage rating for a particular application. Similarly, a large gate width can reduce the overall on-resistance of a transistor device, but it also increases parasitic gate capacitance, which increases the switching losses of the transistor. Therefore, transistor design in practice often involves the trade-off of certain key design parameters in order to reach a compromise between various performance characteristics.

An important performance parameter that determines the efficiency and reliability of transistor devices is Miller capacitance, or gate-to-drain capacitance. With the ever-increasing demand for higher efficiency, power MOSFET designs are trending toward smaller gate dimensions, correspondingly lower gate charge (Q _g ) and lower threshold voltage (V _t ), due to The Miller capacitive coupling effect makes the device more susceptible to drain voltage peaks. At the same time, higher transistor switching frequencies, along with increased parasitic inductance, lead to increased drain ringing voltage. The combined effect of these effects makes today's power transistor devices prone to spurious turn-on caused by drain voltages that can damage the device. Another challenging fact is that Miller capacitance is particularly difficult to reduce and, as a design compromise, often results in an increase in the on-resistance of the device. Common methods of reducing parasitic gate-to-drain capacitance inevitably result in higher device on-resistance, so reducing Miller capacitance in power transistor devices can be one of the most difficult design goals to achieve, as well as a critical factor for product performance and application reliability. critical need.

In Chinese application CN112614891A filed by the inventor on December 17, 2020 (priority date March 4, 2020), a metal oxide semiconductor field effect transistor with enhanced high frequency performance is disclosed, which includes forming An epitaxial region on the upper surface of the substrate and at least two body regions formed in the epitaxial region, the body regions being located adjacent to the upper surface of the epitaxial region and spaced laterally from each other. The device also includes at least two source regions disposed in corresponding body regions and proximate the upper surface of the body regions, and a gate structure including at least two planar gates and one trench gate. Each planar gate is located on the upper surface of the epitaxial region and overlaps at least a portion of the corresponding body region. The trench gate is located between two of the body regions and at least partially within the epitaxial region; and a drain contact located on the backside of the substrate and electrically connected to the substrate. The technical solution of this application can obtain lower on-resistance, lower gate-drain (Miller) capacitance, lower switching loss, and higher blocking voltage in off-state.

However, the disadvantage of this invention is that although lower on-resistance, lower gate-drain (Miller) capacitance, lower switching loss, and higher blocking voltage in the off-state can be obtained, based on this It is very difficult to further improve the performance.

On the basis of the above technical solutions, the present application provides further reduced gate coupling capacitance, and obtains lower on-resistance, lower gate-drain (Miller) capacitance, lower switching loss, higher switching A metal-oxide-semiconductor field-effect transistor device with an off-state blocking voltage.

SUMMARY OF THE INVENTION

The first objective provided by the present invention is to provide further reduced gate coupling capacitance, and obtain lower on-resistance, lower gate-drain (Miller) capacitance, lower switching loss, and higher off-state The blocking voltage of a metal oxide semiconductor field effect transistor device.

The second object of the present invention is to provide further reduced gate coupling capacitance, and obtain lower on-resistance, lower gate-drain (Miller) capacitance, lower switching loss, and higher off-state resistance A method of manufacturing a metal-oxide-semiconductor field-effect transistor device with cut-off voltage.

A third object of the present invention is to provide a capacitor that produces a further reduced gate coupling capacitance.

A fourth object of the present invention is to provide a method of manufacturing a capacitor with a further reduced gate coupling capacitance.

A first aspect of the present invention provides a metal oxide semiconductor field effect transistor device, comprising:

a semiconductor substrate having a first conductivity type, the substrate serving as a drain region of the metal oxide semiconductor field effect transistor;

an epitaxial region having a first conductivity type disposed on the upper surface of the substrate;

a plurality of body regions having a second conductivity type formed in the epitaxial region, the second conductivity type being opposite to the first conductivity type, the body regions disposed proximate the upper surface of the epitaxial region and are laterally spaced from each other;

a plurality of source regions having a first conductivity type, each of the source regions disposed in a corresponding body region and proximate an upper surface of the body region; and

a gate structure, comprising: one or more planar gates and a trench gate, each of the planar gates is located on the upper surface of the epitaxial region and overlaps at least a part of the corresponding body region; the trench gate is formed in at least part of the epitaxial region and between the body region; an upper surface of the trench gate is set to be recessed in the upper surface of the epitaxial region.

A second aspect of the present invention provides a method of fabricating a metal oxide semiconductor field effect transistor device, the method comprising:

forming an epitaxial region having a first conductivity type on at least a portion of an upper surface of a substrate having a first conductivity type, the substrate serving as a drain region of the metal oxide semiconductor field effect transistor;

A plurality of body regions having a second conductivity type opposite in polarity to the first conductivity type are formed in the epitaxial region, and the body regions are disposed adjacent to the epitaxial region surfaces and are laterally spaced from each other;

forming a plurality of source regions having a first conductivity type, each of the source regions being disposed in a corresponding body region and proximate an upper surface of the body region; and

forming a gate structure including one or more planar gates and a trench gate, each of the planar gates being disposed on the upper surface of the epitaxial region and overlapping at least a portion of the corresponding body region; the trench gates is formed in at least part of the epitaxial region and between the body regions; an upper surface of the trench gate is configured to be recessed in the upper surface of the epitaxial region.

A third aspect of the present invention provides a capacitor comprising:

a semiconductor substrate having a first conductivity type;

an epitaxial region with a first conductivity type disposed on at least a part of the upper surface of the substrate, the epitaxial region constituting the first plate of the capacitor;

a trench gate formed in at least a portion of the epitaxial region and proximate an upper surface of the epitaxial region; the trench gate comprising a conductor or semiconductor material that forms the capacitor a second plate surrounded by a dielectric layer that electrically isolates the conductor or semiconductor from the epitaxial region;

a plurality of doped regions having a first conductivity type disposed in the epitaxial region on opposite sides of the trench gate and proximate an upper surface of the epitaxial region; and

a plurality of doped regions having a second conductivity type opposite in polarity to the first conductivity type, a first end of each of the doped regions having a second conductivity type adjoining a corresponding One of the doped regions of the first conductivity type has a second end opposite the first end and abuts a corresponding sidewall of the trench gate.

A fourth aspect of the present invention provides a method of manufacturing a capacitor, the method comprising:

On at least a part of the upper surface of the substrate, an epitaxial region of a first conductivity type is formed, and the epitaxial region constitutes a first plate of the capacitor;

In at least part of the epitaxial region and near the upper surface layer of the epitaxial region, a trench gate is formed; the trench gate contains a conductor or semiconductor material serving as the second plate of the capacitor, and the trench gate a trench gate is surrounded by a dielectric layer that electrically isolates the conductor or semiconductor from the epitaxial region;

forming a plurality of doped regions having a first conductivity type on opposite sides of the trench gate in the epitaxial region and adjacent to an upper surface of the epitaxial region; and

forming a plurality of doped regions with a second conductivity type opposite in polarity to the first conductivity type; the first end of each of the doped regions with the second conductivity type is adjacent to a corresponding One of the doped regions of the first conductivity type has a second end opposite to the first end abutting a corresponding sidewall of the trench gate.

The present invention can bring at least one of the following beneficial effects:

· Lower on-resistance

Lower gate-to-drain (Miller) capacitance;

Lower switching losses;

• Higher off-state blocking voltage.

• Lower coupling capacitance between planar gate and trench gate.

These and other features and advantages of the present invention will be elucidated from the following detailed description in the illustrative embodiments taken in conjunction with the accompanying drawings.

Description of drawings

The preferred embodiments will be described below in a clear and easy-to-understand manner with reference to the accompanying drawings, and the above-mentioned characteristics, technical features, advantages and implementations thereof will be further described.

The embodiments of the invention described below with reference to the accompanying drawings, which are by way of example only, are non-limiting and non-exhaustive. Unless otherwise specified, reference numerals used in the figures identify the same elements throughout the several views.

1A and 1B are, respectively, cross-sectional views of at least a portion of a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET) device including on-resistance and parasitic gate-drain capacitance diagrams;

2A-2C are at least a portion of cross-sectional views of trench gate MOSFET devices showing reduced on-resistance and illustrating some of the effects of varying body region depth in the device;

3A-3C are at least a portion of a cross-sectional view of a split trench WMOSFET device showing reduced parasitic gate-to-drain capacitance and increased off-state blocking voltage, and illustrating some of the effects of varying body region depth in the device ;

Figure 4A shows a perspective view of at least a portion of a Supergate MOSFET device of a comparative embodiment of the present invention;

4B is a cross-sectional view of the super-gate MOSFET device along AA' in FIG. 4A;

4C is a cross-sectional view of the super-gate MOSFET device shown in FIG. 4B with an accumulation layer formed adjacent to the trench gate structure;

Figure 5 conceptually depicts the relationship between the characteristic on-resistance Rsp and breakdown voltage of three different types of MOSFET devices;

Figure 6 represents a perspective view of at least a portion of a Supergate MOSFET device of another comparative embodiment of the present invention;

7A to 7I are schematic cross-sectional views of the manufacturing process of at least a portion of the super-gate MOSFET device of a comparative embodiment of the present invention shown in FIG. 4B;

8 is a cross-sectional view of at least a portion of a super-gate MOSFET device having an enhanced voltage blocking capability gate structure in accordance with a comparative embodiment of the present invention;

9A to 9L are schematic cross-sectional views of the manufacturing process of at least a portion of the super-gate MOSFET device of a comparative embodiment of the present invention shown in FIG. 8;

10 is a cross-sectional view of at least a portion of a super-gate MOSFET device with enhanced source contacts in a comparative embodiment of the present invention;

FIG. 11 is a schematic diagram of the drain voltage as a function of time for super-gate MOSFET devices of one or more comparative embodiments of the present invention as compared to standard MOSFET devices; and

12 is a schematic diagram of gate voltage as a function of time for super-gate MOSFET devices of one or more comparative embodiments of the present invention as compared to standard MOSFET devices.

13 illustrates a cross-sectional view of at least a portion of an exemplary super-gate MOSFET device with reduced gate coupling capacitance of one or more embodiments of the present invention;

14 illustrates a cross-sectional view of at least a portion of an exemplary capacitor including a trench structure;

Figure 15 shows an electrical schematic diagram of at least a portion of an exemplary switching DC-DC voltage regulator circuit to which one or more embodiments of the present invention may be applied;

16 illustrates a cross-sectional view of at least a portion of an exemplary capacitor according to one or more embodiments of the present invention, the capacitor including a trench structure as shown in FIG. 14, the trench structure being modified to provide increased capacitance; and

17 illustrates a cross-sectional view of at least a portion of an exemplary power structure of one or more embodiments of the present invention, including an exemplary super-gate MOSFET device integrated with an exemplary trench capacitor structure.

It will be appreciated that elements shown in the figures are for simplicity and clarity of presentation. In a commercially feasible embodiment, some elements that are useful or necessary but which are well known may not be shown in the figures in order to reduce obstruction of the view.

Detailed ways

The principles of the invention as illustrated in one or more embodiments will be described herein in conjunction with laterally diffused metal oxide semiconductor (LDMOS) devices and methods for fabricating LDMOS devices that do not significantly degrade power and linearity performance enhanced high-frequency performance. It should be understood, however, that this invention is not limited to the specific devices and/or methods illustratively set forth herein. Rather, given the teachings herein, those skilled in the art will appreciate that many modifications can be made to the embodiments that are within the scope of the claimed invention. That is, the embodiments herein are not intended to and should not be construed to limit the present invention.

For the purpose of describing and protecting embodiments of the present invention, the term MISFET as may be used herein should be construed broadly to include any type of metal-insulator-semiconductor field-effect transistor. For example, the term MISFET may include semiconductor field effect transistors (ie, MOSFETs) that utilize oxide materials as gate dielectrics, as well as other semiconductor field effect transistors that do not use oxide materials. In addition, although the word "metal" is mentioned in the acronyms MISFET and MOSFET, MISFET and MOSFET also include semiconductor field effect transistors whose gates are formed of non-metallic materials such as polysilicon, in which case MISFET and MOSFET MOSFETs can be used interchangeably.

Although the overall fabrication methods and structures formed in the present invention are novel, certain individual processing steps required to implement one or more portions of the methods of one or more embodiments of the present invention may utilize conventional semiconductor fabrication techniques and traditional semiconductor manufacturing tools. These techniques and tools are well known to those of ordinary skill in the art. In addition, many of the processing steps and tools used to fabricate semiconductor devices are documented in a number of existing publications, including, for example: P.H. Holloway et al., "Handbook of Compound Semiconductors: Growth, Processing, Properties, and Devices" ( Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices), Cambridge University Press, 2008; and "Processing and Properties of Compound Semiconductors" by R.K.Willardson et al., Academic Press, 2001, The above documents are incorporated herein by reference. It is emphasized that although some individual processing steps are described herein, these steps are merely illustrative and other equally suitable alternatives that may be familiar to those skilled in the art are also included within the scope of the present invention.

It should be understood that the various layers and/or regions shown in the figures are not necessarily drawn to scale. Furthermore, for the sake of economy of description, one or more of the semiconductor layers commonly used in the device may not be represented in the integrated circuit device of the figures shown. However, this does not mean that these semiconductor layers, which are not explicitly represented, are omitted in an actual integrated circuit device.

FIG. 1A shows a cross-sectional view of at least a portion of a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET) device 100 . The VDMOSFET device 100 includes a substrate 102, which may be formed from single crystal silicon that has been added with impurities or dopants (eg, boron, phosphorus, arsenic, etc.) to alter the conductivity of the material (eg, N-type or Type P). In the present conventional gate comparison example, the substrate 102 has an N conductivity type, and thus may be referred to as an N-type substrate (N+SUB).

An epitaxial region 104 is formed on the upper surface of the substrate 102 . In the present conventional gate comparative example, the epitaxial region 104 has an N conductivity type (N-EPI) by adding impurities or dopants. In the VDMOSFET device 100, the epitaxial region 104 acts as a lightly doped drift region of the device. Body regions 106 (P-BODY) having a P-type conductivity type in the present conventional gate comparative example are formed near the upper surface of the epitaxial region 104 and are laterally spaced apart from each other. The VDMOSFET device 100 also includes a source region 108 formed in at least a portion of each body region 106 and proximate the upper surface of the body region. Preferably, the source region 108 can be doped with impurities at known concentration levels using conventional implantation processes, thereby selectively changing the conductivity of the material as desired. For example, the source region 108 is of N conductivity type (N+). A heavily doped region 110 formed near the upper surface of the body region 106 has the same conductivity type as the body region 106 (eg, P-type in this example) and is laterally adjacent to the corresponding source region 108 to form the VDMOSFET device 100 body area contacts. Each of the described source regions 108 is electrically connected to a corresponding body region contact 110 .

In the VDMOSFET structure, the substrate 102 acts as the drain region of the device. A drain contact 112 formed on the backside of the substrate 102 provides electrical connection to the substrate/drain 102 .

A gate 114 is formed over at least a portion of the body region 106 and the epitaxial drift region 104 between the source regions 108 . A thin oxide layer 116 (eg, silicon dioxide SiO ₂ ) is formed under the gate 114 as a gate oxide for electrically connecting the gate to the source region 108 , the body region 106 and the epitaxial region 104 in the VDMOSFET device 100 isolation. Insulating spacers 118 are formed on the sides of the gate electrode 114 and the gate oxide layer 116 to electrically isolate the gate electrode from the source region 108 . As is well known to those skilled in the art, the bias applied to the gate forms a channel in the body region 106 under the gate for controlling current flow between the source region 108 and the substrate 102 as the drain region.

The VDMOSFET device 100 adopts a planar gate structure on the surface of the device, and has the advantages of simple fabrication process and good application reliability. However, the VDMOSFET design also exhibits significant drawbacks, including high on-resistance and large parasitic gate-to-drain capacitance (ie, Miller capacitance), which make this device unsuitable for high-power, high-frequency applications. The higher on-resistance R _ON is mainly due to the body region (P-body) channel resistance R _BODY (which can be called MOSFET channel resistance), the junction field effect transistor (JFET) channel resistance R _JFET and the epitaxial drift region resistance R _EPI (ie, R _ON =R _BODY +R _JFET +R _EPI ). Among them, R _EPI is the main factor (in a 100 volt device, it accounts for more than about fifty percent of the total on-resistance R _ON ).

1B is a cross-sectional view of at least a portion of the exemplary VDMOSFET device 100 of FIG. 1A showing parasitic gate-to-drain capacitance (eg, Miller capacitance). As shown in FIG. 1B , the larger parasitic gate-to-drain capacitance C _gd is mainly due to the larger overlap between the gate 114 and the epitaxial drift region 104 . Such large parasitic gate-to-drain capacitance C _gd components cause significant switching power losses in high frequency applications and are therefore not desirable.

Efforts have been made to reduce the on-resistance of VDMOSFET devices, thereby increasing the conductivity. In particular, it is desirable to increase the channel density of the VDMOSFET device 100 by reducing the lateral spacing of the body regions 106 . However, the junction field effect transistor effect brought about by the narrower body region spacing increases the JFET resistance R _JFET between the body regions 106 , thereby offsetting the benefits of increased channel density, which always requires between the MOSFET channel resistance R _BODY and the JFET A trade-off between channel resistance R and _JFET . Likewise, while the JFET channel resistance can be reduced by increasing the doping concentration in the upper surface of the epitaxial region 104 (JFET region), this reduction in the JFET channel resistance can also lead to undesired avalanche strikes in the off-state of the device Breakthrough voltage reduction. In this regard, there have also been attempts to use a charge balance method to balance the positive charge in the N-type epitaxial drift region 104 and the negative charge in the P-type body region 106 in the off state of the device to increase the doping of the epitaxial drift region 104 The impurity concentration, thereby reducing the on-resistance _REPI of the drift region, however, for a given dimension, the doping concentration is limited to a specific level, usually below about 10 ¹⁷ /cm ³ .

2A to 2C are cross-sectional views of at least a portion of typical trench gate MOSFET devices 200, 230 and 250, respectively, showing reduced on-resistance and conceptually illustrating some of the effects of body region depth variation in the device . Referring to FIG. 2A, trench gate MOSFET device 200 includes a substrate 202, which may be formed of single crystal silicon formed by adding impurities or dopants having an N conductivity type, and thus may be referred to as N type substrate (N+SUB).

An epitaxial region 204 is formed on the upper surface of the substrate 202 . In this example, the epitaxial region 204 has an N conductivity type (N-EPI) by adding impurities or dopants. Similar to the VDMOSFET device 100 shown in FIG. 1A, in the VDMOSFET device 200, the epitaxial region 204 acts as a lightly doped drift region of the device. Body regions (P-BODY) 206 having a P-type conductivity type in this embodiment are formed close to the upper surface of the epitaxial region 204 and are spaced apart from each other in the lateral direction. The MOSFET device 200 also includes a source region 208 formed in at least a portion of each body region 206 and proximate the upper surface of the body region. Preferably, the source region 208 may be doped with impurities of known concentration levels to have an N-type conductivity type (N+) using conventional implantation processes. A heavily doped region 210 of P conductivity type is formed adjacent to the upper surface of the body region 206 and is laterally adjacent to the corresponding source region 208 to form the source contact of the MOSFET device 200 . Each of the described source regions 208 is electrically connected to a corresponding body region contact 210 .

Similar to the VDMOSFET device 100 shown in FIG. 1A, in this MOSFET device 200, the substrate 202 serves as the drain region of the device. Drain contact 212 , preferably formed on the backside of substrate/drain 202 , provides electrical connection to the substrate/drain 202 .

The MOSFET device 200 also includes a trench gate 214 comprising polysilicon formed between the body region 206 and the source region 208 through the upper surface of the epitaxial region 204 . Trench gate 214 may be fabricated by forming a channel (ie, a trench) partially through epitaxial region 204 and between body region 206 and source region 208 , and filling the channel with dielectric material 216 . The dielectric material is preferably an oxide, such as silicon dioxide. Trench gate 214 is then formed partially through dielectric material 216 , extending vertically beyond source region 208 and body region 206 . The thickness of the dielectric material 216 surrounding the sidewalls of the trench gate 214 is preferably just enough to prevent direct electrical contact between the trench gate 214 and the adjacent source regions 208 and body regions 206 .

In contrast to the planar gate design in the VDMOSFET device 100 shown in FIG. 1A , the trench gate MOSFET device 200 achieves the advantage of lower on-resistance by eliminating the JFET resistance factor, R _JFET . However, the parasitic gate-to-drain (Miller) capacitance C _gd remains high. As in the exemplary trench MOSFET device 230 shown in FIG. 2B, by increasing the thickness of the dielectric material 216 at the bottom of the trench, the gate-to-drain capacitance can be slightly reduced. The trench MOSFET device 230 is substantially the same as the device 200 shown in FIG. 2A except that the depth of the body region 206 into the epitaxial drift region 204 is slightly reduced. Although device 230 reduces parasitic gate-to-drain capacitance C _gd , a weak point 232 is created between the bottom corners of polysilicon trench gate 214 and epitaxial region 204 that can lead to undesired device breakdown voltages decrease.

Further complicating the difficulty of this process of forming a channel within body region 206 is that the depth of the body region in epitaxial region 204 must be tightly controlled with respect to the depth of trench gate 214 . The body region 206 cannot be too shallow, as this can result in a weak point 232 that is prematurely broken down at high blocking voltages, as shown in the MOSFET device 230 shown in Figure 2B. Similarly, as shown in the trench gate MOSFET device 250 in FIG. 2C, the body region 206 also cannot be too deep in the epitaxial region 204, as this would increase gate oxidation near the bottom of the trench gate 214, contrary to what is desired layer thickness, as represented by thick oxide region 252 in Figure 2C. The thick oxide region 252 in the trench gate MOSFET device 250 reduces gate control of the channel formed in the body region 206, thereby making the device difficult to turn on; that is, the MOSFET device 250 will behave undesirably increase in the device threshold voltage.

3A-3C are cross-sectional views of at least a portion of exemplary split trench gate MOSFET devices 300, 330, 350, respectively. As shown in FIG. 3A, the split trench gate MOSFET device 300 includes a substrate 302, which may be formed of single crystal silicon, which is formed by adding impurities or dopants having an N conductivity type, and thus may be referred to as It is an N-type substrate (N+SUB). An epitaxial region 304 is formed on the upper surface of the substrate 302 . In this example, the epitaxial region 304 has an N conductivity type (N-EPI) by adding impurities or dopants. Similar to the VDMOSFET device 100 shown in FIG. 1A and the trench gate MOSFET device 200 shown in FIG. 2A, in the MOSFET device 300, the epitaxial region 304 serves as the lightly doped drift region of the device. Body regions (P-BODY) 306 having a P-type conductivity type in this conventional gate comparative example are formed near the upper surface of the epitaxial region 304 and are laterally spaced apart from each other. The MOSFET device 300 also includes a source region 308 formed in at least a portion of each body region 306 and proximate the upper surface of the body region. Preferably, the source region 308 (N+) with N-type conductivity can be formed by conventional implantation of N-type impurities. In this embodiment, a heavily doped region 310 of P conductivity type is formed near the upper surface of the body region 306 and laterally adjacent to the corresponding source region 308 to form the body region contact of the MOSFET device 300 . Thus, each of the described source regions 308 is electrically connected to a corresponding body region contact 310 .

Similar to the VDMOSFET device 100 shown in FIG. 1A and the trench gate MOSFET device 200 shown in FIG. 2A, in this split trench gate MOSFET device 300, the substrate 302 serves as the drain region of the device. A drain contact 312 formed on the backside of the substrate/drain 302 provides electrical connection to the substrate/drain 302 .

The MOSFET device 300 also includes a dielectric trench 314 filled with a dielectric material (eg, silicon dioxide) extending vertically in the epitaxial region 304 between the body region 306 and the source region 308 . A trench gate 316 , which may include polysilicon, is formed in the dielectric trench 314 with a depth just below the bottom of the body region 306 . A shield gate 318 is also formed in the trench 314 vertically below the trench gate 316 . The shield gate 318 is electrically isolated from the trench gate 316 and the epitaxial region 304 by the dielectric material in the dielectric trench 314 . In this comparative example, trench gate 316 is slightly wider than shield gate 318, such that the shield gate is surrounded by a thicker layer of dielectric material than the trench gate. Preferably, shield gate 318 is connected to source region 308 .

In the MOSFET device 300, the shielded gate 318 helps to reduce the parasitic gate-to-drain capacitance _Cgd and increase the off-state blocking voltage. However, any improvement offered by this split trench gate MOSFET design is only applicable in the device off state, that is, where the maximum doping concentration is determined by the desired breakdown voltage of the device, essentially There is no improvement in on-state performance. Split trench gate designs face similar difficulties in precisely controlling the depth and thickness of the body region 306 .

For example, a split trench gate MOSFET device 330 with a shallow body region 306 as shown in FIG. 3B. As previously described in connection with FIG. 2B, the shallow body region 306 in the MOSFET device 330 creates a weak point region 332 near the bottom corner of the trench gate 316, which can cause the device to strike prematurely at high blocking voltages Put on.

Likewise, FIG. 3C shows a split trench gate MOSFET device 350 having a deep body region 306 such that the bottom of the body region extends below the bottom of trench gate 316 . As previously described in connection with FIG. 2C , the deep body region 306 in the MOSFET device 350 forms a thick oxide region 352 near the bottom corners of the trench gate 316 , the thick oxide region 352 reduces the impact on formation in the body region 306 The gate control of the channel increases the threshold voltage of the device, making it difficult for the device to turn on.

As shown in one or more of the comparative examples, the inventors have attempted to take advantage of the beneficial properties of planar gate and trench gate structures to provide MOSFET devices with what are referred to herein as super gate structures, which advantageously enable enhanced high frequency performance without significantly degrading power and linearity performance in the device. 4A and 4B are respectively a perspective view and a cross-sectional view of at least a part of a super-gate MOSFET device 400 as a comparative example of the present invention (refer to CN112614891A for details).

The MOSFET device 400 includes a substrate 402, which may be formed from single crystal silicon (eg, having a <100> or <111> crystallographic orientation) by adding impurities or dopants (eg, boron, phosphorus, arsenic) , antimony, etc.) to form the desired conductivity type (eg, N-type or P-type) and doping level. P-type substrates can be prepared by adding p-type impurities or dopants (eg, Group III elements such as boron) to the substrate material at specified concentration levels (eg, from about 10 ¹⁴ to about 10 ¹⁸ atoms per cubic centimeter). Formation, such as through a diffusion or implantation process, alters the conductive properties of the material as desired. In other embodiments, an N-type substrate may be formed by adding a specified concentration level of N-type impurities or dopants (eg, Group V elements such as phosphorus) to the substrate material. In this embodiment, the substrate 402 is doped to have an N-type conductivity type, and thus may be referred to as an N-type substrate (N+SUB). Similar other materials may be used to form substrate 402, such as, but not limited to, germanium, gallium arsenide, silicon carbide, gallium nitride, indium phosphide, and the like.

An epitaxial region 404 is formed on the upper surface of the substrate 402 . In this comparative example of supergate, epitaxial region 404 has N conductivity type (N-EPI) by adding impurities or dopants, similarly, P-type epitaxy (eg, by adding P-type dopants) is also contemplated. Similar to the VDMOSFET device 100 shown in FIG. 1A and the trench gate MOSFET device 200 shown in FIG. 2A, in the MOSFET device 400, the epitaxial region 404 serves as the lightly doped drift region of the device. Body regions (P-BODY) 406 having a P-type conductivity type in this embodiment are formed close to the upper surface of the epitaxial region 404 and are laterally spaced apart from each other. The body region 406 in this embodiment may be formed by implanting a P-type impurity (eg, boron) into a designated area of the epitaxial region 404 using standard complementary metal oxide semiconductor (CMOS) fabrication techniques. The body region 406 preferably employs a heavier doping relative to the doping level of the substrate, eg, from about ^5x1016 atoms/cm ³ to about ^1x1018 atoms/ ^cm3 . In one or more alternative embodiments employing a P-type epitaxial region, the body region 406 may comprise an N-type well formed using similar CMOS fabrication techniques.

The MOSFET device 400 also includes a source region 408 formed in at least a portion of each body region 406 and proximate the upper surface of the body region. Preferably, the source region 408 is doped with impurities of an opposite conductivity type to that of the body region 406 . In this comparative example of the super gate, the source region 408 is of N-type conductivity (N+). In this comparative example of supergate, a heavily doped region 410 of P-type conductivity is formed near the upper surface of the body region 406 and laterally adjacent to the corresponding source region 408 , thereby forming the body region contact of the MOSFET device 400 . A corresponding source (S) electrode 412 electrically connects each source region 408 to a corresponding body region contact 410 .

Similar to the VDMOSFET device 100 shown in FIG. 1A, in this MOSFET device 400, the substrate 402 serves as the drain region of the device. A drain (D) electrode 414 is preferably formed on the backside of the substrate/drain 402, which provides electrical connection to the substrate/drain. Unlike standard lateral MOSFET devices in which both the drain and source electrodes are formed on the top surface of the device, the drain contact 414 of this MOSFET device 400 is formed on the bottom surface of the device opposite the source electrode 414, that is, the drain Electrode 414 and source electrode 412 are distributed on two vertically opposite surfaces of the MOSFET device 400 .

The MOSFET device 400 also includes a gate structure that includes at least two parts, a planar gate (G1) 416 and a trench gate (G2) 418. In the illustration of the super gate comparative example, two planar gates 416 are provided on both sides of the trench gate 418, respectively. The planar gate 416 and the trench gate 418 are preferably formed in a comb-like (striped) structure that is physically isolated from each other, even though the planar and trench gates are electrically connected at one or both ends of their striped structures (not shown in the figure, but clear meaning). In one or more alternative embodiments, the planar gate 416 and the trench gate 418 may form a connected gate structure with planar and trench gate functionality, as described in further detail below in conjunction with FIG. 6 .

In one or more comparative supergate examples, trench gate 418 , which may include polysilicon, is formed substantially vertically through the upper surface of epitaxial region 404 between body region 406 and source region 408 such that trench gate 418 is There is a source region 408 on both sides. More specifically, trench gate 418 may be fabricated partially through epitaxial region 404 and opening (eg, trenching or trenching) between body region 406 and source region 408 and filling the opening with dielectric material 420 . In one or more of the comparative supergate examples, the dielectric material 420 is an oxide, such as silicon dioxide, although the invention is not limited to any particular electrically insulating material. The trench gate 418 is then formed partially through the dielectric material 420 and extends vertically further below the source region 408 and the body region 406 . Thus, the dielectric material 420 electrically isolates the trench gate 418 from the surrounding epitaxial region 404, thereby preventing direct electrical contact between the trench gate 418 and the adjacent source regions 408 and body regions 406, and thus the dielectric material 420 may be referred to as trench gate oxide.

In one or more embodiments, each planar gate 416 is disposed on the upper surface of the epitaxial region 404 , which overlaps at least a portion of the corresponding body region 406 . A dielectric layer 422 is formed between each planar gate 416 and the upper surfaces of the body region 406 and epitaxial region 404 to electrically isolate the planar gate 416 from the body region and epitaxial region, and thus may be referred to as a planar gate oxide layer. Although not explicitly shown in FIG. 4A , as shown in FIG. 4B , dielectric spacers are preferably formed on the sidewalls of planar gate 416 and a portion of the sidewalls of trench gate 418 extending over the upper surface of epitaxial layer 404 424. As shown in FIG. 4B , gate spacer spacers 424 electrically isolate the planar gate from the trench gate and electrically isolate the planar gate 416 from the corresponding source electrode 412 .

With continued reference to FIG. 4B , the MOSFET device 400 also includes a first gate electrode 426 electrically connected to the planar gate 416 and a second gate electrode 428 electrically connected to the trench gate 418 . Gate electrodes 426 and 428 may be implemented by forming a metal silicide layer on at least a portion of the upper surfaces of gate electrodes 416 and 418, respectively. As known to those skilled in the art, in the gate silicidation process, a metal film (eg, titanium, tungsten, platinum, cobalt, nickel, etc.) is deposited on the upper surface of the polysilicon gate, and the deposited metal film is annealed to make the polysilicon Reactions occur between the silicon in the gate, eventually forming a metal silicide contact.

When a positive bias voltage in excess of the threshold voltage is applied to the N-channel MOSFET device, such as by applying a positive voltage between the planar gate 416 and the corresponding source region 408 as described, a channel is formed in the body region 406 under the planar gate, Thus, the MOSFET device 400 is turned on. At the same time, since the trench gate 418 is electrically connected to the planar gate 416, a positive bias voltage will be applied to the trench gate, thereby forming a surface with a majority of the epitaxial region 404 near the surface of the trench gate oxide 420 as shown in Figure 4C A strong accumulation layer 430 of carriers, such as electrons in this embodiment. This accumulation layer 430 beneficially increases the conductance of the MOSFET device 400, which enables the device to achieve very low on-resistance, for example, about two milliohm-square millimeters (2 mΩ at a blocking voltage rating of 30 volts) -mm ² ). As will be described below, the super gate MOSFET device 400 achieves substantial performance improvements over conventional planar gate and trench gate devices.

Figure 5 conceptually depicts the proportional relationship between characteristic on-resistance _Rsp (ohm-square centimeter) and breakdown voltage (volts) for three different types of MOSFET devices. Specifically, reference numeral 502 denotes the proportional relationship between the characteristic on-resistance _Rsp and breakdown voltage of a trench-gate MOSFET device consistent with the trench-gate MOSFET device 200 shown in FIG. 2A. Reference numeral 504 denotes the proportional relationship between the characteristic on-resistance Rsp and breakdown voltage of a split trench gate MOSFET device consistent with the split trench gate MOSFET device 300 shown in FIG. 3A. Reference numeral 506 represents the ratio between the characteristic on-resistance _Rsp and the breakdown voltage of a super-gate MOSFET device formed in accordance with one or more comparative embodiments of the present invention, such as the super-gate MOSFET device 400 shown in FIG. 4A relation. Ideally, MOSFET devices will exhibit high breakdown voltage and low characteristic on-resistance, however, in practice, device characteristics are often conflicting, that is, MOSFET devices with very low on-resistance will also Has very low breakdown voltage, and vice versa, as in the trench gate and split trench gate MOSFET devices shown at 502 and 504, respectively.

As shown in FIG. 5, a super gate MOSFET device (reference numeral 506) formed in accordance with the comparative example of the super gate of the present invention has at least two an obvious advantage. First, the slope representing the proportional relationship between characteristic on-resistance _Rsp and breakdown voltage 506 is significantly reduced compared to 502 and 504, i.e. in a trench gate MOSFET device with the same breakdown voltage rating or split trench Super MOSFET devices have significantly lower characteristic on-resistance than gated MOSFET devices. As a result, the size of the chip can be scaled down in proportion to the size of the chip, further resulting in a significant reduction in parasitic gate capacitance and gate-to-drain capacitance.

Normally, the capacitance value C of the parallel plate capacitor is determined according to the following formula:

where ε0 is the absolute permittivity (i.e. vacuum permittivity ε0 = 8.854×10-12F/m, εr is the relative permittivity of the medium or dielectric material between parallel plates, A is a The surface area of the sides, d is the distance between the parallel plates (i.e., the thickness of the dielectric material between the parallel plates). Therefore, by reducing the chip size, one or more of the parasitic gate capacitance and/or the parasitic gate-to-drain capacitance can be reduced The surface area of the two parallel plates, parasitic gate capacitance and gate-to-drain capacitance reduction is beneficial for reducing switching losses in high frequency applications such as synchronous DC-DC converters.

Continuing to refer to FIG. 5, a second significant advantage of the super-gate MOSFET device of the comparative example of the present invention, as indicated by the trapezoidal shape of reference 506, is that the super-gate MOSFET device can adjust the characteristic on-resistance during device operation, while the Conventional MOSFET devices have a fixed characteristic on-resistance. This is primarily due to the fact that in conventional MOSFET designs, the doping concentration, and its associated carrier concentration, are fixed after the device is fabricated. In contrast, in the super-gate MOSFET devices of one or more embodiments of the present invention, the carrier concentration is not fixed, but depends on the bias voltage applied to the trench gate structure, which can be easily adjusted of. This brings many benefits, including greater flexibility in device design, a wider process window, and higher reliability for the operation of super-gate MOSFET devices.

FIG. 6 is a perspective view of at least a portion of a typical super-gate MOSFET device 600 shown in another comparative example of the present invention. More specifically, the super-gate MOSFET device 600 is similar to the typical super-gate MOSFET device 400 shown in FIGS. 4A and 4B except that the MOSFET device 600 includes a simplified gate design that combines the planar gate (in FIG. 4B ). 416 ) and trench gate ( 418 in FIG. 4B ) are merged together to form a T-shaped gate 602 with planar gate and trench gate functions in the MOSFET device 600 . Specifically, the gate 602 includes a planar gate portion 604 and a trench gate portion 606 as a connecting structure.

A trench gate portion 606 is located between the two body regions 406 and extends at least partially vertically in the epitaxial region 404 . The trench gate portion 606 in the comparative super gate embodiment of the present invention is not limited to any particular size, but the depth of the trench gate portion 606 is preferably about 1-2 micrometers (μm). Planar gate portion 604 begins at trench gate portion 606 and extends along the upper surfaces of epitaxial region 404 and body region 406 in two opposite lateral directions (ie, horizontal) to the edge of corresponding source region 408 . An insulating layer 608 is formed under the gate 602 to electrically isolate the gate from adjacent structures and regions. Preferably, dielectric spacers 610 are disposed on the sidewalls of the gate electrode 602 to prevent electrical contact between the gate electrode and the source electrode 412 .

Plane and trench gate portions 604 and 606 preferably operate in the same manner as plane gate 416 and trench gate 418, respectively, in example MOSFET device 400 in Figure 4b. More specifically, by applying a gate bias signal greater than the threshold voltage of MOSFET device 600 between gate 602 and source region 408, each planar gate portion 604 will induce a corresponding body region 406 directly below the planar gate portion A channel is formed in the device; when the applied gate bias signal is below the device threshold voltage, the channel is essentially closed. At the same time, the applied gate bias signal will cause trench gate portion 606 to form a strong accumulation layer 612 with a majority of carriers and with the contours of the trench gate portion near gate oxide 608 . As previously discussed, even though there is only a narrow space between the body regions 406, the strong accumulation layer 612 can increase the conductance of the MOSFET device 600, thereby reducing the on-resistance of the device. Connecting the gate 602 to the source electrode 412 closes the channel within the body region 406 , thereby turning off the MOSFET device 600 .

By way of example only, and not limitation, FIGS. 7A-7I are schematic cross-sectional views of an exemplary fabrication process of at least a portion of the super MOSFET device of a comparative embodiment of the present invention in FIG. 4B .

Referring to Figure 7A, the exemplary fabrication process begins with a substrate 702, which in one or more embodiments includes single crystal silicon or other alternative semiconductor materials such as, but not limited to, germanium, Silicon germanium, silicon carbide, gallium arsenide, gallium nitride, etc. In this illustrative embodiment, the substrate 702 is doped with N-type impurities or dopants (eg, phosphorus, etc.) to form an N-conductivity-type substrate (N+SUB). P-conductivity type substrates may also be considered in embodiments of the present invention. Substrate 702 is preferably cleaned and surface treated.

An epitaxial layer 704 is then formed on the upper surface of the substrate 702 by, for example, an epitaxial growth process. In one or more embodiments, the epitaxial layer has an N conductivity type (N-EPI), although a similar P conductivity type epitaxial layer is also contemplated. The doping concentration of epitaxial layer 704 is preferably lower than the doping concentration of substrate 702 .

As shown in FIG. 7B , a hard mask layer 706 is formed on the surface of the epitaxial layer 704 . In one or more embodiments, the hard mask layer 706, which may include silicon nitride, is preferably formed using standard deposition processes. The hard mask layer 706 is then patterned (eg, using standard photolithography and etching) and etched to form trenches 708 at least partially in the epitaxial layer 704 . In one or more of the comparative super gate embodiments, reactive ion etching (RIE) may be employed to form trenches 708 . Then, as shown in FIG. 7C, a first dielectric layer 710 is formed on the inner walls (eg, sidewalls and bottom) of the trench 708, which may be an oxide layer in one or more embodiments. Although the comparative supergate embodiments of the present invention are not limited to any particular dielectric material, in one or more embodiments, the first dielectric layer 710 includes silicon dioxide formed using a dry or wet oxidation process . This first dielectric layer 710 will form the gate oxide of the trench gate in the supergate MOSFET device of this example (eg, 418 in Figure 4A).

)的天然氧化物。为了在受控环境中生长较厚的氧化物，可以使用几种已知的方法，例如，通过原位生成蒸汽或远程等离子体源(例如，远程等离子体氧化(RPO))进行氧化。Referring now to FIG. 7D, the hard mask layer (706 in FIG. 7C) is removed, for example, by using a wet or dry etching process such as chemical or plasma etching. A second dielectric layer 711 is then formed on the upper surface of the epitaxial layer 704. In one or more embodiments, the second dielectric layer 711 may be an oxide layer. This second dielectric layer 711 will form the gate oxide of the planar gate of the super gate MOSFET device (eg, 416 in Figure 4A). A chemical reaction between oxygen and silicon is typically driven by a high temperature environment (eg, about 800 degrees Celsius (°C) to 1200°C), producing silicon dioxide, forming the first and second dielectric layers 710, 711; however, even in At room temperature, a thin layer (e.g., about 1-3 angstroms) can also be formed in the surrounding environment.

) of natural oxides. To grow thicker oxides in a controlled environment, several known methods can be used, for example, oxidation by in-situ steam generation or remote plasma sources (eg, remote plasma oxidation (RPO)).

Next, as shown in FIG. 7E, a gate structure including a planar gate 712 and a trench gate 714 is formed. The planar and trench gates 712, 714 preferably comprise polysilicon and are formed using standard deposition processes, followed by patterning (eg, using standard photolithography and etching) and etching. In this comparative example of the super gate, two plane gates 712 are provided on both sides of the trench gate 714 . Although not explicitly shown in FIG. 7E, the planar gate 712 and the trench gate 714 preferably form a comb-like (ie, stripe-like) structure that is structurally separated from each other, in which the planar gate and the trench gate are One or (opposite) ends of the strip are electrically connected. In one or more alternative embodiments, the planar gate 712 and the trench gate 714 may form a connected structure having planar gate and trench gate functions as described above in connection with FIG. 6 .

As shown in FIG. 7F, the exposed portion of the second dielectric layer (711 in FIG. 7E) on the upper surface of the epitaxial layer 704 (ie, not covered by the planar gate 712 and the trench gate) is removed using, for example, a standard selective etching process. Part of the second dielectric layer covered by 714) is removed. A self-aligned body region 716 is then formed in the epitaxial layer 704 near the upper surface of the epitaxial layer. In the present exemplary comparative supergate embodiment, the body region is preferably formed by implanting a P-type dopant at a specified concentration level into the epitaxial layer 704, followed by thermal processing (eg, annealing) to drive the dopant into the epitaxial layer. 716.

Alternatively, in the comparative supergate embodiment shown in FIG. 7F , implant region 718 is preferably formed in epitaxial layer 704 near the upper surface of the epitaxial layer and between body region 716 and trench gate 714 . In one or more of the supergate comparative examples, the implanted region 718 is formed by implanting a specified concentration level of N-type dopant into the epitaxial layer 704 between the planar gate 712 and the trench gate 714 of. During implantation, the planar gate and trench gate act as masks. Preferably, the implanted region 718 is used to increase the N-type doping concentration level of the edge of the channel formed in the body region 716, thereby reducing the on-resistance of the MOSFET device. Implanted region 718 may also confine the channel area under gate 712, thereby improving high frequency performance. Although embodiments of the present invention are not limited to any particular doping concentration, in one or more embodiments, a preferred doping concentration for the implanted region 718 is about 1×10 ¹⁶ to 1×10 ¹⁸ atoms/ cubic centimeters.

As shown in FIG. 7G , then, dielectric spacers 720 are formed on the sidewalls of the planar gate 712 and the trench gate 714 . Although the present invention is not limited to any particular dielectric material, in one or more comparative supergate embodiments, the dielectric spacers 720 may include silicon dioxide or silicon nitride. An etching process is then used to create the desired patterning to form source region contacts (eg, N-type) and body region pick-up contacts (eg, P-type) in the device.

In FIG. 7H , source regions 722 are formed in corresponding body regions 716 proximate the upper surface of the body regions and self-aligned planar gates 712 . In the present exemplary comparative embodiment, the source region 722 having an N conductivity type is formed using, for example, a standard implantation process (eg, ion implantation). In this comparative example, a heavily doped region 724 of P conductivity type is formed near the upper surface of the body region 716 and laterally adjacent to the corresponding source region 722 to form the body of the super-gate MOSFET device area contacts. Thus, each source region 722 is electrically connected to a corresponding body region contact 724 .

Referring now to FIG. 7I, using a standard front-end silicidation process, metal silicide contacts 726 are formed on the source region 722, respectively, and metal silicide contacts 728 and 730 are formed on the planar and trench gates, respectively. As is well known, during silicidation, a layer of metal is deposited on the upper surface of the wafer and then thermally treated (eg, thermal annealing) to form an alloy (metal silicide) where the metal contacts the exposed silicon. The unreacted metal is then removed using, for example, standard etching processes, forming a low resistance suicide at the source and gate contacts. Front-side interconnects and passivation are then performed with metals (eg, aluminum, etc.), and dielectric deposition and patterning are performed in a front-end-of-line (FEOL) process. After the FEOL process, the wafer is flipped for backside thinning (eg, using chemical mechanical polishing, CMP) and backside metallization to form the drain contact 732 of the Supergate MOSFET device.

8 is a cross-sectional view of at least a portion of a super-gate MOSFET device 800 in a comparative embodiment of the present invention. The MOSFET device 800 is similar to the super-gate MOSFET device 400 shown in Figure 4B, except that its gate structure is configured for enhanced voltage blocking capability. As shown in FIG. 8, a super-gate MOSFET device 800 includes a substrate 802, which can be prepared by adding impurities or dopants (eg, boron, phosphorous, etc.) of desired conductivity type (N-type or P-type) and doping level , arsenic, antimony, etc.) and modified single crystal silicon formed. In the present exemplary embodiment, the substrate 802 is doped to have an N conductivity type, and thus may be referred to as an N-type substrate (N+SUB). Other materials are also contemplated to form substrate 802, such as, but not limited to, germanium, gallium arsenide, silicon carbide, gallium nitride, indium phosphide, and the like.

An epitaxial region 804 is formed on the upper surface of the substrate 802 . In this comparative example of super gate, the epitaxial region 804 is formed by adding impurities or dopant denaturation with N conductivity type (N-EPI). Of course, P-type epitaxy can also be considered. In the MOSFET device 800, the epitaxial region 804 acts as a lightly doped drift region of the device. In this embodiment, two body regions (P-BODY) 806 having a P-type conductivity type are formed near the upper surface of the epitaxial region 804 and are laterally spaced apart from each other. The body region 806 in this embodiment may be formed by implanting a P-type impurity (eg, boron) into designated areas of the epitaxial region 804 using standard complementary metal oxide semiconductor (CMOS) fabrication techniques.

A source region 808 is formed in at least a portion of the corresponding body region 806 near the upper surface of the body region. Preferably, in the exemplary MESFET device 800, the source region 808 has an N-type conductivity type. In this comparative example of super gate, the heavily doped region 810 formed near the upper surface of the body region 806 and laterally adjacent to the corresponding source region 808 has a P-type conductivity, thereby forming a body region contact of the MOSFET device 800 . point. A corresponding source (S) electrode 812 electrically connects each source region 808 to a corresponding body region contact 810 .

In this super gate MOSFET device 800, the substrate 802 serves as the drain region of the device. Accordingly, for example in a back-end-of-line (BEOL) process, the drain (D) electrode 814 is preferably formed on the backside of the substrate/drain 802, which is provided between the substrate/drain electrical connection. Similar to the MOSFET device 400 shown in FIG. 4B, the drain electrode 814 is formed on the backside of the MOSFET device 800, on the side opposite the source electrode 812 formed on the upper/front surface of the device, that is, the drain The pole electrode 814 and the source electrode 812 are distributed on two vertically opposite surfaces of the MOSFET device 800 .

The MOSFET device 800 also includes a gate structure that includes at least two parts, a planar gate (G1) 816 and a trench gate (G2) 818. In the illustration of the comparative example of the super gate of the present invention, two planar gates 816 are respectively disposed on both sides of the trench gate 818 . The planar gate 816 and the trench gate 818 are preferably formed into a comb-like (striped) structure that is structurally separated from each other, that is, the planar gate and the trench gate are electrically connected at one or both ends of the striped structure (not explicitly shown in the figure, but hidden). contains). In one or more alternative embodiments, planar gate 816 and trench gate 818 may form a connected gate structure with planar and trench gate functionality.

In one or more embodiments, trench gate 818 , which may include polysilicon, may generally be formed vertically through the upper surface of epitaxial region 804 located between body regions 806 and also between source regions 808 , such that the trench gate 818 is located in the trenches. There is a source region 808 on both sides of the trench gate 818 . The MOSFET device 800 also includes a dielectric layer 820 that electrically isolates the trench gate 818 from the surrounding epitaxial region 804 , thereby preventing direct electrical contact between the trench gate 818 and adjacent source regions 808 and body regions 806 . In one or more comparative supergate embodiments, the dielectric layer 820 includes an oxide, such as silicon dioxide, which may be referred to as a trench gate oxide, although this approach is not limited to any particular electrically insulating material.

In one or more comparative embodiments, each planar gate 816 is disposed on the upper surface of the epitaxial region 804 at least partially overlapping the corresponding body region 806 . A second dielectric layer 822 is formed between each planar gate 816 and the upper surface of the body region 806 and epitaxial region 804 to electrically isolate the planar gate 816 from the body region and epitaxial region, and thus may be referred to as a planar gate oxide layer. Dielectric spacers 824 are preferably formed on the sidewalls of the planar gate 816 and the sidewalls of the trench gate 818 . Gate spacers 824 electrically isolate the planar gate from the trench gate and electrically isolate the planar gate 816 from the corresponding source electrode 812 .

With continued reference to FIG. 8 , the super gate MOSFET device 800 also includes a first gate electrode 826 connected to the planar gate 816 and a second gate electrode 828 connected to the trench gate 818 . Gate electrodes 826 and 828 may be implemented by forming a metal silicide layer on at least a portion of the upper surfaces of gate electrodes 816 and 818, respectively.

In order to optimize the voltage blocking capability of the super gate MOSFET device 800, the trench gate structure is preferably configured with a trench gate oxide layer 820, and the portion of the trench gate oxide layer 820 located in the lower part 830 of the trench gate structure is more than the trench gate structure. The portion of the upper portion 832 of the gate structure is thicker. Although the comparative supergate embodiments of the present invention are not limited to any particular size, in one or more comparative supergate embodiments, the trench gate oxide 820 at the upper portion 832 of the trench gate structure has a thickness of about 10 Å -50nm, while the thickness of the trench gate oxide layer at the lower part 830 of the trench gate structure is about 50-500nm. The planar gate oxide layer 822 under each planar gate (G1) 816 is preferably around 5-50 nm. A method of configuring a super-gate MOSFET device having a trench gate structure is illustratively described below with reference to FIGS. 9A to 9L.

Specifically, FIGS. 9A to 9L are schematic cross-sectional views of a manufacturing process of at least a portion of a super gate MOSFET device 800 in the embodiment shown in FIG. 8 of the super gate comparative example of the present invention shown in FIG. 8 . Referring to FIG. 9A, the exemplary fabrication process begins with a substrate 902, which in one or more embodiments includes monocrystalline silicon or other alternative semiconductor materials such as, but not limited to, germanium, Silicon germanium, silicon carbide, gallium arsenide, gallium nitride, etc. In this illustrative embodiment, the substrate 902 is doped with N-type impurities or dopants (eg, phosphorus, etc.) to form an N-conductivity-type substrate (N+SUB). The use of a P-conductivity-type substrate may also be considered in the comparative example of the supergate of the present invention. Substrate 902 is preferably cleaned and surface treated.

An epitaxial layer 904 is then formed on the upper surface of the substrate 902 by, for example, an epitaxial growth process. In one or more embodiments, the epitaxial layer has an N conductivity type (N-EPI), although a similar P conductivity type epitaxial layer is also contemplated. The doping concentration of epitaxial layer 904 is preferably lower than the doping concentration of substrate 902 .

As shown in FIG. 9B , a hard mask layer 906 is formed on the surface of the epitaxial layer 904 . In one or more embodiments, the hard mask layer 906, which may include silicon nitride, is formed, preferably using standard deposition processes. The hard mask layer 906 is then patterned using, for example, standard photolithography and etching, and trenches 908 are formed at least partially in the epitaxial layer 904 using, for example, an etching process; in one or more of the comparative supergate embodiments , the trenches 908 may be formed using reactive ion etching (RIE). Subsequently, as shown in FIG. 9c, the hard mask layer 906 is removed using a method such as etching.

The first two steps in the fabrication of this super-gate MOSFET device 800 are identical to the fabrication of the exemplary super-gate MOSFET device 400 shown in Figure 4B, depicted in Figures 7A and 7B. Referring now to FIG. 9D , an insulating layer 910 is formed in trench 908 and over at least a portion of the upper surface of epitaxial layer 904 . In one or more embodiments, insulating layer 910 includes an oxide (eg, silicon dioxide) grown or deposited in trench 908 and on the upper surface of epitaxial layer 904 . Then, as shown in FIG. 9E, an etch-back process, such as wet etching, is used to remove the insulating layer 910 on the upper surface of the epitaxial layer 904 and the insulating layer 910 on part of the sidewalls in the trench 908, allowing part of the insulating layer 910 to remain on At the bottom of the trench, as shown in FIG. 9F , the wafer is thermally oxidized to form a thinner conformal gate oxide layer 912 . Although the supergate comparative example of the present invention is not limited to any particular size, in one or more embodiments, the thickness of the oxide layer 912 on the upper surface of the epitaxial layer 904 and on the sidewalls of the trench 908 is about 30-50 nm .

As shown in FIG. 9G, in one or more of the comparative supergate embodiments, a narrower trench 914 is formed in insulating layer 910 using anisotropic etching (eg, RIE). Then, as shown in FIG. 9H , a thin gate oxide layer 916 (eg, about 30-50 nm) is grown on the upper portion of the sidewalls of the first trench 908 and the upper surface of the epitaxial layer 904 . Next, as shown in FIG. 9I, a gate structure including planar gate 918 and trench gate 920 is formed. Each of the planar and trench gates 918, 920 preferably comprises polysilicon and is formed using standard deposition processes, followed by patterning (eg, using standard photolithography and etching) and etching. In this embodiment, two plane gates 918 are provided on both sides of the trench gate 920 . Although not explicitly shown in FIG. 9I, the planar gate 918 and the trench gate 920 preferably form a comb-like (ie, strip-like) structure that is structurally separated from each other, in which the planar gate and the trench gate are One or (opposite) ends of the strip are electrically connected.

Referring now to FIG. 9J , the exposed portion of the gate oxide layer (916 in FIG. 9I ) on the upper surface of the epitaxial layer 904 (ie, not covered by the planar gate 918 and the trench gate 920 ) is removed using, for example, a selective etching process. Part of the gate oxide) removed. Self-aligned body regions 922 are then formed in epitaxial layer 904 near the upper surface of the epitaxial layer. In the present exemplary embodiment, body region 922 is preferably formed by implanting a specified concentration level of P-type dopant into epitaxial layer 904, followed by thermal processing (eg, annealing) to drive the dopant into the epitaxial layer.

Alternatively, in the comparative example of the super gate shown in FIG. 9J , the implanted region 924 is preferably formed in the epitaxial layer 904 near the upper surface of the epitaxial layer and between the body region 922 and the trench gate 920 . In one or more embodiments, the implanted region 924 is formed by implanting an N-type dopant at a specified concentration level into the epitaxial layer 904 located between the planar gate 918 and the trench gate 920 . During implantation, the planar gate and trench gate act as masks. Like the implanted region 718 shown in FIG. 7F, the implanted region 924 is preferably used to increase the N-type doping concentration level at the edge of the channel formed in the body region 922, thereby reducing the MOSFET device's On resistance. Implanted region 924 may also confine the channel area under gate 918, thereby improving high frequency performance. Although embodiments of the present invention are not limited to any particular doping concentration, in one or more embodiments, a preferred doping concentration for the implanted region 924 is about 1×10 ¹⁶ to 1×10 ¹⁸ atoms/ cubic centimeters.

As shown in FIG. 9K , dielectric spacers 926 are then formed on the sidewalls of the planar gate 918 and the trench gate 920 . Although the present invention is not limited to any particular dielectric material, in one or more embodiments, the dielectric spacers 926 may include silicon dioxide. An etching process is then used to create the desired patterning to form source region contacts (eg, N-type) and body region contacts (eg, P-type) in the device.

In FIG. 9L , source regions 928 are formed in corresponding body regions 922 proximate the upper surface of the body regions and self-aligned planar gates 918 . In the present exemplary embodiment, the source region 928 having an N conductivity type is formed using, for example, a standard implantation process (eg, ion implantation). In the supergate comparative example, a heavily doped region 930 of P conductivity type is formed near the upper surface of the body region 922 and laterally adjacent to the corresponding source region 928 to form the supergate MOSFET device body area contacts. Thus, each source region 928 is electrically connected to a corresponding body region contact 930 .

Using standard front-end silicidation processes, metal silicide contacts (812) are formed on source region 928, respectively, and metal silicide contacts (826 and 828) are formed on planar gate 918 and trench gate 920, respectively. Front-side interconnection and passivation are then performed using metals (eg, aluminum, etc.), and dielectric deposition and patterning are performed in a front-end-of-tine (FEOL) process. After the FEOL process, the wafer is flipped for backside thinning (eg, CMP) and backside metallization to form drain contacts (814), thereby forming the super gate MOSFET device 800 shown in FIG.

10 is a cross-sectional view of at least a portion of a Super Gate MOSFET device with enhanced source contacts in another comparative Super Gate embodiment of the present invention. The MOSFET device 1000 is identical to the super-gate MOSFET device 400 shown in Figure 4B, with the difference being the source contact. Specifically, as shown in FIG. 10, the super-gate MOSFET device 1000 includes an embedded source contact 1002 formed in a corresponding body region 406, the source contact 1002 being proximate to the upper surface of the body region and connected to the body region 406. Adjacent source regions 408 are electrically connected. In one or more embodiments, each embedded source contact 1002 includes a metal, such as tungsten, although embodiments of the invention are not limited to tungsten. This source contact structure provides a larger contact area between the source metal and the source region 408, thus facilitating lower resistance of the source contact. Desirably, such a source contact structure can be used with any of the super-gate MOSFET device structures described herein, as will be apparent to those skilled in the art based on this revelation. Although not explicitly shown in FIG. 10, metal silicide may also be formed around the embedded source contact 1002 using the same metal silicide process used for the formation of the planar gate and trench gate contacts 426 and 428, for This solution will also be apparent to those skilled in the art based on this revelation.

The MOSFET devices of each of the Supergate Comparative Examples of the present invention achieve superior performance compared to standard MOSFET device designs. For example, Figure 11 is a schematic diagram of the drain voltage as a function of time for a super gate MOSFET device (reference numeral 1102), such as the super gate MOSFET device 400 shown in Figure 4B, compared to a standard MOSFET device (reference numeral 1104). As can be seen in Figure 11, the drain voltage of the new super-gate MOSFET device rises over time (ie, dv/dt) much faster than the standard MOSFET device. This demonstrates that the switching speed of the new super-gate MOSFET device is an improvement.

12 is a schematic diagram of gate voltage as a function of time for a super gate MOSFET device (reference numeral 1202), such as the super gate MOSFET device 400 shown in FIG. 4B, as compared to a standard MOSFET device (reference numeral 1204). As can be seen in Figure 12, the gate voltage of a standard MOSFET device exhibits severe disturbance 1206 when the device is turned off. This perturbation is mainly due to the drain voltage coupling effect of the large parasitic Miller capacitance (C _gd ) associated with standard MOSFET devices (as discussed earlier), which can exceed the device's threshold voltage, causing the device misleading. Misturning of such devices can lead to short-circuit conditions, especially when MOSFET devices are used as low-side transistors in power switching applications such as DC-DC converters. By comparison, it can be found that the super-gate MOSFET device represented by the reference numeral 1202 exhibits very little gate voltage disturbance, which is much lower than the threshold voltage of the device, thus eliminating the problem of false turn-on of the device. Therefore, the super-gate MOSFET devices of the comparative embodiments of the present invention have higher efficiency and higher reliability in higher frequency DC-DC converter applications than conventional MOSFET devices.

For the illustrative embodiment of the super-gate MOSFET device 1000 shown in FIG. 10, by recessing the trench gate G2 below the upper silicon surface of the device, the coupling capacitance between the planar gate G1 or the trench control gate G2 can be further reduced .

FIG. 13, by way of example only and not limitation, shows a cross-sectional view of at least a portion of an exemplary super-gate MOSFET device 1300 with reduced gate coupling capacitance in accordance with one or more embodiments of the present invention. MOSFET device 1300 is similar to illustrative MOSFET device 100 shown in Figure 10, except that the control gate is recessed below the top surface of the device.

More specifically, referring to FIG. 13 , MOSFET device 1300 includes a control gate ( G2 ) formed as trench gate 1302 . Trench gate 1302 may be fabricated in a manner consistent with trench gate 418 shown in FIG. 10, such as by forming openings (eg, trenches or channels) partially through epitaxial region 404 between P-type body regions 406, and using Dielectric material 1304 fills the openings. The dielectric material 1304 may be an oxide, such as silicon dioxide, although the invention is not limited to any particular electrically insulating material. A trench gate 1302 is then formed partially through the dielectric material 1304 , extending vertically below the source region 408 and body region 406 . Accordingly, the dielectric material 1304 electrically isolates the trench gate 1304 from the surrounding epitaxial region 404, thereby preventing direct electrical contact between the trench gate 1302 and the adjacent source regions 408 and body regions 406, and may therefore be referred to as a "trench" Gate Oxide".

In one or more embodiments, an additional layer of dielectric material 1306 is formed on the upper surface of trench gate 1302 , filling the trench and substantially flush with the upper surface of epitaxial layer 404 . Subsequently, a thin gate oxide layer 1308 (eg, about 3-50 nm) is formed (eg, grown) on the upper surface of epitaxial layer 404 and the upper surface of dielectric material layer 1306 . A planar gate ( G1 ) 416 is formed on the upper surface of the gate oxide layer 1308 . Each planar gate 416 preferably comprises polysilicon and is formed using standard chemical vapor deposition (CVD) processes, followed by patterning (eg, using standard photolithography and etching). In this illustrative embodiment, there are two planar gates 416 arranged on either side of recessed trench gate 1302 . Although not explicitly shown in FIG. 13, the planar gate 416 and the trench gate 1302 may be formed as fingers (ie, lift-off) structures that are physically separated from each other, with the planar gate and the trench gate at one end or both of the fingers. Terminal (opposite) electrical connection.

As shown in FIG. 13 , the thickness of the trench gate oxide layer 1304 of the trench gate 1302 is substantially constant. It should be appreciated, however, that in one or more alternative embodiments, the thickness of trench gate oxide 1304 may be varied such that trench gate 1302 has a tapered profile. For example, in one or more embodiments, trench gate oxide 1304 may be formed to have a thickness greater at the bottom of the trench than at the upper portion of the trench, which is similar to the exemplary trench gate 920 shown in FIG. 9I . formation is consistent.

As shown in FIG. 13 , by separating the gate 418 shown in FIG. 10 into a planar gate 1310 and a recessed trench gate 1302 (recessed gate), the recessed trench gate 1302 is recessed in the MOSFET device 1300 below the upper surface, whereby the coupling capacitance between the drain terminal and the control gate (G2) is beneficially reduced when the trench gate 1302 is grounded and acts as a shield gate during the turn-off cycle, resulting in a The 1300 offers improved high frequency switching performance.

In an optional embodiment of the present invention, the plane grid 1310 can be removed (specifically, as shown in FIG. 17 , it is an example of removing the plane grid 1310 ). In the case of removing the planar gate 1310, due to the recess of the trench gate, the overlapping area with the planar gate becomes smaller, the distance is further turned and enlarged, and the coupling capacitance is significantly reduced, so the object of the present invention can also be achieved.

In another optional implementation manner of the present invention, the planar gate can also be set in a shape similar to the T-shaped gate shown in FIG. 6 , which can also achieve the purpose of the present invention.

In short, since the trench gate is very close to the source region, it is easy to be coupled with high voltage. If this capacitance is too large, the high voltage coupled by the trench gate will be easily further coupled to the planar gate. If the coupling voltage exceeds the threshold voltage , the device is turned on by mistake. The arrangement of the MOSFET device 1300 of FIG. 13 and its optional embodiments of the present invention can further reduce the capacitance between the planar gate and the trench gate (compared to the MOSFET devices shown in FIGS. 1 to 12 ), thereby solving the technical problem .

In some applications, such as in DC-DC voltage regulators, trench gate 1302 can also be used to form capacitors integrated on the same substrate as MOSFET devices and other circuit components, which is more efficient than traditional capacitor structures. For example, FIG. 14 shows a cross-sectional view of at least a portion of an exemplary capacitor 1400 that includes a trench structure suitable for integration with MOSFET devices and other circuit components on a common substrate. 14, a capacitor 1400 includes a trench structure including a conductive or semiconducting material 1402 (eg, polysilicon) forming a first plate of the capacitor, surrounded by a layer of dielectric material 1404, and forming a second plate of the capacitor Substrate material 404 .

The trench structures are preferably fabricated in a manner consistent with the formation of trench gate structures of the MOSFET device 1300 shown in FIG. 13 . More specifically, in one or more embodiments, the trench structure of capacitor 1400 is formed by forming an opening (eg, a trench or channel) extending partially through epitaxial region 404 and filling the opening with dielectric material 1404 . to manufacture. Alternatively, a dielectric material 1404 may be deposited or grown on the sidewalls of the opening. Like the dielectric material 1304 shown in FIG. 13, the dielectric material 1404 may include an oxide (eg, silicon dioxide), although the invention is not limited to any particular insulating material. After the opening is partially formed through the dielectric material 1404 in the trench, the opening is filled with the conductive or semiconductive material 1402 forming the first plate of the capacitor 1400 . Thus, the dielectric material 1404 electrically isolates the conductive or semiconductor material 1402 from the surrounding epitaxial region 404, thereby preventing direct electrical contact between the first and second plates.

More dielectric material is then deposited/grown in the trenches on the upper surface of the conductive or semiconductor material 1402 so that the upper surface of the trenches is substantially planar with the upper surface of the epitaxial layer 404 . Subsequently, an insulating layer 1406 is formed on the upper surface of the trench and epitaxial layer 404 .

15 shows an electrical schematic diagram of at least a portion of an exemplary switching DC-DC voltage regulator circuit 1500, applied as a Buck converter, in which various aspects of one or more embodiments of the present invention may be utilized. The voltage regulator circuit 1500 includes a first MOSFET device M1 (which may be referred to herein as a high side device) and a second MOSFET device M2 (which may be referred to herein as a low side device). The drain (D) of the high side device M1 is connected to the input voltage V _IN , the source (S) of M1 is connected to the output switching node SW, and the gate (G) of M1 is connected to the first driver circuit 1502 . The drain of the low side device M2 is connected to the output switch node SW, the source of M2 is connected to ground, or an alternative voltage return of the circuit 1500 , and the gate of M2 is connected to the second driver circuit 1504 .

The first and second driver circuits 1502, 1504 form part of a controller circuit 1506 for generating first and second control signals provided to the gates of the MOSFET devices Ml and M2, respectively. The first drive circuit 1502 is coupled between the switch node SW and the boot supply voltage BOOT, and the second drive circuit 1504 is coupled between the drive supply voltage _VDR and ground. In one or more embodiments, each of the driver circuits 1502, 1504 may be implemented using an inverter. The driver supply voltage V _DR is preferably provided to the second driver circuit 1504 , and the boot supply voltage BOOT is preferably provided to the first driver circuit 1502 . Diode D1 is connected, it has an anode coupled to the driver supply voltage _VDR , and has a cathode connected to the boot supply voltage. The capacitor C1 is preferably connected between the boot supply voltage BOOT and the switching node SW. Diode D1 and capacitor C1 together form a bootstrap circuit for generating a voltage V _G high enough (V _G not shown) to fully turn on the N-channel MOSFET as a high-side switch, which is usually the MOSFETs are required for high-side transistors in Buck converters.

The voltage regulator circuit 1500 also includes an input capacitor C _IN connected between the input voltage V _IN and ground, and an output capacitor C _OUT connected between the regulated output voltage V _OUT and ground. An output inductor L _OUT coupled between the switch node SW and the output of the voltage regulator circuit 1500 is used to generate the regulated output voltage V _OUT . Inductor L1 and output capacitor C _OUT together may serve as an energy storage element for regulator circuit 1500 .

When the capacitor 1400 shown in FIG. 14 is used in a DC-DC voltage regulator application (eg, the voltage regulator circuit 1500 shown in FIG. 15 ), the first plate of the capacitor (including the conductor/semiconductor material 1402 in the trench) Ground (eg, one or both ends of the trench) is preferred, and the second plate of the capacitor is connected to the input voltage V _IN through the drain terminal 414 of the high side MOSFET device M1 . Therefore, the input capacitor C _IN can be implemented using capacitor 1400 and integrated with the MOSFET device. However, since the drain is connected to a high potential voltage, a large depletion region will be formed within the epitaxial layer 404 . The boundary 1408 of the depletion region in the epitaxial layer 404 is conceptually shown in FIG. 14 . This large depletion region results in a reduction in the capacitance of capacitor 1400, which is undesirable.

In order to increase capacitance without significantly increasing the area consumed by the capacitor, the illustrative capacitor 1400 of FIG. 14 may be modified as shown in FIG. 16 . Specifically, FIG. 16 is a cross-sectional view illustrating at least a portion of an exemplary capacitor 1600 including a trench structure in accordance with one or more embodiments of the present invention, the exemplary capacitor 1600 including a trench structure, similar to the exemplary capacitor 1400 shown in FIG. 14 . Consistent, it has been modified to provide increased capacitance.

Referring now to FIG. 16, capacitor 1600 includes a first doped region 1602 of the same conductivity type as epitaxial layer 404, in this embodiment an N+ region, formed in the epitaxial layer near its upper surface. N+ regions 1602 are formed on opposite sides of trench structures 1402 , 1404 . The second doped region 1604 has a conductivity type opposite to the polarity of the first doped region 1602 in this embodiment, which is also a P+ region in this embodiment, and is formed in the epitaxial layer 404 and close to its upper surface. Each P+ region 1604 has a first end adjoining the corresponding N+ region 1602 and has a second end opposite the first end adjoining the corresponding sidewall of the trench 1404 . N+ regions 1602 are connected to corresponding P+ regions 1604 using conductive material 1606 formed on at least a portion of the upper surfaces of the N+ and P+ regions. In one or more embodiments, the conductive material 1606 used as the electrode of the capacitor 1600 is preferably formed using a silicide process.

With this improved design of capacitor 1600, drain 414 is at a high potential and holes are the predominant carriers in P+ region 1604. In addition, the P+ region 1604 will act as a hole source supplying holes along the periphery of the trench dielectric layer 1404 . This creates a narrower depletion region in the device, conceptually described as boundary 1608. When the voltage potential between the electrode 1606 and the ground increases by more than a specified amount, an inversion layer 1610 is formed at the oxide semiconductor interface near the periphery of the trench 1404 . The inversion layer 1610 serves as the second plate of the capacitor 1600 . Depletion region 1608 is connected to heavily doped p-type polysilicon layer 1604, which in turn is connected to heavily doped n-type polysilicon 1602 via silicide layer 1606. As the voltage potential increases further, the width of the depletion region 1608 does not increase significantly because the charge in the inversion layer 1610 increases exponentially with the surface potential. In this manner, the capacitance of capacitor 1600 is beneficially increased.

In the illustrative DC-DC buck regulator circuit 1500, the source node of high-side MOSFET device M1 is connected to the drain node of low-side MOSFET device M2, and the voltage on the source node of M1 may ring to a high voltage. To reduce this potential ringing voltage, a decoupling capacitor may be placed between the drain of the high side device M1 connected to the input voltage V _IN and ground. The decoupling capacitor is preferably placed as close as possible to the drain of the high side device M1. Traditionally, however, such decoupling capacitors are packaged with power devices, which introduces some parasitic loop inductance. This parasitic loop inductance will weaken the filtering effect of the decoupling capacitor. To minimize this parasitic loop inductance, it is best to integrate decoupling capacitors into the switches. A portion of the control gate in the trench can be used as a decoupling capacitor.

17 illustrates a cross-sectional view of at least a portion of an exemplary power supply structure 1700 in accordance with one or more embodiments of the present invention. On a common substrate 1706, a power structure 1700 integrates one or more power MOSFET devices 1702, each formed in a manner consistent with the illustrative MOSFET device 1300 shown in FIG. 13, and one or more capacitor devices 1704, Each capacitor device is formed in a manner consistent with the illustrative capacitor shown in FIG. 16 . Advantages of power structure 1700 include reducing coupling capacitance between the planar gate (gate) and control gate (CG) in MOSFET device 1702, increasing the capacitance of trench capacitor 1704, reducing parasitic inductance, and thus reducing vibration in integrated devices. Bell and other advantages.

Accordingly, with reference to the illustrative embodiments shown in Figures 13-17, aspects of the present invention advantageously provide a high density capacitor formed using processes and structures that are compatible with MOSFET devices. In this way, capacitors according to embodiments of the present invention can be easily monolithically integrated with power MOSFET transistors, which is an effective way to overcome the voltage ringing problem that plagues conventional buck converter circuits.

At least some of the techniques of this disclosure may be implemented in integrated circuits. In the formation of integrated circuits, the same molds are typically fabricated in an iteratively patterned manner on the surface of a semiconductor wafer. Each mold includes the devices described herein, and may also include other structures and/or circuits. Individual dies are cut from wafers and then packaged into integrated circuits. Those skilled in the art will know how to cut and package dies from wafers to form integrated circuits. Any exemplary structure or circuit shown in the figures, or a portion thereof, may be part of an integrated circuit. Such integrated circuit fabrication methods are also considered to be part of the present invention.

It will be understood by those skilled in the art that the above-described exemplary structures in one or more embodiments of the present invention may be used in raw form (ie, a single wafer with multiple unpackaged chips), bare chips, or in packaged form, or As a component of intermediate products or end products, it is used in devices with power MOSFETs, such as radio frequency (RF) power amplifiers, power management integrated circuits, power system integration, etc.

Essentially any high frequency, high power application and/or electronic system, such as, but not limited to, radio frequency power amplifiers, power management integrated circuits, etc., can use integrated circuits consistent with the present disclosure. Systems suitable for implementing embodiments of the present invention may include, but are not limited to, DC-DC converters/voltage regulators. Systems incorporating such integrated circuits are considered part of the present invention. Given the teachings of the present invention provided herein, those of ordinary skill in the art will be able to consider other implementations and applications of embodiments of the present invention.

The examples herein of embodiments of the invention are intended to provide a general understanding of the various embodiments, and are not intended to be a complete description of all elements and features of the devices and systems in which the circuits and techniques of the invention may be used. Based on the teachings herein, many other embodiments will become apparent to those skilled in the art, or derived therefrom, so that structural and logical modifications can be made without departing from the scope of the present disclosure. Replace and change. The drawings are also representative and not drawn to scale. Accordingly, both the specification and the drawings are to be regarded in an illustrative rather than a restrictive sense.

The various embodiments of the invention recited herein, individually and/or collectively, refer to the word "embodiment", which is for convenience only and is not intended to limit the scope of application of the invention to any single or Several embodiments or inventive concepts. Thus, although specific embodiments have been illustrated and described herein, it should be understood that arrangements that achieve the same purpose of the invention may be substituted for the specific embodiments shown; that is, the invention is intended to cover various embodiments of any and all adaptations or changes. Combinations of the above-described embodiments, as well as other embodiments not specifically described herein, will also be apparent to those skilled in the art.

The terminology used herein is used to describe specific embodiments only, and not to limit the invention. The singular form of an article as used herein may also include the plural form unless the context clearly indicates otherwise. Further, when "comprising" and/or "comprising" are used in this specification, only the presence of the stated features, steps, operations, elements and/or components does not preclude the presence or addition of one or more other Features, steps, operations, elements, components and/or components thereof. Rather, terms such as "above", "below", "above" and "below" are used to denote relative positional relationships between elements or structures, rather than absolute positions.

Based on the teachings of the embodiments of the present invention, those of ordinary skill in the art can perform other implementations and applications of the technologies of the embodiments of the present invention. Although illustrative embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that the embodiments of the invention are not limited to these precise embodiments, without departing from the scope of the claims. Various other modifications may be made to the embodiments herein by those skilled in the art.

Claims (20)

1. A metal oxide semiconductor field effect transistor device, comprising:

-a semiconductor substrate having a first conductivity type, said substrate serving as a drain region of said mosfet;

-an epitaxial region of a first conductivity type provided on an upper surface of the substrate;

a plurality of body regions of a second conductivity type formed in the epitaxial region, the second conductivity type being opposite the first conductivity type, the body regions being disposed adjacent an upper surface of the epitaxial region and laterally spaced apart from one another;

a plurality of source regions of a first conductivity type, each of the source regions being disposed in a corresponding body region and adjacent to an upper surface of the body region; and

-a gate structure comprising: one or more planar gates and a trench gate,

each planar gate is positioned on the upper surface of the epitaxial region and is overlapped with at least one part of the corresponding body region;

the trench gate is formed in at least part of the epitaxial region and between the body regions; an upper surface of the trench gate is configured to be recessed in the upper surface of the epitaxial region.

2. The device of claim 1, wherein the trench gate comprises:

a conductor or semiconductor structure; and

a dielectric layer at least surrounding the sidewalls, bottom and top of the conductor or semiconductor structure, the dielectric layer electrically isolating the conductor or semiconductor structure from the epitaxial region.

3. The device of claim 1, wherein the plurality of planar gates and the trench gate form finger structures physically separated from each other, the finger structures being electrically connected together by one or both ends thereof.

4. The device of claim 1, wherein at least one of the trench gate and the planar gate comprises a doped polysilicon material.

5. The device of claim 1, wherein the gate structure is configured to form a channel in each body region under the planar gate when a forward bias voltage applied exceeds a threshold voltage of an n-channel metal oxide semiconductor field effect transistor device, thereby turning on the device; meanwhile, a strong accumulation layer of majority carriers is formed in the epitaxial region close to the surface of the trench gate.

6. The device of claim 5, wherein the gate structure is configured such that a concentration of majority carriers in the device is a function of a bias voltage applied to the trench gate.

7. The device of claim 1, further comprising a dielectric layer disposed between the trench gate and the adjacent epitaxial region, the dielectric layer comprising:

a first portion forming a trench gate bottom wall and extending partially up to a sidewall of the trench gate; and

a second portion which is a side wall of the trench gate and extends upwards to the upper surface of the epitaxial region;

the first portion has a first thickness, the second portion has a second thickness, and the first thickness is greater than the second thickness.

8. The device of claim 1 further comprising at least two doped regions of a second conductivity type formed in respective body regions and adjacent to said upper surfaces of said body regions and laterally adjacent to said respective source regions, said two doped regions forming respective body region contacts of said device.

9. The device of claim 1, wherein each body region has a doping concentration of 5 x 10¹⁶Atom/cm³To 1X 10¹⁸Atom/cm³。

10. The device of claim 1, further comprising a plurality of gate electrodes electrically connected to the respective planar and trench gates of the gate structure; each of the gate electrodes includes a metal silicide layer formed on at least a portion of an upper surface of a corresponding one of the planar gate and the trench gate.

11. The device of claim 1, further comprising at least two recessed source region contacts, each source region contact being formed at a respective one of the body regions and adjacent to the upper surface of the body region and electrically connected to and in adjacent position to a respective one of the source regions.

12. A method of fabricating a metal oxide semiconductor field effect transistor device, the method comprising:

forming an epitaxial region of a first conductivity type on at least a portion of an upper surface of a substrate of the first conductivity type, the substrate serving as a drain region of the mosfet;

forming a plurality of body regions of a second conductivity type opposite in polarity to the first conductivity type in the epitaxial region, the body regions being disposed adjacent an upper surface of the epitaxial region and laterally spaced apart from one another;

forming a plurality of source regions having a first conductivity type, each of the source regions being disposed in a corresponding body region and adjacent to an upper surface of the body region; and

forming a gate structure including one or more planar gates and a trench gate, each planar gate being disposed on the upper surface of the epitaxial region and overlapping at least a portion of a corresponding body region; the trench gate is formed in at least part of the epitaxial region and between the body regions; an upper surface of the trench gate is configured to be recessed in the upper surface of the epitaxial region.

13. The method of claim 12, further comprising configuring the gate structure,

such that when an applied forward bias voltage exceeds the threshold voltage of an n-channel mosfet device, a channel is formed in each body region under the planar gate, thereby turning on the device; meanwhile, a strong accumulation layer of majority carriers is formed in the epitaxial region close to the surface of the trench gate.

14. The method of claim 12, wherein the step of forming the trench gate comprises:

forming a conductor or semiconductor structure; and

and forming a dielectric layer at least surrounding the side wall, the bottom and the top of the conductor or the semiconductor structure, wherein the dielectric layer electrically isolates the conductor or the semiconductor structure from the epitaxial region.

15. The method of claim 12, further comprising forming the plurality of planar gates and the trench gate as fingers physically separated from each other, the fingers being electrically connected together by one or both ends thereof.

16. A capacitor, comprising:

a semiconductor substrate having a first conductivity type;

an epitaxial region having a first conductivity type disposed on at least a portion of the upper surface of the substrate, the epitaxial region constituting a first plate of the capacitor;

the trench gate is formed in at least part of the epitaxial region and is close to the upper surface of the epitaxial region; the trench gate comprising a conductor or semiconductor material forming a second plate of the capacitor surrounded by a dielectric layer electrically isolating the conductor or semiconductor from the epitaxial region;

a plurality of doped regions of the first conductivity type disposed in the epitaxial region and on opposite sides of the trench gate and proximate an upper surface of the epitaxial region; and

a plurality of doped regions of a second conductivity type opposite in polarity to the first conductivity type, each doped region of the second conductivity type having a first end adjacent a respective one of the doped regions of the first conductivity type and a second end opposite the first end and adjacent a respective sidewall of the trench gate.

17. A capacitor according to claim 16, wherein the upper surface of the conductor or semiconductor is arranged to be recessed below the upper surface of the epitaxial region.

18. The capacitor of claim 16, further comprising a second dielectric layer disposed on an upper surface of said conductor or semiconductor forming said trench gate.

19. A method of manufacturing a capacitor, the method comprising:

forming an epitaxial region of a first conductivity type on at least a portion of an upper surface of the substrate, the epitaxial region constituting a first plate of the capacitor;

forming a trench gate in at least part of the epitaxial region and close to the upper surface layer of the epitaxial region; the trench gate contains a conductor or semiconductor material that serves as a second plate of the capacitor and is surrounded by a dielectric layer that electrically isolates the conductor or semiconductor from the epitaxial region;

forming a plurality of doped regions with a first conductivity type on opposite sides of the trench gate in the epitaxial region and near an upper surface of the epitaxial region; and

forming a plurality of doped regions having a second conductivity type, the second conductivity type being opposite in polarity to the first conductivity type; a first end of each of the doped regions of the second conductivity type abuts a respective one of the doped regions of the first conductivity type and a second end opposite the first end abuts a respective sidewall of the trench gate.

20. The method of claim 19, wherein the method comprises:

when the trench gate is formed, the method includes recessing an upper surface of the conductor or semiconductor below the upper surface of the epitaxial region.

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