CN115188812A - MOSFET with split planar gate structure - Google Patents

Abstract

The invention relates to a metal oxide semiconductor field effect transistor (MOSFET) device having a split planar gate structure, which includes an epitaxial region formed on the upper surface of a substrate and at least two body regions formed in the epitaxial region. The body regions are located adjacent to the upper surface of the epitaxial region and are laterally spaced apart from each other. The device also includes at least two source regions disposed in corresponding body regions and proximate the upper surface of the body regions, and a gate structure including at least two planar gates and one trench gate. Each planar gate is located on the upper surface of the epitaxial region and overlaps at least a portion of the corresponding body region. the trench gate is located between the two body regions and at least partially within the epitaxial region, and also forms laterally overgrown sidewalls over the upper surface of the epitaxial region; and is located on the backside of the substrate and electrically connected to the substrate connected drain contact.

Description

Metal-oxide-semiconductor field-effect transistor with split planar gate structure

technical field

The present invention relates generally to electrical, electronic and computer technology, and more particularly to power transistor devices and methods of manufacture

Background technique

Power transistors, such as power metal-oxide-semiconductor field-effect transistors (MOSFETs), are typically designed to maintain a high drain-source current density in the on-state and a high blocking voltage between source and drain in the off-state. There are many transistor device types, such as lateral and vertical devices, planar and trench gate, unipolar and bipolar transistors, each designed for a specific application. Many design parameters are mutually exclusive, so improvement in one parameter leads to degradation in another. Therefore, there is a special performance trade-off in different transistor designs.

Transistor design and performance criteria can be measured by several properties, including drain-source breakdown voltage (BV _ds ), characteristic on-resistance (R _sp ), gate capacitance (C _g ), and gate-drain capacitance (C _gd ). These performance characteristics are highly dependent on factors such as transistor design, structure, and material selection. Furthermore, these transistor performance characteristics typically follow opposite trends on key design parameters such as gate length, channel and drift region doping concentrations, drift region length, overall gate width, etc., allowing transistor device designs with challenge. For example, increasing the doping concentration of the drift region in a transistor reduces the characteristic on-resistance and also reduces the breakdown voltage, which may prevent the transistor device from meeting the breakdown voltage rating for a particular application. Likewise, a larger gate width can reduce the overall on-resistance of the transistor device, but it also increases parasitic gate capacitance, thereby increasing the switching losses of the transistor. Therefore, in the practice of transistor design, it often involves the trade-off of certain key design parameters in order to reach a compromise between various performance characteristics.

An important performance parameter that determines the efficiency and reliability of transistor devices is Miller capacitance, or gate-to-drain capacitance. With the increasing demand for higher efficiency, power MOSFET designs are trending towards smaller gate sizes, resulting in lower gate charge (Q _g ) and lower threshold voltage (V _t ) due to Miller capacitive coupling effect, making the device more susceptible to drain voltage spikes. At the same time, higher transistor switching frequencies, along with increased parasitic inductance, lead to increased drain ringing voltage. The combined effect of these effects makes today's power transistor devices prone to spurious turn-on caused by drain voltages that can damage the device. Another very challenging fact is reducing the Miller capacitance and, as a design compromise, often leads to an increase in the on-resistance of the device. Common methods of reducing parasitic gate-to-drain capacitance inevitably result in higher device on-resistance, so reducing Miller capacitance in power transistor devices can be one of the most difficult design goals to achieve, as well as a critical factor for product performance and application reliability. critical need.

SUMMARY OF THE INVENTION

The purpose of this invention is to overcome the above-mentioned disadvantages of the prior art, and to provide an enhancement gate structure advantageously provided for an LDMOS transistor device and a method for manufacturing the same. This gate structure facilitates compatibility with existing complementary metal-oxide-semiconductor (CMOS) fabrication technologies and does not rely on the use of esoteric and expensive processes and materials, eg, silicon carbide (SiC), gallium nitride (GaN) etc., under the premise of not significantly reducing the blocking voltage of the device and the reliability of the device, the on-resistance of the device can be greatly reduced.

In order to achieve the above-mentioned purpose, this invention has the following constitution:

According to an embodiment of the present invention, a metal oxide semiconductor field effect transistor (MOSFET) device includes an epitaxial region having a first conductivity type disposed on an upper surface of a substrate, and a second conductivity type formed in the epitaxial region At least two body regions, the second conductivity type has an opposite conductivity type to the first conductivity type. The body regions are distributed proximate the upper surface of the epitaxial region and are laterally spaced from each other. The device also includes at least two source regions of the first conductivity type disposed in each respective body region and proximate an upper surface of the body region, and includes at least two planar gates and a trench gate gate structure. Each of the planar gates is disposed on the upper surface of the epitaxial region and overlaps at least a portion of the corresponding body region. A trench gate is partially formed in the epitaxial region and between the body regions, and the trench gate forms laterally overgrown sidewalls on the upper surface of the epitaxial region to partially cover the upper surface of the epitaxial region. A drain contact disposed on the backside of the substrate provides electrical connection to the substrate.

According to an embodiment of the present invention, a method of fabricating the MOSFET device includes: forming an epitaxial region having a first conductivity type on an upper surface of a substrate having a first conductivity type; forming an epitaxial region having a second conductivity type in the epitaxial region at least two body regions, the second conductivity type is opposite to the conductivity type of the first conductivity type, the body regions are disposed close to the upper surface of the epitaxial region and are laterally spaced from each other; forming a at least two source regions, each of which is respectively disposed in a corresponding corresponding body region near the upper surface of the body region; forming a gate structure including at least two planar gates and one trench gate, The planar gates are all disposed on the upper surface of the epitaxial region and overlap with at least a portion of the corresponding body region, the trench gate portion is formed in the epitaxial region, and is located between the body regions, and the trench gate is in the A lateral overgrown sidewall is formed on the upper surface of the epitaxial region to partially cover the upper surface of the epitaxial region; and a drain contact is formed on the backside of the substrate and electrically connected to the substrate.

The techniques of the present invention can provide substantial beneficial technical effects. By way of example only and not by way of limitation, the LDMOS in one or more embodiments of the present invention may provide one or more of the following beneficial effects:

Lower on-resistance R _DS-on

Lower gate-to-drain (Miller) capacitance;

Lower switching losses;

• Higher off-state blocking voltage.

These and other features and advantages of the present invention will be elucidated from the following detailed description in the illustrative embodiments taken in conjunction with the accompanying drawings.

Description of drawings

The embodiments of the invention described below with reference to the accompanying drawings, which are by way of example only, are non-limiting and non-exhaustive. Unless otherwise specified, reference numerals used in the figures identify the same elements throughout the several views.

1A and 1B are, respectively, cross-sectional views of at least a portion of a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET) device including on-resistance and parasitic gate-drain capacitance diagrams;

2A-2C are at least a portion of cross-sectional views of trench gate MOSFET devices showing reduced on-resistance and illustrating some of the effects of varying body region depth in the device;

3A-3C are at least a portion of cross-sectional views of a split trench gate MOSFET device showing reduced parasitic gate-to-drain capacitance and increased off-state blocking voltage, and illustrating some of the effects of body region depth variation in the device influences;

Figure 4A represents a perspective view of at least a portion of a Supergate MOSFET device of one embodiment of the present invention;

4B is a cross-sectional view of the super-gate MOSFET device along A-A' in FIG. 4A;

4C is a cross-sectional view of the super-gate MOSFET device shown in FIG. 4B with an accumulation layer formed adjacent to the trench gate structure;

Figure 5 conceptually depicts the relationship between the characteristic on-resistance R _SP and breakdown voltage of three different types of MOSFET devices;

Figure 6 shows a perspective view of at least a portion of a Super Gate MOSFET device of another embodiment of the present invention;

7A to 7I are schematic cross-sectional views of the manufacturing process of at least a portion of the super-gate MOSFET device according to an embodiment of the present invention shown in FIG. 4B;

8 is a cross-sectional view of at least a portion of a super-gate MOSFET device having an enhanced voltage blocking capability gate structure in accordance with one embodiment of the present invention;

9A to 9L are schematic cross-sectional views of the manufacturing process of at least a portion of the super-gate MOSFET device according to one embodiment of the present invention shown in FIG. 8;

10 is a cross-sectional view of at least a portion of a super-gate MOSFET device with enhanced source contacts in one embodiment of the present invention;

Figure 11 is a schematic diagram of the drain voltage as a function of time for a super-gate MOSFET device of one or more embodiments of the present invention compared to a standard MOSFET device; and

12 is a schematic diagram of gate voltage as a function of time for a super-gate MOSFET device according to one or more embodiments of the present invention compared to a standard MOSFET device.

It will be appreciated that elements shown in the figures are for simplicity and clarity of presentation. In a commercially feasible embodiment, some elements that are useful or necessary but which are well known may not be shown in the figures in order to reduce obstruction of the view.

Detailed ways

In order to understand the technical content of the invention more clearly, the following examples are given for detailed description.

The principles of the laterally diffused metal-oxide-semiconductor (LDMOS) devices and methods of fabricating LDMOS devices of the present invention will be described herein in one or more embodiments and contexts without significant degradation in power and linearity performance. Enhanced high frequency performance. It should be appreciated, however, that the present invention is not limited to the specific devices and/or methods illustratively set forth herein. It is believed that many modifications to the embodiments will become apparent to those skilled in the art in view of the teachings herein, which are within the scope of the present invention as claimed. That is, the embodiments herein are not intended to and should not be construed to limit the present invention.

For purposes of describing embodiments of the present invention, the term MISFET as may be used herein should be construed broadly to include any type of metal-insulator-semiconductor field-effect transistor. For example, MISFETs may include semiconductor field effect transistors (ie, MOSFETs) that utilize oxide materials as gate dielectrics, as well as other semiconductor field effect transistors that do not use oxide materials. In addition, although the word "metal" is mentioned in the acronyms MISFET and MOSFET, MISFET and MOSFET also include semiconductor field effect transistors whose gates are formed of non-metallic materials such as polysilicon, in which case MISFET and MOSFET MOSFETs can be used interchangeably.

Although the overall fabrication methods and structures formed in the present invention are novel, certain individual processing steps required to implement one or more portions of the methods of one or more embodiments of the present invention may utilize conventional semiconductor fabrication techniques and traditional semiconductor manufacturing tools. These techniques and tools are well known to those of ordinary skill in the art. In addition, numerous process steps and tools for the fabrication of semiconductor devices are also documented in a number of existing publications, including, for example: P.H. Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices), Cambridge University Press, 2008; and "Processing and Properties of Compound Semiconductors" by R.K.Willardson et al., Academic Press, 2001, The above documents are incorporated herein by reference. It is emphasized that although some individual processing steps are described herein, these steps are merely illustrative and other equally suitable alternatives that may be familiar to those skilled in the art are also included within the scope of the present invention.

It should be understood that the various layers and/or regions shown in the figures have not necessarily been drawn to scale. Furthermore, for the sake of economy of description, one or more of the semiconductor layers commonly used in the device may not be represented in the integrated circuit device of the figures shown. However, this does not mean that these semiconductor layers, which are not explicitly represented, are omitted in an actual integrated circuit device.

FIG. 1A shows a cross-sectional view of at least a portion of a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET) device 100 . The VDMOSFET device 100 includes a substrate 102, which may be formed from single crystal silicon that has been added with impurities or dopants (eg, boron, phosphorus, arsenic, etc.) to alter the conductivity of the material (eg, N-type or Type P). In this example, the substrate 102 has an N conductivity type, and thus may be referred to as an N-type substrate (N+SUB).

An epitaxial region 104 is formed on the upper surface of the substrate 102 . In this example, the epitaxial region 104 has an N conductivity type (N-EPI) by adding impurities or dopants. In the VDMOSFET device 100, the epitaxial region 104 acts as a lightly doped drift region of the device. Two body regions (P-BODY) having a P-type conductivity type in this embodiment are formed near the upper surface of the epitaxial region 104 and are laterally spaced apart from each other. The VDMOSFET device 100 also includes a source region 108 formed in at least a portion of each body region 106 and proximate the upper surface of the body region. Preferably, the source region 108 can be doped with impurities of known concentration levels using conventional implantation processes, thereby selectively changing the conductivity of the material as desired. For example, the source region 108 is of N-type conductivity type (N+). A heavily doped region 110 formed near the upper surface of the body region 106 has the same conductivity type as the body region 106 (eg, P-type in this example), and is laterally adjacent to the corresponding source region 108 to form the VDMOSFET device 100 . body area contacts. Each of the described source regions 108 is electrically connected to a corresponding body region contact 110 .

In the VDMOSFET structure, the substrate 102 acts as the drain region of the device. A drain contact 112 formed on the backside of the substrate 102 provides electrical connection to the substrate/drain 102 .

A gate 114 is formed over at least a portion of the body region 106 and the epitaxial drift region 104 between the source regions 108 . A thin oxide layer 116 (eg, silicon dioxide SiO ₂ ) is formed under the gate 114 as a gate oxide for electrically isolating the gate from the source region 108 , the body region 106 and the epitaxial region 104 in the VDMOSFET device 100 . Insulating spacers 118 are formed on the sides of the gate electrode 114 and the gate oxide layer 116 to electrically isolate the gate electrode from the source region 108 . As is well known to those skilled in the art, the bias applied to the gate forms a channel in the body region 106 under the gate for controlling current flow between the source region 108 and the substrate 102 as the drain region.

The VDMOSFET device 100 adopts a planar gate structure on the surface of the device, and has the advantages of simple fabrication process and good application reliability. However, the VDMOSFET design also exhibits significant drawbacks, including high on-resistance and large parasitic gate-to-drain capacitance (ie, Miller capacitance), which make this device unsuitable for high-power, high-frequency applications. The higher on-resistance R _ON is mainly attributable to the combination of the P body channel resistance R _BODY (which can be referred to as the MOSFET channel resistance), the junction field effect transistor (JFET) channel resistance R _JFET and the epitaxial drift region resistance R _EPI (i.e. R _ON = R _BODY + R _JFET + R _EPI ). Among them, R _EPI is the main factor (in a 100-volt device, it is more than 50% of the total on-resistance R _ON ).

FIG. 1B is a cross-sectional view of at least a portion of the VDMOSFET device 100 of FIG. 1A showing parasitic gate-to-drain capacitance (Miller capacitance). As shown in FIG. 1B , the larger parasitic gate-to-drain capacitance C _gd is mainly due to the larger overlap between the gate 114 and the epitaxial drift region 104 . Such large parasitic gate-to-drain capacitance C _gd components cause significant switching power losses in high frequency applications and are therefore not suitable.

Efforts have been made to reduce the on-resistance of VDMOSFET devices, thereby increasing the conductivity. In particular, it is desirable to increase the channel density of the VDMOSFET device 100 by reducing the lateral spacing of the body regions 106 . However, the junction field effect transistor effect brought about by the narrower body region spacing increases the JFET resistance R _JFET between the body regions 106 , thereby offsetting the benefits of increased channel density, which always requires between the MOSFET channel resistance R _BODY and the JFET There is a trade-off between channel resistance R _JFET . Likewise, while the JFET channel resistance can be reduced by increasing the doping concentration in the upper surface of the epitaxial region 104 (JFET region), this reduction in JFET channel resistance can also lead to undesired avalanche strikes in the off-state of the device Breakthrough voltage reduction. In this regard, there have also been attempts to use a charge balance method to balance the positive charge in the N-type epitaxial drift region 104 and the negative charge in the P-type body region 106 in the off state of the device to increase the doping of the epitaxial drift region 104 The impurity concentration, thereby reducing the on-resistance _REPI of the drift region, however, for a given dimension, the doping concentration is limited to a specific level, usually below about 10 ¹⁷ /cm ³ .

Figures 2A-2C are at least a portion of cross-sectional views of typical trench gate MOSFET devices 200, 230, and 250, respectively, showing reduced on-resistance and conceptually illustrating some of the effects of body region depth variation in the device . Referring to FIG. 2A, trench gate MOSFET device 200 includes a substrate 202, which may be formed of single crystal silicon formed by adding impurities or dopants having an N conductivity type, and thus may be referred to as N type substrate (N+SUB).

An epitaxial region 204 is formed on the upper surface of the substrate 202 . In this example, the epitaxial region 204 has an N conductivity type (N-EPI) by adding impurities or dopants. Similar to the VDMOSFET device 100 shown in FIG. 1A, in the VDMOSFET device 200, the epitaxial region 204 acts as a lightly doped drift region of the device. In the present embodiment, two body regions (P-BODY) 206 having a P-type conductivity type are formed near the upper surface of the epitaxial region 204 and are laterally spaced apart from each other. The MOSFET device 200 also includes a source region 208 formed in at least a portion of each body region 206 and proximate the upper surface of the body region. Preferably, the source region 208 may be doped with impurities of known concentration levels to have an N-type conductivity type (N+) using conventional implantation processes. A heavily doped region 210 of P conductivity type is formed adjacent to the upper surface of the body region 206 and is laterally adjacent to the corresponding source region 208 to form the source contact of the MOSFET device 200 . Each of the described source regions 208 is electrically connected to a corresponding body region contact 210 .

Similar to the VDMOSFET device 100 shown in FIG. 1A, in this MOSFET device 200, the substrate 202 serves as the drain region of the device. A drain contact 212 formed on the backside of the substrate 202 provides electrical connection to the substrate/drain 202 .

The MOSFET device 200 also includes a trench gate 214 comprising polysilicon formed on the upper surface of the epitaxial region 204 between the body regions 206 and between the source regions 208 . Trench gate 214 may be fabricated by forming channels (ie, trenches) partially through epitaxial regions 204 between body regions 206 and between source regions 208 and filling the channels with dielectric material 216 . The dielectric material is preferably an oxide, such as silicon dioxide. Trench gate 214 then extends vertically partially through dielectric material 216 and beyond source region 208 and body region 206 . The thickness of the sidewalls of the dielectric material 216 surrounding the sidewalls of the trench gate 214 is preferably just enough to prevent direct electrical contact between the trench gate 214 and the adjacent source regions 208 and body regions 206 .

In contrast to the planar gate arrangement in the VDMOSFET device 100 shown in FIG. 1A , the trench gate MOSFET device 200 achieves the advantage of lower on-resistance by eliminating the JFET resistance R _JFET . However, the parasitic gate-to-drain (Miller) capacitance C _gd remains high. As in the trench gate MOSFET device 230 shown in FIG. 2B, by increasing the thickness of the dielectric material 216 at the bottom of the trench, the gate-to-drain capacitance C _gd can be slightly reduced. The trench gate MOSFET device 230 is substantially the same as the device 200 shown in FIG. 2A except that the depth of the body region 206 into the epitaxial drift region 204 is slightly reduced. While device 230 reduces parasitic gate-to-drain capacitance C _gd , a weak point 232 is created between the bottom corner of polysilicon trench gate 214 and epitaxial region 204 that can lead to undesired device breakdown voltage drop.

Further complicating the difficulty of this process of forming a channel within the body region 206 is that in the epitaxial region 204 the depth of the body region must be tightly controlled with respect to the depth of the trench gate 214 . The body region 206 cannot be too shallow, as this can result in a weak point 232 that is prematurely broken down at high blocking voltages, as shown in the MOSFET device 230 shown in Figure 2B. Similarly, as shown in the trench gate MOSFET device 250 in FIG. 2C, the body region 206 also cannot be too deep in the epitaxial region 204, as this would increase the gate near the bottom of the trench gate 214, contrary to what is desired The oxide layer thickness, as represented by thick oxide region 252 in Figure 2C. The thick oxide region 252 in the trench gate MOSFET device 250 reduces gate control of the channel formed in the body region 206, thereby making the device difficult to turn on; that is, the MOSFET device 250 will behave undesirably increase in the device threshold voltage.

3A-3C are at least a portion of cross-sectional views of split trench gate MOSFET devices 300, 330, 350, respectively. As shown in FIG. 3A, the split trench gate MOSFET device 300 includes a substrate 302, which may be formed of single crystal silicon, which is formed by adding impurities or dopants having an N conductivity type, and thus may be referred to as It is an N-type substrate (N+SUB). An epitaxial region 304 is formed on the upper surface of the substrate 302 . In this example, the epitaxial region 304 has an N conductivity type (N-EPI) by adding impurities or dopants. Similar to the VDMOSFET device 100 shown in FIG. 1A and the trench gate MOSFET device 200 shown in FIG. 2A, in the MOSFET device 300, the epitaxial region 304 serves as the lightly doped drift region of the device. In the present embodiment, two body regions (P-BODY) 306 having a P-type conductivity type are formed near the upper surface of the epitaxial region 304 and are laterally spaced apart from each other. The MOSFET device 300 also includes a source region 308 formed in at least a portion of each body region 306 and proximate the upper surface of the body region. Preferably, the source region 308 (N+) with N-type conductivity can be formed by conventional implantation of N-type impurities. In the present embodiment, the heavily doped region 310 formed on the upper surface near the body region 306 has P conductivity type and is laterally adjacent to the corresponding source region 308 to form the body region contact of the MOSFET device 300 . Thus, each of the described source regions 308 is electrically connected to a corresponding body region contact 310 .

Similar to the VDMOSFET device 100 shown in FIG. 1A and the trench gate MOSFET device 200 shown in FIG. 2A, in this split trench gate MOSFET device 300, the substrate 302 serves as the drain region of the device. A drain contact 312 formed on the backside of the substrate/drain 302 provides electrical connection to the substrate/drain 302 .

The MOSFET device 300 also includes a dielectric trench 314 filled with a dielectric material (eg, silicon dioxide) extending vertically in the epitaxial region 304 between the body regions 306 and between the source regions 308 . A trench gate 316 , which may comprise polysilicon, is formed in the dielectric trench 314 with a depth of the trench gate 316 just below the bottom of the body region 306 . A shield gate 318 is also formed in the trench 314 vertically below the trench gate 316 . The dielectric material in dielectric trench 314 electrically isolates shield gate 318 from trench gate 316 and epitaxial region 304 as described. In this embodiment, trench gate 316 is slightly wider than shield gate 318, whereby the shield gate is surrounded by a thicker layer of dielectric material than the trench gate. Preferably, shield gate 318 is connected to source region 308 .

In the MOSFET device 300, the shielded gate 318 helps to reduce the parasitic gate-to-drain capacitance _Cgd and increase the off-state blocking voltage. However, any improvement offered by this split trench gate MOSFET design is only applicable in the device off state, that is, where the maximum doping concentration is determined by the desired breakdown voltage of the device, essentially There is no improvement in on-state performance. Split trench gate designs face similar difficulties in precisely controlling the depth and thickness of the body region 306 .

For example, a split trench gate MOSFET device 330 with a shallow body region 306 as shown in FIG. 3B. As previously described in connection with FIG. 2B, the shallow body region 306 in this MOSFET device 330 creates a weak spot region 332 near the bottom corner of the trench gate 316, which can cause the device to be prematurely shut down at high blocking voltages breakdown.

Likewise, FIG. 3C shows a split trench gate MOSFET device 350 having a deep body region 306 such that the bottom of the body region extends below the bottom of trench gate 316 . As previously described in connection with FIG. 2C , the deep body region 306 in the MOSFET device 350 forms a thick oxide region 352 near the bottom corners of the trench gate 316 , the thick oxide region 352 reduces the impact on the formation of the body region 306 The gate control of the channel in the device increases the threshold voltage of the device, making it difficult for the device to turn on.

As shown in one or more embodiments, the present invention exploits the beneficial properties of planar gate and trench gate structures to provide MOSFET devices with super gate structures that advantageously achieve enhanced high frequency performance without Significantly degrades power and linearity performance in the device. 4A and 4B are respectively a perspective view and a cross-sectional view of at least a portion of a super-gate MOSFET device 400 in one embodiment of the present invention.

The MOSFET device 400 includes a substrate 402, which may be formed from single crystal silicon (eg, having a <100> or <111> crystal orientation) by adding impurities or dopants (eg, boron, phosphorous, arsenic) , antimony, etc.) to form the desired conductivity type (eg, N-type or P-type) and doping level. P-type substrates can be prepared by adding P-type impurities or dopants (eg, Group III elements such as boron) to the substrate material at specified concentration levels (eg, from about 10 ¹⁴ to about 10 ¹⁸ atoms per cubic centimeter). Formation, such as through a diffusion or implantation process, alters the conductive properties of the material as desired. In other embodiments, an N-type substrate may be formed by adding a specified concentration level of N-type impurities or dopants (eg, Group V elements such as phosphorus) to the substrate material. In this embodiment, the substrate 402 is doped to have an N-type conductivity type, and thus may be referred to as an N-type substrate (N+SUB). Similar other materials may be used to form substrate 402, such as, but not limited to, germanium, gallium arsenide, silicon carbide, gallium nitride, indium phosphide, and the like.

An epitaxial region 404 is formed on the upper surface of the substrate 402 . In this example, the epitaxial region 404 has an N conductivity type (N-NPI) by adding impurities or dopants, and similarly, P-type epitaxy (eg, by adding a P-type dopant) is also contemplated. Similar to the VDMOSFET device 100 shown in FIG. 1A and the trench gate MOSFET device 200 shown in FIG. 2A , in the MOSFET device 400 , the epitaxial region 404 serves as the lightly doped drift region of the device. Two body regions (P-BODY) 406 having a P-type conductivity type in this embodiment are formed close to the upper surface of the epitaxial region 404 and are laterally spaced apart from each other. The body region 406 in this embodiment may be formed by implanting a P-type impurity (eg, boron) into designated areas of the epitaxial region 404 using standard complementary metal oxide semiconductor (CMOS) fabrication techniques. The body region 406 preferably employs a heavier doping relative to the doping level of the substrate, eg, from about ^5x1016 atoms/cm ³ to about ^1x1018 atoms/ ^cm3 . In one or more alternative embodiments employing a P-type epitaxial region, the body region 406 may comprise an N-type well formed using CMOS-like fabrication techniques.

The MOSFET device 400 also includes a source region 408 formed in at least a portion of each body region 406 and proximate the upper surface of the body region. Preferably, the source region 408 is doped with impurities of an opposite conductivity type to that of the body region 406 . In this embodiment, the source region 408 is of an N-type conductivity type (N+). In this embodiment, a heavily doped region 410 formed near the upper surface of the body region 406 and laterally adjacent to the corresponding source region 408 has a P-type conductivity, thereby forming the body region contact of the MOSFET device 400 . A corresponding source (S) electrode 412 electrically connects each source region 408 to a corresponding body region contact 410 .

Similar to the VDMOSFET device 100 shown in FIG. 1A, in this MOSFET device 400, the substrate 402 serves as the drain region of the device. A drain (D) contact 414 is preferably formed on the backside of the substrate/drain 402, which provides electrical connection to the substrate/drain. Unlike standard lateral MOSFET devices in which both the drain and source electrodes are formed on the top surface of the device, the drain contact 414 of this MOSFET device 400 is formed on the bottom surface of the device opposite the source electrode 414, that is, the drain Electrode 414 and source electrode 412 are distributed on two vertically opposite surfaces of the MOSFET device 400 .

The MOSFET device 400 also includes a gate structure that includes at least two parts, a planar gate (G1) 416 and a trench gate (G2) 418. In the illustration of this embodiment, two planar gates 416 are respectively disposed on two sides of the trench gate 418 . The planar gate 416 and the trench gate 418 are preferably formed as comb-like (striped) structures that are structurally separated from each other, even if the planar gate and the trench gate are electrically connected at one or both ends of their striped structures (not explicitly shown in the figure, but hidden). contains). In one or more alternative embodiments, planar gate 416 and trench gate 418 may form a connected gate structure with planar and trench gate functionality, as described in further detail below in conjunction with FIG. 6 .

In one or more embodiments, trench gate 418 , which may include polysilicon, may generally be formed vertically through the upper surface of epitaxial region 404 located between body regions 406 and also between source regions 408 , such that the trench gates 418 in the trenches Gate 418 has a source region 408 on both sides. More specifically, trench gate 418 may be fabricated by opening (ie, trenching) epitaxial region 404 between two body regions 406 (and source region 408 ) and filling the opening with dielectric material 420 . In one or more embodiments, the dielectric material 420 is an oxide, such as silicon dioxide, although the invention is not limited to any particular electrically insulating material. The trench gate 418 is then formed partially through the dielectric material 420 , extending vertically further below the source region 408 and the body region 406 . Thus, the dielectric material 420 electrically isolates the trench gate 418 from the surrounding epitaxial region 404, thereby preventing direct electrical contact between the trench gate 418 and the adjacent source regions 408 and body regions 406, and thus the dielectric material 420 May be referred to as trench gate oxide. The trench gate 418 may further include forming laterally overgrown sidewalls on the upper surface of the epitaxial region 404 to partially cover the upper surface of the epitaxial region 404 .

In one or more embodiments, each planar gate 416 is disposed on the upper surface of the epitaxial region 404 at least partially overlapping the corresponding body region 406 . A dielectric layer 422 is formed between each planar gate 416 and the upper surfaces of the body region 406 and epitaxial region 404 to electrically isolate the planar gate 416 from the body region and epitaxial region, and thus may be referred to as a planar gate oxide layer. Although not explicitly shown in FIG. 4A , as shown in FIG. 4B , dielectrics are preferably formed on the sidewalls of the planar gate 416 and the sidewalls of the lateral overgrown portions of the trench gate 418 extending over the upper surface of the epitaxial layer 404 . Electrical sidewall 424. As shown in FIG. 4B , gate spacers 424 electrically isolate the planar gate from the trench gate and electrically isolate the planar gate 416 from the corresponding source electrode 412 .

With continued reference to FIG. 4B , the MOSFET device 400 also includes a first gate electrode 426 connected to the planar gate 416 and a second gate electrode 428 connected to the trench gate 418 . Gate electrodes 426 and 428 may be implemented by forming a metal silicide layer on at least a portion of the upper surfaces of gate electrodes 416 and 418, respectively. As known to those skilled in the art, in the gate silicidation process, a metal film (eg, titanium, tungsten, platinum, cobalt, nickel, etc.) is deposited on the upper surface of the polysilicon gate, and the deposited metal film is annealed to make the polysilicon Reactions occur between the silicon in the gate, eventually forming a metal silicide contact.

When a positive bias voltage in excess of the threshold voltage is applied to an N-channel MOSFET device, such as by applying a positive voltage between the planar gate 416 and the corresponding source region 408, a channel is formed in the body region 406 under the planar gate, thereby The MOSFET device 400 is turned on. At the same time, since the trench gate 418 is electrically connected to the planar gate 416, a positive bias voltage will be applied to the trench gate, thereby forming a surface with a majority of the epitaxial region 404 near the surface of the trench gate oxide 420 as shown in Figure 4C A strong accumulation layer 430 of carriers, such as electrons in this embodiment. This accumulation layer 430 beneficially increases the conductance of the MOSFET device 400, which enables the device to achieve very low on-resistance, for example, about two milliohm-square millimeters (2 mΩ at a blocking voltage rating of 30 volts) -mm ² ). As will be described below, the super gate MOSFET device 400 achieves substantial performance improvements over conventional planar gate and trench gate devices.

Figure 5 conceptually depicts the proportional relationship between characteristic on-resistance R _SP (ohm-square centimeter) and breakdown voltage (volts) for three different types of MOSFET devices. In particular, reference numeral 502 represents the proportional relationship between the characteristic on-resistance R _SP and breakdown voltage of a trench gate MOSFET device consistent with the trench gate MOSFET device 200 shown in FIG. 2A . Reference numeral 504 represents the proportional relationship between the characteristic on-resistance R _SP and breakdown voltage of a split trench gate MOSFET device consistent with the split trench gate MOSFET device 300 shown in FIG. 3A . Reference numeral 506 represents the proportional relationship between the characteristic on-resistance R _SP and the breakdown voltage of a super-gate MOSFET device formed in accordance with one or more embodiments of the present invention, such as the super-gate MOSFET device 400 shown in FIG. 4A . . Ideally, MOSFET devices will exhibit high breakdown voltage and low characteristic on-resistance, however, in practice, device characteristics are often conflicting, that is, MOSFET devices with very low on-resistance will also Has very low breakdown voltage, and vice versa, as in the trench gate and split trench gate MOSFET devices shown at 502 and 504, respectively.

As shown in FIG. 5, a super gate MOSFET device (reference numeral 506) formed in accordance with embodiments of the present invention has at least two distinct features compared to a trench gate MOSFET device (reference numeral 502) or a split trench gate MOSFET device (reference numeral 504). The advantages. First, the slope representing the proportional relationship between characteristic on-resistance R _SP and breakdown voltage 506 is significantly reduced compared to 502 and 504 , i.e. in a trench gate MOSFET device with the same breakdown voltage rating or split trench Super-gate MOSFET devices have significantly lower characteristic on-resistance than gate MOSFET devices. As a result, the size of the chip can be scaled down in proportion to the size of the chip, further resulting in a significant reduction in parasitic gate capacitance and gate-to-drain capacitance.

Normally, the capacitance value C of the parallel plate capacitor is determined according to the following formula:

where ε ₀ is the absolute permittivity (i.e. vacuum permittivity ε ₀ = 8.854×10 ⁻¹² F/m, ε _r is the relative permittivity of the medium or dielectric material between parallel plates, A is each The surface area of one side of the parallel plates, d is the distance between the parallel plates (i.e., the thickness of the dielectric material between the parallel plates). Therefore, by reducing the chip size, parasitic gate capacitance and/or parasitic gate leakage can be reduced The surface area of one or two parallel plates of the capacitor. Parasitic gate capacitance and gate-to-drain capacitance reduction is beneficial for reducing switching losses in high frequency applications such as synchronous DC-DC converters.

Continuing to refer to FIG. 5, as indicated by the trapezoidal shape of reference numeral 506, a second significant advantage of the Supergate MOSFET device of embodiments of the present invention is that the Supergate MOSFET device is capable of adjusting the characteristic on-resistance during device operation, while the Conventional MOSFET devices have a fixed characteristic on-resistance. This is primarily due to the fact that in conventional MOSFET designs, the doping concentration, and its associated carrier concentration, are fixed after the device is fabricated. In contrast, in the super-gate MOSFET devices of one or more embodiments of the present invention, the carrier concentration is not fixed, but depends on the bias voltage applied to the trench gate structure, which can be easily adjusted of. This brings many benefits, including greater flexibility in device design, a wider process window, and higher reliability for the operation of super-gate MOSFET devices.

FIG. 6 is a perspective view of at least a portion of a typical super-gate MOSFET device 600 shown in an alternative embodiment of the present invention. More specifically, the super-gate MOSFET device 600 is similar to the typical super-gate MOSFET device 400 shown in FIGS. 4A and 4B except that the MOSFET device 600 includes a simplified gate design that combines the planar gate (in FIG. 4B ). 416 ) and trench gate ( 418 in FIG. 4B ) are merged together to form a T-shaped gate 602 with planar gate and trench gate functions in the MOSFET device 600 . Specifically, the gate 602 includes a planar gate portion 604 and a trench gate portion 606 as a connecting structure.

A trench gate portion 606 is located between the two body regions 406 and extends at least partially vertically in the epitaxial region 404 . The trench gate portion 606 is not limited to any particular size in embodiments of the present invention, but the depth of the trench gate portion 606 is preferably about 1-2 micrometers (μm). Planar gate portion 604 begins at trench gate portion 606 and extends along the upper surfaces of epitaxial region 404 and body region 406 in two opposite lateral directions (ie, horizontal directions) to the edge of the corresponding source region 408 . An insulating layer 608 is formed under the gate 602 to electrically isolate the gate from adjacent structures and regions. Preferably, dielectric spacers 610 are disposed on the sidewalls of the gate electrode 602 to prevent electrical contact between the gate electrode and the source electrode 412 .

Plane and trench gate portions 604 and 606 preferably operate in the same manner as plane gate 416 and trench gate 418, respectively, in example MOSFET device 400 in Figure 4b. More specifically, by applying a gate bias signal greater than the threshold voltage of MOSFET device 600 between gate 602 and source region 408, each planar gate portion 604 will be induced in the corresponding body region 406 directly below the planar gate portion A channel is formed; when the applied gate bias signal is below the device threshold voltage, the channel is essentially closed. At the same time, the applied gate bias signal will cause trench gate portion 606 to form a strong accumulation layer 612 with a majority of carriers and with the contours of the trench gate portion near gate oxide 608 . As previously discussed, even though there is only a narrow space between the body regions 406, the strong accumulation layer 612 can increase the conductance of the MOSFET device 600, thereby reducing the on-resistance of the device. Connecting the gate 602 to the source electrode 412 closes the channel within the body region 406 , thereby turning off the MOSFET device 600 .

By way of example only, and not limitation, FIGS. 7A-7I illustrate schematic cross-sectional views of an exemplary fabrication process for at least a portion of the super-gate MOSFET device of one embodiment of the present invention in FIG. 4B . Referring to Figure 7A,

The exemplary fabrication process begins with a substrate 702, which in one or more embodiments includes single crystal silicon or other alternative semiconductor materials such as, but not limited to, germanium, silicon germanium, silicon carbide, Gallium Arsenide, Gallium Nitride, etc. In this illustrative embodiment, the substrate 702 is doped with N-type impurities or dopants (eg, phosphorus, etc.) to form an N-conductivity-type substrate (N+SUB). P-conductivity type substrates may also be considered in embodiments of the present invention. Substrate 702 is preferably cleaned and surface treated.

An epitaxial layer 704 is then formed on the upper surface of the substrate 702 by, for example, an epitaxial growth process. In one or more embodiments, the epitaxial layer has an N conductivity type (N-EPI), although a similar P conductivity type epitaxial layer is also contemplated. The doping concentration of epitaxial layer 704 is preferably lower than the doping concentration of substrate 702 .

As shown in FIG. 7B , a hard mask layer 706 is formed on the surface of the epitaxial layer 704 . In one or more embodiments, the hard mask layer 706, which may include silicon nitride, is preferably formed using standard deposition processes. The hard mask layer 706 is then patterned (eg, using standard photolithography and etching) and etched to form trenches 708 at least partially in the epitaxial layer 704 . In one or more embodiments, reactive ion etching (RIE) may be employed to form trenches 708 . Subsequently, as shown in FIG. 7C, a first dielectric layer 710 is formed on the inner walls (eg, sidewalls and bottoms) of the trench 708, which in one or more embodiments may be an oxide layer of . Although embodiments of the present invention are not limited to any particular dielectric material, in one or more embodiments, the first dielectric layer 710 includes silicon dioxide formed using a dry or wet oxidation process. This first dielectric layer 710 will form the gate oxide of the trench gate in the super-gate MOSFET device of this example (eg, 418 in Figure 4A).

Referring now to FIG. 7D, the hard mask layer (706 in FIG. 7C) is removed, for example, by using a wet or dry etching process such as chemical or plasma etching. A second dielectric layer 711 is then formed on the upper surface of the epitaxial layer 704. In one or more embodiments, the second dielectric layer 711 may be an oxide layer. This second dielectric layer 711 will form the gate oxide of the planar gate of the super gate MOSFET device (eg, 416 in Figure 4A). A chemical reaction between oxygen and silicon is typically driven by a high temperature environment (eg, about 800 degrees Celsius (°C) to 1200°C), producing silicon dioxide, forming the first and second dielectric layers 710, 711; however, even in At room temperature, a thin layer (eg, about 1-3 Angstroms (A)) of native oxide may also form in the surrounding environment. To grow thicker oxides in a controlled environment, several known methods can be used, for example, oxidation by in-situ steam generation or remote plasma sources (eg, remote plasma oxidation (RPO)).

Next, as shown in FIG. 7E, a gate structure including a planar gate 712 and a trench gate 714 is formed. The planar and trench gates 712, 714 preferably comprise polysilicon and are formed using standard deposition processes, followed by patterning (eg, using standard photolithography and etching) and etching. In this embodiment, two plane gates 712 are provided on both sides of the trench gate 714 . The trench gate 714 further includes laterally overgrown sidewalls formed on the upper surface of the second dielectric layer 711 to cover a portion of the upper surface of the epitaxial layer 704 . As shown in FIG. 7E , the planar gate 712 and the trench gate 714 are preferably formed in a comb-like (ie, strip-like) structure separated from each other in structure, and between the sidewalls of the trench gate 714 and the sidewalls of the adjacent planar gates 712 The spacing is k, and k is the minimum value of the process to ensure that the spacing k is as small as possible to avoid the increase of the on-resistance of the device. In this structure, the planar gate and the trench gate are electrically connected at one end or (opposite) ends of the strip. In one or more alternative embodiments, the planar gate 712 and the trench gate 714 may form a connected structure having planar gate and trench gate functions as described above in connection with FIG. 6 .

As shown in FIG. 7F, the exposed portion of the second dielectric layer (711 in FIG. 7E) on the upper surface of the epitaxial layer 704 (ie, not covered by the planar gate 712 and the trench gate) is removed using, for example, a standard selective etching process. The portion of the second dielectric layer covered by the lateral overgrown sidewalls of 714) is removed. A self-aligned body region 716 is then formed in the epitaxial layer 704 near the upper surface of the epitaxial layer. In the present exemplary embodiment, body region 716 is preferably formed by implanting a specified concentration level of P-type dopant into epitaxial layer 704, followed by thermal processing (eg, annealing) to drive the dopant into the epitaxial layer.

Alternatively, in the embodiment shown in FIG. 7F , implant region 718 is preferably formed in epitaxial layer 704 near the upper surface of the epitaxial layer and between body region 716 and trench gate 714 . In one or more embodiments, the implanted region 718 is formed by implanting an N-type dopant at a specified concentration level into the epitaxial layer 704 located between the planar gate 712 and the trench gate 714 . During implantation, the planar gate and trench gate act as masks. Preferably, the implanted region 718 is used to increase the N-type doping concentration level of the edge of the channel formed in the body region 716, thereby reducing the on-resistance of the MOSFET device. Implanted region 718 may also confine the channel area under gate 712, thereby improving high frequency performance. Although embodiments of the present invention are not limited to any particular doping concentration, in one or more embodiments, a preferred doping concentration for the implanted region 718 is about 1×10 ¹⁶ to 1×10 ¹⁸ atoms/ cubic centimeters.

As shown in FIG. 7G , then, dielectric spacers 720 are formed on the sidewalls of the planar gate 712 and the trench gate 714 . Although the present invention is not limited to any particular dielectric material, in one or more embodiments, the dielectric spacers 720 may include silicon dioxide or silicon nitride. An etching process is then used to create the desired patterning to form source contacts (eg, N-type) and body region pickup contacts (eg, P-type) in the device.

In FIG. 7H , source regions 722 are formed in corresponding body regions 716 proximate the upper surface of the body regions and self-aligned planar gates 712 . In the present exemplary embodiment, the source region 722 having an N conductivity type is formed using, for example, a standard implantation process (eg, ion implantation). In this embodiment, a heavily doped region 724 of P conductivity type is formed near the upper surface of the body region 716 and laterally adjacent to the corresponding source region 722 to form a body region contact of the super-gate MOSFET device. point. Thus, each source region 722 is electrically connected to a corresponding body region contact 724 .

Referring now to FIG. 7I, using a standard front-end silicidation process, metal silicide contacts 726 are formed on the source region 722, respectively, and metal silicide contacts 728 and 730 are formed on the planar and trench gates, respectively. As is well known, during silicidation, a layer of metal is deposited on the upper surface of the wafer and then thermally treated (eg, thermal annealing) to form an alloy (metal silicide) where the metal contacts the exposed silicon. The unreacted metal is then removed using, for example, standard etching processes, forming a low resistance suicide at the source and gate contacts. Front-side interconnection and passivation are then performed with metals (eg, aluminum, etc.), and dielectric deposition and patterning are performed in a front-end-of-line (FEOL) process. After the FEOL process, the wafer is flipped for backside thinning (eg, using chemical mechanical polishing, CMP) and backside metallization to form the drain contact 732 of the Supergate MOSFET device.

8 is a cross-sectional view of at least a portion of a super-gate MOSFET device 800 in one embodiment of the present invention. The MOSFET device 800 is similar to the super-gate MOSFET device 400 shown in Figure 4B, except that its gate structure is configured for enhanced voltage blocking capability. As shown in FIG. 8, a super-gate MOSFET device 800 includes a substrate 802, which can be prepared by adding impurities or dopants (eg, boron, phosphorous, etc.) of desired conductivity type (N-type or P-type) and doping level , arsenic, antimony, etc.) and modified single crystal silicon formed. In the present exemplary embodiment, the substrate 802 is doped to have an N conductivity type, and thus may be referred to as an N-type substrate (N+SUB). Other materials are also contemplated to form substrate 802, such as, but not limited to, germanium, gallium arsenide, silicon carbide, gallium nitride, indium phosphide, and the like.

An epitaxial region 804 is formed on the upper surface of the substrate 802 . In this example, the epitaxial region 804 is formed by adding impurities or dopant denaturation with N conductivity type (N-NPI). Of course, P-type epitaxy can also be considered. In the MOSFET device 800, the epitaxial region 804 acts as a lightly doped drift region of the device. In this embodiment, two body regions (P-BODY) 806 having a P-type conductivity type are formed near the upper surface of the epitaxial region 804 and are laterally spaced apart from each other. The body region 806 in this embodiment may be formed by implanting a P-type impurity (eg, boron) into designated areas of the epitaxial region 804 using standard complementary metal oxide semiconductor (CMOS) fabrication techniques.

A source region 808 is formed in at least a portion of the corresponding body region 806 near the upper surface of the body region. Preferably, in the exemplary MESFET device 800, the source region 808 has an N-type conductivity type. In this embodiment, a heavily doped region 810 formed near the upper surface of the body region 806 and laterally adjacent to the corresponding source region 808 has a P-type conductivity, thereby forming the body region contact of the MOSFET device 800 . A corresponding source (S) electrode 812 electrically connects each source region 808 to a corresponding body region contact 810 .

In this super gate MOSFET device 800, the substrate 802 serves as the drain region of the device. Accordingly, for example in a back-end-of-line (BEOL) process, the drain (D) electrode 814 is preferably formed on the backside of the substrate/drain 802, which is provided between the substrate/drain electrical connection. Similar to the MOSFET device 400 shown in FIG. 4B, the drain electrode 814 is formed on the backside of the MOSFET device 800, on the side opposite the source electrode 812 formed on the upper/front surface of the device, that is, the drain The pole electrode 814 and the source electrode 812 are distributed on two vertically opposite surfaces of the MOSFET device 800 .

The MOSFET device 800 also includes a gate structure that includes at least two parts, a planar gate (G1) 816 and a trench gate (G2) 818. In the illustration of this embodiment, two planar gates 816 are respectively disposed on two sides of the trench gate 818 . The trench gate 818 also includes forming laterally overgrown sidewalls over the upper surface of the epitaxial region 804 to cover a portion of the upper surface of the epitaxial region 804 . The planar gate 816 and the trench gate 818 are preferably formed into a comb-like (striped) structure that is structurally separated from each other, and the distance between the sidewall of the trench gate 818 and the sidewall of the adjacent planar gate 816 is k, where k is the minimum process value, the planar gate and the trench gate are electrically connected at one or both ends of their strip structures (not explicitly shown in the figure, but implied). In one or more alternative embodiments, planar gate 816 and trench gate 818 may form a connected gate structure with planar and trench gate functionality.

In one or more embodiments, trench gate 818 , which may include polysilicon, may generally be formed vertically through the upper surface of epitaxial region 804 located between body regions 806 and also between source regions 808 such that the trench gate 818 is located in the trenches. Gate 818 has a source region 808 on both sides. The MOSFET device 800 also includes a dielectric layer 820 that electrically isolates the trench gate 818 from the surrounding epitaxial region 804 , thereby preventing direct electrical contact between the trench gate 818 and adjacent source regions 808 and body regions 806 . In one or more embodiments, the dielectric layer 820 includes an oxide, such as silicon dioxide, which may be referred to as a trench gate oxide, although the invention is not limited to any particular electrically insulating material.

In one or more embodiments, each planar gate 816 is disposed on the upper surface of the epitaxial region 804 , at least a portion of which overlaps the corresponding body region 806 . A second dielectric layer 822 is formed between each planar gate 816 and the upper surface of the body region 806 and epitaxial region 804 to electrically isolate the planar gate 816 from the body region and epitaxial region, and thus may be referred to as a planar gate oxide layer. Dielectric spacers 824 are preferably formed on the sidewalls of the planar gate 816 and the sidewalls of the trench gate 818 . Gate spacers 824 electrically isolate the planar gate from the trench gate and electrically isolate the planar gate 816 from the corresponding source electrode 812 .

With continued reference to FIG. 8 , the super gate MOSFET device 800 also includes a first gate electrode 826 connected to the planar gate 816 and a second gate electrode 828 connected to the trench gate 818 . Gate electrodes 426 and 428 may be implemented by forming a metal silicide layer on at least a portion of the upper surfaces of gate electrodes 816 and 818, respectively.

In order to optimize the voltage blocking capability of the super gate MOSFET device 800, the trench gate structure is preferably configured with a trench gate oxide layer 820, and the portion of the trench gate oxide layer 820 located in the lower part 830 of the trench gate structure is more than the trench gate structure. The portion of the upper portion 832 of the gate structure is thicker. Although embodiments of the present invention are not limited to any particular size, in one or more embodiments, the trench gate oxide 820 at the upper portion 832 of the trench gate structure has a thickness of about 10-50 nm, while the thickness of the trench gate oxide 820 at the upper portion 832 of the trench gate structure The thickness of the trench gate oxide layer at the lower part 830 of the trench gate structure is about 50-500 nm. The planar gate oxide layer 822 under each planar gate (G1) 816 is preferably around 5-50 nm. A method of configuring a super-gate MOSFET device having a trench gate structure is illustratively described below with reference to FIGS. 9A to 9L.

Specifically, FIGS. 9A to 9L are schematic cross-sectional views of a manufacturing process of at least a portion of the super-gate MOSFET device 800 in the embodiment shown in FIG. 8 of the present invention shown in FIG. 8 . Referring to FIG. 9A, the exemplary fabrication process begins with a substrate 902, which in one or more embodiments includes monocrystalline silicon or other alternative semiconductor materials such as, but not limited to, germanium, Silicon germanium, silicon carbide, gallium arsenide, gallium nitride, etc. In this illustrative embodiment, the substrate 902 is doped with N-type impurities or dopants (eg, phosphorus, etc.) to form an N-conductivity-type substrate (N+SUB). P-conductivity type substrates may also be considered in embodiments of the present invention. Substrate 902 is preferably cleaned and surface treated.

An epitaxial layer 904 is then formed on the upper surface of the substrate 902 by, for example, an epitaxial growth process. In one or more embodiments, the epitaxial layer has an N conductivity type (N-EPI), although a similar P conductivity type epitaxial layer is also contemplated. The doping concentration of epitaxial layer 904 is preferably lower than the doping concentration of substrate 902 .

As shown in FIG. 9B , a hard mask layer 906 is formed on the surface of the epitaxial layer 904 . In one or more embodiments, the hard mask layer 906, which may include silicon nitride, is formed, preferably using standard deposition processes. The hard mask layer 906 is then patterned using, for example, standard photolithography and etching, and trenches 908 are formed at least partially in the epitaxial layer 904 using, for example, an etching process; in one or more embodiments, using Reactive ion etching (RIE) forms trenches 908 . Subsequently, as shown in FIG. 9c, the hard mask layer 906 is removed using a method such as etching.

The first two steps in the fabrication of this super-gate MOSFET device 800 are identical to the fabrication of the exemplary super-gate MOSFET device 400 shown in Figure 4B, depicted in Figures 7A and 7B. Referring now to FIG. 9D , an insulating layer 910 is formed in trench 908 and over at least a portion of the upper surface of epitaxial layer 904 . In one or more embodiments, insulating layer 910 includes an oxide (eg, silicon dioxide) grown or deposited in trench 908 and on the upper surface of epitaxial layer 904 . Then, as shown in FIG. 9E, an etch-back process, such as wet etching, is used to remove the insulating layer 910 on the upper surface of the epitaxial layer 904 and the insulating layer 910 on part of the sidewalls in the trench 908, allowing part of the insulating layer 910 to remain on At the bottom of the trench, as shown in FIG. 9F , the wafer is thermally oxidized to form a thinner conformal gate oxide layer 912 . Although embodiments of the present invention are not limited to any particular size, in one or more embodiments, the thickness of oxide layer 912 on the upper surface of epitaxial layer 904 and on the sidewalls of trench 908 is approximately 30-50 nm.

As shown in FIG. 9G, in one or more embodiments, a narrow trench 914 is formed in insulating layer 910 using anisotropic etching (eg, RIE). Then, as shown in FIG. 9H , a thin gate oxide layer 916 (eg, about 30-50 nm) is grown on the upper portion of the sidewalls of the first trench 908 and the upper surface of the epitaxial layer 904 . Next, as shown in FIG. 9I, a gate structure including planar gate 918 and trench gate 920 is formed. Each of the planar and trench gates 918, 920 preferably comprises polysilicon and is formed using standard deposition processes, followed by patterning (eg, using standard photolithography and etching) and etching. In this embodiment, two plane gates 918 are provided on both sides of the trench gate 920 . Trench gate 920 also includes forming laterally overgrown sidewalls over the upper surface of gate oxide 916 to cover portions of the upper surface of epitaxial layer 904 . As shown in FIG. 9I , the planar gate 918 and the trench gate 920 are preferably formed in a comb-like (ie, strip-like) structure that is structurally separated from each other, and between the sidewalls of the trench gate 920 and the sidewalls of the adjacent planar gates 918 The spacing is k, and k is the minimum value of the process. In this structure, the planar gate and the trench gate are electrically connected at one end or (opposite) ends of the strip.

Referring now to FIG. 9J , the exposed portion of the gate oxide layer ( 916 in FIG. 9I ) on the upper surface of the epitaxial layer 904 (ie, not covered by the lateral surfaces of the planar gate 918 and the trench gate 920 ) is removed using, for example, a selective etching process. Part of the gate oxide covered by the overgrown sidewalls) is removed. Self-aligned body regions 922 are then formed in epitaxial layer 904 near the upper surface of the epitaxial layer. In the present exemplary embodiment, body region 922 is preferably formed by implanting a specified concentration level of P-type dopant into epitaxial layer 904, followed by thermal processing (eg, annealing) to drive the dopant into the epitaxial layer.

Optionally, in the embodiment shown in FIG. 9J , the implanted region 924 is preferably formed in the epitaxial layer 904 near the upper surface of the epitaxial layer and between the body region 922 and the trench gate 920 . In one or more embodiments, the implanted region 924 is formed by implanting an N-type dopant at a specified concentration level into the epitaxial layer 904 located between the planar gate 918 and the trench gate 920 . During implantation, the planar gate and trench gate act as masks. Like the implanted region 718 shown in FIG. 7F, the implanted region 924 is preferably used to increase the N-type doping concentration level at the edge of the channel formed in the body region 922, thereby reducing the MOSFET device's On resistance. Implanted region 924 may also limit the channel area under gate 918, thereby improving high frequency performance. Although embodiments of the present invention are not limited to any particular doping concentration, in one or more embodiments, a preferred doping concentration for the implanted region 924 is about 1×10 ¹⁶ to 1×10 ¹⁸ atoms/ cubic centimeters.

As shown in FIG. 9K , dielectric spacers 926 are then formed on the sidewalls of the planar gate 918 and the trench gate 920 . Although the present invention is not limited to any particular dielectric material, in one or more embodiments, the dielectric spacers 926 may include silicon dioxide. An etching process is then used to create the desired patterning to form source region contacts (eg, N-type) and body region contacts (eg, P-type) in the device.

In FIG. 9L , source regions 928 are formed in corresponding body regions 922 proximate the upper surface of the body regions and self-aligned planar gates 918 . In the present exemplary embodiment, the source region 928 having N conductivity type is formed using, for example, a standard implantation process (eg, ion implantation). In this embodiment, a heavily doped region 930 of P conductivity type is formed close to the upper surface of the body region 922 and laterally adjacent to the corresponding source region 928 to form a body region contact of the super-gate MOSFET device. point. Thus, each source region 928 is electrically connected to a corresponding body region contact 930 .

Using standard front-end silicidation processes, metal silicide contacts (812) are formed on source region 928, respectively, and metal silicide contacts (826 and 828) are formed on planar gate 918 and trench gate 920, respectively. Front-side interconnection and passivation are then performed with metals (eg, aluminum, etc.), and dielectric deposition and patterning are performed in a front-end-of-line (FEOL) process. After the FEOL process, the wafer is flipped for backside thinning (eg, CMP) and backside metallization to form drain contacts (814), thereby forming the super gate MOSFET device 800 shown in FIG.

10 is a cross-sectional view of at least a portion of a super-gate MOSFET device with enhanced source contacts in another embodiment of the present invention. The MOSFET device 1000 is identical to the super-gate MOSFET device 400 shown in Figure 4B, with the difference being the source contact. Specifically, as shown in FIG. 10, the super-gate MOSFET device 1000 includes an embedded source contact 1202 formed in a corresponding body region 406, the source contact 1202 being proximate to the upper surface of the body region and connected to the body region 406. Adjacent source regions 408 are electrically connected. In one or more embodiments, each embedded source contact 1202 includes a metal, such as tungsten, although embodiments of the invention are not limited to tungsten. This source contact structure provides a larger contact area between the source metal and the source region 408, and thus is beneficial for reducing the resistance of the source contact. Desirably, such a source contact structure can be used with any of the super-gate MOSFET device structures described herein, as will be apparent to those skilled in the art based on this revelation. Although not explicitly shown in FIG. 10, metal silicide may also be formed around the embedded source contact 1202 using the same metal silicide process used for the formation of the planar gate and trench gate contacts 426 and 428, for This solution will also be apparent to those skilled in the art based on this revelation.

The MOSFET devices of various embodiments of the present invention achieve superior performance compared to standard MOSFET device designs. For example, Figure 11 is a graphical representation of the drain voltage as a function of time for a super gate MOSFET device (reference numeral 1102), such as the super gate MOSFET device 400 shown in Figure 4B, compared to a standard MOSFET device (reference numeral 1104). As can be seen in Figure 11, the drain voltage of the new super-gate MOSFET device rises over time (ie, dv/dt) much faster than the standard MOSFET device. This demonstrates that the switching speed of the new super-gate MOSFET device is an improvement.

12 is a schematic diagram of gate voltage as a function of time for a super gate MOSFET device (reference numeral 1202), such as the super gate MOSFET device 400 shown in FIG. 4B, as compared to a standard MOSFET device (reference numeral 1204). As can be seen in Figure 12, the gate voltage of a standard MOSFET device exhibits severe disturbance 1206 when the device is turned off. This perturbation is mainly due to the drain voltage coupling effect of the large parasitic Miller capacitance (C _gd ) associated with standard MOSFET devices (as discussed earlier), which can exceed the device's threshold voltage, causing the device misleading. Misturning of such devices can lead to short-circuit conditions, especially when MOSFET devices are used as low-side transistors in power switching applications such as DC-DC converters. By comparison, it can be found that the super-gate MOSFET device represented by the reference numeral 1202 exhibits very little gate voltage disturbance, which is much lower than the threshold voltage of the device, thus eliminating the problem of false turn-on of the device. Therefore, the super-gate MOSFET devices of various embodiments of the present invention have higher efficiency and higher reliability in higher frequency DC-DC converter applications than conventional MOSFET devices.

At least some of the techniques of this disclosure may be implemented in integrated circuits. In the formation of integrated circuits, the same molds are typically fabricated in an iteratively patterned manner on the surface of a semiconductor wafer. Each mold includes the devices described herein, and may also include other structures and/or circuits. Individual dies are cut from the wafer and packaged into integrated circuits. Those skilled in the art will know how to cut and package molds from wafers to form integrated circuits. Any exemplary structure or circuit shown in the figures, or a portion thereof, may be part of an integrated circuit. Such integrated circuit fabrication methods are also considered to be part of the present invention.

It will be understood by those skilled in the art that the above-described exemplary structures in one or more embodiments of the present invention may be used in raw form (ie, a single wafer with multiple unpackaged chips), bare chips, or in packaged form, or Used as part of intermediate or end products in devices with power MOSFETs, such as radio frequency (RF) power amplifiers, power management integrated circuits, etc.

Essentially any high frequency, high power application and/or electronic system, such as, but not limited to, radio frequency power amplifiers, power management integrated circuits, etc., can use integrated circuits consistent with the present disclosure. Systems suitable for implementing embodiments of the present invention may include, but are not limited to, DC-DC converters. Systems incorporating such integrated circuits are considered part of the present invention. Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to consider other implementations and applications of embodiments of the present invention.

A complete description of all elements and features of the devices and systems of the circuits and techniques of the present invention. Based on the teachings herein, many other embodiments will become apparent to those skilled in the art, or derived therefrom, so that structural and logical modifications can be made without departing from the scope of the present disclosure. Replace and change. The drawings are also representative only and not drawn to scale. Accordingly, both the specification and the drawings are to be regarded in an illustrative rather than a restrictive sense.

The various embodiments of the invention recited herein, individually and/or collectively, refer to the word "embodiment", which is for convenience only and is not intended to limit the scope of application of the invention to any single or Several embodiments or inventive concepts. Thus, although specific embodiments have been illustrated and described herein, it should be understood that arrangements that achieve the same purpose of the invention may be substituted for the specific embodiments shown; that is, this disclosure is intended to cover various embodiments of any and all adaptations or changes. Combinations of the above-described embodiments, as well as other embodiments not specifically described herein, will also be apparent to those skilled in the art.

The terminology used herein is used to describe specific embodiments only, and not to limit the invention. The singular form of an article as used herein may also include the plural form unless the context clearly indicates otherwise. Further, when "comprising" and/or "comprising" are used in this specification, only the presence of the stated features, steps, operations, elements and/or components does not preclude the presence or addition of one or more other Features, steps, operations, elements, components and/or components thereof. Rather, terms such as "above", "below", "above" and "below" are used to denote relative positional relationships between elements or structures, rather than absolute positions.

Based on the teachings of the embodiments of the present invention, those of ordinary skill in the art can relate to other implementations and applications of the technologies of the embodiments of the present invention. Although illustrative embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that the embodiments of the invention are not limited to these precise embodiments, without departing from the scope of the claims. Various other modifications may be made to the embodiments herein by those skilled in the art.

Claims (23)

1. a metal oxide semiconductor field effect transistor device, is characterized in that, comprises: a semiconductor substrate having a first conductivity type; an epitaxial region, having a first conductivity type, and disposed on the upper surface of the substrate; at least two body regions, having a second conductivity type, are formed in the epitaxial region, the second conductivity type is opposite to the first conductivity type, the body regions are located near the upper surface of the epitaxial region, and the The two body regions are laterally spaced from each other; at least two source regions with a first conductivity type, each of the source regions is disposed in a position close to the upper surface of the body region in the corresponding body region; A gate structure, comprising: at least two planar gates, each of the planar gates is located on the upper surface of the epitaxial region and overlaps with at least a part of the corresponding body region; further comprising two of the body regions a trench gate between and at least partially within the epitaxial region, the trench gate forming laterally overgrown sidewalls over the upper surface of the epitaxial region to partially cover the upper surface of the epitaxial region; and The drain contact is disposed on the backside of the substrate and is electrically connected to the substrate. 2 . The device of claim 1 , wherein the at least two planar gates and the trench gate form a T-shaped junction gate with functions of the planar gate and the trench gate. 3 . 3. The device of claim 1, further comprising: a first dielectric layer disposed between the trench gate and the adjacent epitaxial region; and The second dielectric layer is arranged between the at least two planar gates and the corresponding lower partial body regions and the epitaxial region, and is also arranged between the laterally overgrown sidewalls of the trench gate and the corresponding lower between the epitaxial regions. 4 . The device of claim 3 , wherein the first dielectric layer has a non-uniform thickness and is located at all positions of the trench gate bottom wall and the upwardly extending part of the spacer. 5 . The first portion of the first dielectric layer has a first thickness, and the spacer of the trench gate extends upward until the upper surface of the second portion of the first dielectric layer has a second thickness, the first thickness is greater than the predetermined thickness. The second thickness is thicker. 5 . The device according to claim 1 , wherein the two planar gates and the trench gates have comb-like structures that are structurally separated from each other, and the sidewalls of the trench gates and the phase There is a distance k between the sidewalls of the adjacent planar gates, and one or both ends of the comb-like structure are electrically connected together. 6 . The device of claim 1 , further comprising dielectric spacers formed on sidewalls of at least two planar gates in the gate structure and formed on top of the epitaxial layer. 7 . A portion of the sidewall of the trench gate on the surface. 7. The device according to claim 1, further comprising at least two doped regions with the second conductivity type, formed near the upper surface of the body region and laterally adjacent to the corresponding source regions, to form the source contact of the device. 8 . The device of claim 1 , further comprising a plurality of implanted regions having the first conductivity type, each of the implanted regions is formed close to the upper surface of the epitaxial layer and located in a corresponding between the body region and the trench gate. 9. The device of claim 8, wherein a vertical edge of each of the implanted regions is self-aligned with the planar gate and trench gate of the gate structure. 10 . The device of claim 8 , wherein the doping concentration of each of the implanted regions is 1×10 ¹⁶ atoms/cm 3 to 1×10 ¹⁸ atoms/cm 3 . 11 . 11. The device according to claim 1, further comprising a plurality of gate electrodes, which are respectively electrically connected to the planar gate and the trench gate in the gate structure, and each gate electrode is A metal silicide layer is formed on at least a portion of the upper surfaces of the corresponding planar gate and trench gate, respectively. 12. The device of claim 1, further comprising at least two embedded source contacts, each of the embedded source contacts formed in a corresponding body region adjacent to the body the upper surface of the region and is electrically connected to the adjacent source region. 13. The device of claim 1 , wherein the doping concentration of the body region is 5×10 ¹⁶ atoms/cm 3 to 1×10 ¹⁸ atoms/cm 3 . 14. The device of claim 1, wherein when a positive bias voltage exceeding a threshold voltage of an N-channel MOSFET device is applied to the gate structure, formed in the body region under the planar gate channel, thereby turning on the device, and at the same time, a strong accumulation layer with majority carriers is formed in the epitaxial region near the surface of the trench gate. 15. The device of claim 14, wherein the majority carrier concentration is dependent on a bias voltage applied to the trench gate structure. 16. A method for manufacturing a metal-oxide-semiconductor field-effect transistor device, characterized in that the method comprises: forming an epitaxial region having the first conductivity type on the upper surface of the substrate having the first conductivity type; At least two body regions having a second conductivity type opposite to the first conductivity type are formed in the epitaxial region, the body regions are located close to the upper surface of the epitaxial region, and the second conductivity type is opposite to the first conductivity type The two body regions are laterally spaced from each other; forming at least two source regions having the first conductivity type, each of the source regions being disposed in the corresponding body region near the upper surface of the body region; forming a gate structure including at least two planar gates and one trench gate, each of the planar gates is located on the upper surface of the epitaxial region and overlaps with at least a portion of the corresponding body region; the trenches A trench gate is located between two of the body regions and at least partially within the epitaxial region, and the trench gate forms laterally overgrown sidewalls over the upper surface of the epitaxial region to partially cover the epitaxial region the upper surface of the area; and A drain contact electrically connected to the substrate is formed on the backside of the substrate. 17. The method of claim 16, further comprising: the at least two planar gates and the trench gate form a T-shaped junction gate having functions of the planar gate and the trench gate. 18. The method of claim 16, further comprising: forming a first dielectric layer between the trench gate and the adjacent epitaxial region; and forming a second dielectric layer between the at least two planar gates and the corresponding underlying partial body regions and the epitaxial region, and also between the laterally overgrown sidewalls of the trench gate and the corresponding underlying epitaxy between regions. 19 . The method of claim 18 , further comprising: forming the first dielectric layer with a non-uniform thickness at positions of the trench gate bottom wall and the upwardly extending portion of the spacer. 20 . The first portion of the first dielectric layer has a first thickness, the sidewall spacers of the trench gate extend up to the upper surface and the second portion of the first dielectric layer has a second thickness, the first thickness thicker than the second thickness. 20. The method of claim 16, further comprising: The formed two planar gates and the trench gates have comb-like structures that are structurally separated from each other, so that the distance k between the sidewalls of the trench gates and the sidewalls of the adjacent planar gates has a process minimum value; One or both ends of the comb-like structure are electrically connected together. 21 . The method of claim 16 , further comprising: forming dielectric spacers on sidewalls of at least two planar gates in the gate structure and forming dielectric spacers on the sidewalls extending from the epitaxial layer. 22 . A portion of the sidewall of the trench gate on the upper surface. 22. The method of claim 16, further comprising: adjusting the concentration of the majority carriers in the device by adjusting the bias voltage applied to the gate structure. 23. The method of claim 16, further comprising: when a forward bias voltage exceeding a threshold voltage of an N-channel MOSFET device is applied to the gate structure, the bulk under the planar gate A channel is formed in the region to turn on the device, and at the same time, a strong accumulation layer with majority carriers is formed in the epitaxial region near the surface of the trench gate.

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