CN114337226A

CN114337226A - Protection circuit, power protection chip and equipment of power tube

Info

Publication number: CN114337226A
Application number: CN202111679057.5A
Authority: CN
Inventors: 姜艳
Original assignee: Shanghai Aiwei Microelectronics Technology Co ltd
Current assignee: Shanghai Aiwei Microelectronics Technology Co ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-04-12
Anticipated expiration: 2041-12-31
Also published as: CN114337226B

Abstract

The application provides a protection circuit of power tube, this circuit is including the bias branch road of connection on the grid of power tube and the clamp branch road of connection between the source electrode and the drain electrode of power tube, the source electrode connection input of power tube, the drain electrode connection output of power tube, the bias branch road is used for providing bias current, the output current of power tube is subject to bias current, the clamp branch road is used for when the source drain voltage of power tube is greater than source drain clamp voltage threshold value, reduce bias current, and then reduce the output current of power tube, make the power tube get into current-limiting protection mode control power. Therefore, the power of the power tube can be limited by combining current limiting and clamping, and the safety of the power tube is fundamentally protected.

Description

Protection circuit, power protection chip and equipment of power tube

Technical Field

The application relates to the technical field of circuits, in particular to a protection circuit of a power tube, a power protection chip and electronic equipment.

Background

In the power protection chip, many power switch tubes are integrated. Among them, the power switching tube is also called a power tube, and the power tube is a transistor serving as a final-stage output in the amplifier circuit. The power transistor may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), also referred to as MOS.

The power tube can be divided into an N-type power tube and a P-type power tube. The P-type power tube is usually connected to a power port, and when the power tube is turned on, the power tube can supply power to a load, and when the power tube is turned off, the power tube does not supply power to the load. Normally, the P-type power tube works in a linear region, at the moment, the gate-source voltage (Vgs) is large, the on-resistance is small, the drain-source voltage (Vds) of the P-type power tube is small, and the drain-terminal voltage is close to the source-terminal voltage. If the source-drain power supply of the P-type power tube is increased due to misoperation, the P-type power tube generates large power instantly, and in some cases, the P-type power tube can even be burnt out.

Currently, the industry adopts an overcurrent protection scheme to protect a P-type power tube. Specifically, the P-type power tube is turned off when the current flowing through the P-type power tube exceeds an overcurrent protection threshold. However, the output voltage is not limited by this scheme, the drain-source voltage may still be large, and there is a high power risk in high-current applications, which may cause the P-type power transistor to be burned out.

Disclosure of Invention

The application provides a protection circuit of power tube, this circuit including connect the bias branch road on the grid of power tube and connect the clamp branch road between power tube source electrode and drain electrode, can combine current-limiting and clamp, the power of restriction power tube avoids power tube too big burning out of power tube power. The application also provides a power protection chip and electronic equipment corresponding to the protection circuit.

In a first aspect, the present application provides a protection circuit for a power transistor. The circuit comprises a bias branch connected to a grid electrode of the power tube and a clamping branch connected between a source electrode and a drain electrode of the power tube, wherein the source electrode of the power tube is connected with an input end, and the drain electrode of the power tube is connected with an output end;

the bias branch circuit is used for providing a bias current, wherein the output current of the power tube is limited by the bias current;

and the clamping branch is used for reducing the bias current when the source-drain voltage of the power tube is greater than a source-drain clamping voltage threshold value, so as to reduce the output current of the power tube, and the power tube enters a current-limiting protection mode.

In some possible implementations, the product of the output current of the power tube when entering the current-limiting protection mode and the maximum voltage of the input end is smaller than the rated power of the power tube.

In some possible implementation manners, the clamping branch includes a first P-type metal oxide semiconductor field effect transistor PMOS, a second PMOS, at least one third PMOS, and switches corresponding to the third PMOS one to one, where the third PMOS is used to adjust a source-drain clamping voltage threshold of the power transistor;

the source electrode of the first PMOS and the source electrode of the second PMOS are connected with the input end, the grid electrode of the first PMOS and the grid electrode of the second PMOS are connected with the drain electrode of the first PMOS, the drain electrode of the first PMOS is connected with the source electrode of one third PMOS in the at least one third PMOS, the grid electrode and the drain electrode of one third PMOS in the at least one third PMOS are connected with the source electrode of the next third PMOS, and the grid electrode and the drain electrode of the last third PMOS in the at least one third PMOS are connected with the output end.

In some possible implementations, the clamping branch further includes an inverter and a first NMOS, the second PMOS is connected to the gate of the first NMOS through the inverter, and the drain of the first NMOS is connected to the biasing branch.

In some possible implementation manners, when the source-drain voltage of the power tube is greater than the source-drain clamp voltage threshold, the first PMOS is turned on, the second PMOS is used for mirroring the current of the first PMOS to obtain the current of the second PMOS, and the phase inverter is used for outputting a low level when the current of the second PMOS is greater than a preset constant current, so that the first NMOS is turned off, the resistance of the bias branch is increased, the bias current is decreased, and the current of the power tube is decreased along with the decrease of the bias current.

In some possible implementation manners, the circuit further includes an inverter and a fourth PMOS, an input end of the inverter is connected to a drain of the second PMOS, an output end of the inverter is connected to a gate of the fourth PMOS, a source of the fourth PMOS is connected to the input end, and a drain of the fourth PMOS is connected to the gate of the power transistor.

In some possible implementations, the bias branch includes a plurality of bias resistors, at least one of the plurality of bias resistors is connected in parallel with a switch, and the switch connected in parallel with the bias resistor is used to adjust the resistance of the bias branch.

In some possible implementations, the bias branch further includes a basic PMOS, a gate of the basic PMOS is connected to the gate of the power transistor, a source of the basic PMOS is connected to the input terminal, and a drain of the basic PMOS is connected to the bias resistor.

In some possible implementations, the bias branch further includes an operational amplifier, a first input terminal of the operational amplifier is connected to a reference voltage, and a second input terminal of the operational amplifier is connected to the drain of the basic PMOS.

In a second aspect, the present application provides a power protection chip, where the power protection chip includes the protection circuit of the power transistor in the first aspect or any implementation manner of the first aspect.

In a third aspect, the present application provides an electronic device, which includes a power supply and a power protection chip as in the second aspect or any implementation manner of the second aspect.

The present application can further combine to provide more implementations on the basis of the implementations provided by the above aspects.

According to the technical scheme, the embodiment of the application has the following advantages:

the embodiment of the application provides a protection circuit of a power tube, the protection circuit comprises a bias branch connected to a grid electrode of the power tube and a clamping branch connected between a source electrode and a drain electrode of the power tube, the source electrode of the power tube is connected with an input end, the drain electrode of the power tube is connected with an output end, the bias branch is used for providing bias current, the output current of the power tube is limited by the bias current, the clamping branch is used for reducing the bias current when the source-drain voltage of the power tube is greater than the source-drain clamping voltage threshold value, and then the output current of the power tube is reduced, and the power tube enters a current-limiting protection mode to control power. Therefore, the power of the power tube can be limited by combining current limiting and clamping, and the safety of the power tube is fundamentally protected.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a power tube power supply provided in an embodiment of the present application;

fig. 2 is a schematic diagram of a current limiting circuit for power tube protection according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a power tube protection circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a relationship between a source-drain voltage difference and an output current of a power tube protection circuit provided in an embodiment of the present application;

fig. 5 is a schematic diagram of a power tube protection circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a power protection chip according to an embodiment of the present application.

Detailed Description

The scheme in the embodiments provided in the present application will be described below with reference to the drawings in the present application.

The terms "first" and "second" in the embodiments of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

Some technical terms referred to in the embodiments of the present application will be first described.

A P-type power transistor (PMOS) is usually connected to a power port, and when the PMOS power transistor is turned on, the PMOS power transistor can supply power to a load, and when the PMOS power transistor is turned off, the PMOS power transistor does not supply power to the load, as shown in fig. 1.

Under the normal state that the power tube is conducted, the P-type power tube works in a linear region, at the moment, the grid-source voltage is large, the conducting impedance is small, the drain-source voltage of the P-type power tube is small, the drain-end voltage is close to the source-end voltage, however, when a load is short-circuited or the load is excessively heavy, the PMOS can enter a saturation region, the current and the voltage on the power tube are both large, and the risk that the PMOS is burnt out due to the excessively large power exists.

Typically, current limiting protection is commonly used for PMOS protection, as shown in fig. 2. Wherein, the current limiting Resistor (RLIM) can configure the magnitude of the current limiting.

The comparator enables a comparison between two data items, outputting a positive level when the voltage input at the positive input terminal of the comparator is greater than the voltage at the negative input terminal, and outputting a low level otherwise.

Specifically, the comparator compares the voltage drop generated by the mirror current (ISENSE) on the RLIM with a reference Voltage (VREF), when the voltage drop generated on the RLIM is greater than VREF, a high level is output, the power tube is turned off, when the voltage drop generated on the RLIM is less than VREF, a low level is output, and the power tube is turned on to work normally. Since the current of ISENSE becomes larger as the IOUT current becomes larger, the rail-to-rail operational amplifier output high turns off the PMOS when the voltage drop generated on RLIM is greater than VREF.

However, this solution can limit power by limiting current, but does not limit output voltage, so the voltage difference between the source and the drain of the power transistor may still be large, and there is still a risk that the PMOS is burned out due to excessive power at a large current.

In view of the above, the present application provides a power protection circuit, which includes a bias branch connected to a gate of a power transistor, and a clamp branch connected between a source and the gate of the power transistor, where the source of the power transistor is connected to an input terminal, and the drain of the power transistor is connected to an output terminal. The bias branch circuit is used for providing bias current, the output current of the power tube is limited by the bias current, and the clamping branch circuit is used for reducing the bias current when the voltage difference of a source electrode and a drain electrode of the power tube is larger than a source electrode and drain electrode clamping voltage threshold value, so that the output current of the power tube is reduced, and the power tube enters a current-limiting protection mode. Therefore, the current-limiting protection can be performed on the power tube, the voltage difference between the source electrode and the drain electrode of the power tube can be limited, the power on the power tube can be limited, and the safety of the power tube is comprehensively protected.

For the convenience of understanding, the protection circuit of the power tube provided by the embodiment of the present application is described below with reference to the accompanying drawings.

Referring to fig. 3, a schematic diagram of a protection circuit of a power transistor includes the power transistor and a bias branch connected to a gate of the power transistor and a clamp branch connected between a source and a drain of the power transistor.

The power tube comprises a power tube, a clamping branch circuit, a source electrode, a drain electrode and an output end, wherein the source electrode of the power tube is connected with the input end, the drain electrode of the power tube is connected with the output end, the biasing branch circuit is used for providing a biasing current, the output current of the power tube is limited by the biasing current, and the clamping branch circuit is used for reducing the biasing current when the source-drain voltage of the power tube is larger than the source-drain clamping voltage threshold value, so that the output current of the power tube is reduced, and the power tube enters a current-limiting protection mode.

The protection circuit can not only carry out current-limiting protection on the power tube, but also limit the voltage difference between the source electrode and the drain electrode of the power tube, thereby limiting the power tube on the power layer and comprehensively protecting the safety of the power tube.

IN some possible implementations, the power transistor may be a PMOS, and the source of the power transistor is connected to the input terminal (IN), and the drain of the power transistor is connected to the output terminal (OUT). The protection circuit can realize current-limiting protection and power-limiting protection of a P-type power tube (such as PMOS), and has high reliability.

In some possible implementations, the clamping branch includes a first PMOS, a second PMOS, at least one third PMOS, and switches corresponding to the third PMOS one to one. And the third PMOS is used for adjusting the source drain clamping voltage threshold of the power tube.

Specifically, the source of the first PMOS is connected to the input terminal, the gate of the first PMOS is connected to the drain of the first PMOS, the source of the second PMOS is connected to the input terminal, the gate of the second PMOS is connected to the drain of the first PMOS, and the drain of the first PMOS is connected to the source of one third PMOS of the at least one third PMOS. When the number of the third PMOSs is multiple, the grid electrode and the drain electrode of one third PMOS in the at least one third PMOS are connected with the source electrode of the next third PMOS, and the grid electrode and the drain electrode of the last third PMOS in the at least one third PMOS are connected to the output end.

For ease of understanding, the following description is made with reference to specific examples. As shown in fig. 3, the clamp branch includes a first PMOS, a second PMOS and a plurality of third PMOS, the first PMOS is denoted as P1, the second PMOS is denoted as M3, the plurality of third PMOS are denoted as P1, P2 and P3, and the switches corresponding to P1, P2 and P3 are K1, K2 and K3, respectively.

The gate of P1 is connected to the drain and output of P1 and one end of the corresponding switch K1, the source of P1 is connected to the other end of K1, and the gate and drain of P2 and one end of P2 corresponding to the switch K2 are connected. The source of P2 is connected to the gate and drain of P3, the other end of K2, and one end of switch K3 corresponding to P3. The source of the P3 is connected to the drain and gate of the first PMOS, the gate of the second PMOS and the other end of the K3. Wherein, K1, K2, K3 correspond to K1, K2, K3 in the bias branch.

Optionally, the clamping branch further includes an inverter and a first N-type power transistor (NMOS), a drain of the second PMOS is connected to an input terminal of the inverter, an output terminal of the inverter is connected to a gate of the first NMOS, and a drain of the first NMOS is connected to the biasing branch.

Therefore, when the source-drain voltage of the power tube is larger than the source-drain clamping voltage threshold, the first PMOS is started, and the second PMOS carries out mirror image on the current flowing through the first PMOS to obtain the current flowing through the second PMOS. The phase inverter is used for outputting low level to turn off the first NMOS when the current of the second PMOS is larger than the preset constant current, so that the resistance in the bias branch circuit is increased, the bias current in the bias branch circuit is reduced, and the current of the power tube is reduced along with the reduction of the bias current.

In some possible implementations, the bias branch includes a plurality of bias resistors, and at least one of the plurality of bias resistors is connected in parallel with the switch. A switch in parallel with the bias resistor is used to adjust the resistance of the bias branch. For example, when a switch in parallel with a bias resistor is closed, the bias resistor will be caused to be shorted, so that the resistance of the bias branch will be reduced; when the switch in parallel with the bias resistor is turned off, the bias resistor is not short-circuited, and the resistance of the bias branch is increased.

Further, the bias branch also includes a base PMOS. As shown in fig. 3, the basic PMOS may be referred to as M0, the source of the basic PMOS is connected to the input terminal, the gate of the basic PMOS is connected to the gate of the power transistor, and the drain of the basic PMOS is connected to the bias resistor.

In some possible implementations, the bias branch further includes an operational amplifier. The first input end (for example, the inverting input end) of the operational amplifier is connected with a reference voltage, and the second input end (for example, the non-inverting input end) of the operational amplifier is connected with the drain electrode of the basic PMOS. The operational amplifier may be used as a comparator to compare the magnitude of the voltage at the positive input terminal and the magnitude of the voltage at the negative input terminal to determine whether the input reaches a predetermined value. That is, the operational amplifier can detect whether the voltage drop generated in the bias branch circuit based on the bias current and the bias resistor reaches the reference voltage.

And when the voltage drop generated based on the bias current and the bias resistor is smaller than the reference voltage, the voltage at the output end of the operational amplifier is reduced to the power supply voltage at the reverse input end until the voltage is saturated.

Still taking the example of fig. 3 as an illustration, as shown in fig. 3, the bias resistors include R, R1, R2, R3, R4, R5, R6, switches connected in parallel with the bias resistors R1 to R6 are respectively K1B, K2B, K3B, K1, K2, K3, a drain of the first NMOS (specifically, N1) is connected to a common terminal of R3 and R4, and a common terminal of K1 and K3B. When the drain of the first NMOS is in a high level, R, R1, R2 and R3 are connected into the circuit, and whether R4, R5 and R6 are connected into the circuit or not is further controlled by the switch. When the drain of the first NMOS is low, the first NMOS is turned off, and R, R1, R2, R3, R4, R5 and R6 are all connected into the circuit.

In the embodiment of the application, R, R1, R2, R3, R4, R5, R6 may be resistors of the same type and have a resistance value of R, further, in order to ensure the consistency of the circuit after current limiting, in general, K1 is opposite to K1B, when K1 is closed, K1B is opened, when K1 is opened, K1B is closed, and K2 is similar to K2B, and K3 is similar to K3B.

In this embodiment, when the power transistor enters the current-limiting protection mode, the product of the output current of the power transistor and the maximum voltage of the input terminal is smaller than the rated power of the power transistor. As shown in fig. 3, the product of the output current (ISW) of the power tube and the maximum voltage at the input end is smaller than the rated power of the power tube. Therefore, the power tube can be prevented from being burnt out due to over power, and over power protection is realized.

In some possible implementations, the current of the power tube is limited by the bias current. For example, the maximum current of the power tube may be M times the bias current. The magnitude of the bias current can be adjusted by adjusting the magnitude of the bias resistor on the bias branch.

In particular, the switches with parallel biasing resistors can be assigned different current steps from a truth table. As shown in fig. 3, in the drawing, K1, K2, and K3 may be allocated with different current gears by a truth table, and it should be noted that the allocation of K1, K2, and K3 in this embodiment is only an example, and actually has a plurality of combinations, and this embodiment is not limited herein.

The sum of the effective resistances of the bias branches is recorded as R0, the bias current is equal to the reference voltage/R0, and the maximum current of the power tube is equal to M × reference voltage/R0.

The truth tables of K1, K2 and K3 can be shown in the first three columns of table 1 below, where 1 indicates that the switch is closed and 0 indicates that the switch is open, and the corresponding resistor is connected into the circuit.

Truth tables of tables 1K1, K2, K3

The fourth column is bias current corresponding to a switching state, the fifth column is current flowing through the power tube correspondingly, the sixth column is input and output voltage corresponding to the switching state, the seventh column is maximum power, and the eighth column is current-limiting current. As shown in fig. 3, where R, R1, R2, R3, R4, R5, R6 are all the same type, and the resistances are all R, and M1, M2, P1, P2, P3 are all the same type, K1 in the bias branch is the same direction as K1 in the clamp branch, and is opposite to K1B in the bias branch, K2 in the bias branch is the same direction as K2 in the clamp branch, and is opposite to K2B in the bias branch, and K3 in the bias branch is the same direction as K3 in the clamp branch, and is opposite to K3B in the bias branch.

Specifically, when the true values of K1, K2, and K3 correspond to 000, that is, K1 is turned off, K2 is turned off, and K3 is turned off, the resistances connected to the bias branches are R4, R5, and R6, so that the bias current IBIAS becomes VREF/3R, and the output current ISW of the power tube becomes M IBIAS, that is, the output current ISW of the power tube becomes M VREF/3R. IN the clamp branch, the PMOS connected to the clamp branch includes 4 series-connected PMOS transistors M1, P3, P2, and P1, then the input-output voltage IN-OUT is 4Vgs, and the maximum power Pmax of the power transistor is IBIAS IN-OUT, that is, Pmax is 4/3M VREF Vgs/R. Due to the arrangement in the bias branch, the resistances connected to the bias branch after the current limiting protection mode are R, R4, R5, and R6, so that the current limiting current ILIM is VREF/4R × M.

When the true values of K1, K2, and K3 correspond to 100, that is, K1 is closed, K2 is opened, and K3 is opened, the resistances connected to the bias branches are R5 and R6, so that the bias current IBIAS is VREF/2R, and the output current ISW of the power tube is M IBIAS, that is, the output current ISW of the power tube is M VREF/2R. IN the clamping branch, the PMOS connected to the clamping branch includes 3 PMOS transistors connected IN series, M1, P3, and P2, so that the input-output voltage IN-OUT is 3Vgs, and the maximum power Pmax of the power transistor is IBIAS IN-OUT, that is, Pmax is 3/2M VREF Vgs/R. Due to the arrangement in the bias branch, the resistances connected to the bias branch after the current limiting protection mode are R, R1, R5, and R6, so that the current limiting current ILIM is VREF/4R × M.

When the true values of K1, K2, and K3 correspond to 110, that is, K1 is closed, K2 is closed, and K3 is open, the resistance connected to the bias branch is R6, so that the bias current IBIAS is VREF/R, and the output current ISW of the power tube is M IBIAS, that is, the output current ISW of the power tube is M VREF/R. IN the clamp branch, the PMOS connected to the clamp branch includes 2 PMOS transistors connected IN series, i.e., M1 and P3, so that the input-output voltage IN-OUT is 2Vgs, and the maximum power Pmax of the power transistor is IBIAS IN-OUT, i.e., Pmax is 2M VREF Vgs/R. Due to the arrangement in the bias branch, the resistances connected to the bias branch after the current limiting protection mode are R, R1, R2, and R6, so that the current limiting current ILIM is VREF/4R × M.

Therefore, the clamping voltage of the source and the drain of the power tube can be automatically adjusted at different current gears. When the output voltage is reduced, the source-drain voltage of the power tube is greater than the clamping voltage, the first PMOS is started, the larger the source-drain voltage difference of the power tube is, the larger the current of the first PMOS is, the second PMOS mirrors the first PMOS current, and when the second PMOS current is greater than the constant current, the inverter outputs a low level, and the first NMOS is turned off. The resistance of the bias current branch is increased, the bias current is reduced, the current of the power tube is also folded back into small current, and the power tube enters current-limiting protection. The product of the small current after the return and the maximum voltage of the input end is less than the rated power.

According to the truth table, the test results are shown in fig. 4, where CLM represents the truth of K3, K2, and K1, CLM 000 represents K3 open, K2 open, and K1 open, CLM 100 represents K3 closed, K2 open, and K1 open, and CLM 111 represents K3 closed, K2 closed, and K1 closed.

The larger the output current is, the smaller the source-drain clamp voltage Vds is, and once the clamp voltage is triggered, the current foldback may occur, and the current is limited to be within 0.5A. And only when the source-drain voltage is less than the clamping voltage, the small current can be withdrawn, and the power tube is recovered to be normal.

In some possible implementations, the protection circuit of the power transistor may be as shown in fig. 5, and the circuit further includes an inverter and a fourth PMOS. The input end of the phase inverter is connected with the drain electrode of the second PMOS, the input end of the phase inverter is connected with the grid electrode of the fourth PMOS, the source electrode of the fourth PMOS is connected with the input end, and the drain electrode of the fourth PMOS is connected with the power tube and the grid electrode of the basic PMOS.

In this way, the circuit can be protected by turning off the power transistor. When the source-drain voltage of the power tube is greater than the output clamping voltage, the power tube is turned off, so that the power tube can be protected.

In summary, the present embodiment provides a protection circuit for a power transistor, where the protection circuit includes a bias branch connected to a gate of the power transistor and a clamp branch connected between a source of the power transistor and the gate of the power transistor, the source of the power transistor is connected to an input terminal, and a drain of the power transistor is connected to an output terminal. The bias branch circuit is used for providing bias current, the output current of the power tube is limited by the bias current, and the clamp branch circuit is used for reducing the bias current when the source-drain voltage of the power tube is larger than the source-drain clamp voltage threshold value, so that the output current of the power tube can be reduced. Therefore, the protection circuit not only for the power tube by the control circuit is provided, the protection circuit can combine current limiting and clamping, adaptively adjust the current of the power tube according to the source-drain pressure difference of the power tube, realize the control of the power on the power tube, and fundamentally reduce the risk of thermal damage of the power tube.

Corresponding to the circuit embodiment, the present application further provides a power protection chip, as shown in fig. 6, including the protection circuit of the power transistor.

From the above description of the embodiments, it is clear for those skilled in the art that all or part of the steps in the above embodiments may be implemented by software plus a necessary general hardware platform. Based on such understanding, the technical solutions of the present application may be essentially or partially implemented in the form of software products, which may be stored in a storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and include instructions for causing a computer device (which may be a personal computer, a server, or a network communication device such as a media gateway, etc.) to execute the solutions described in the embodiments or some parts of the embodiments of the present application.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the scheme disclosed by the embodiment, the scheme corresponds to the system disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the system part for description.

It should also be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing description of the disclosed embodiments will enable those skilled in the art to make or use the invention in various modifications to these embodiments, which will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A protection circuit of a power tube is characterized in that the circuit comprises a bias branch connected to a grid electrode of the power tube and a clamping branch connected between a source electrode and a drain electrode of the power tube, wherein the source electrode of the power tube is connected with an input end, and the drain electrode of the power tube is connected with an output end;

2. The circuit of claim 1, wherein the product of the output current of the power tube entering the current-limiting protection mode and the maximum voltage of the input end is smaller than the rated power of the power tube.

3. The circuit of claim 1, wherein the clamping branch comprises a first P-type metal oxide semiconductor field effect transistor (PMOS), a second PMOS, at least one third PMOS and switches corresponding to the third PMOS in a one-to-one manner, and the third PMOS is used for adjusting a source-drain clamping voltage threshold of the power tube;

4. The circuit of claim 3, wherein the clamping branch further comprises an inverter and a first N-type metal oxide semiconductor field effect transistor (NMOS), the second PMOS is connected to the gate of the first NMOS through the inverter, and the drain of the first NMOS is connected to the biasing branch.

5. The circuit of claim 4, wherein when a source-drain voltage of the power transistor is greater than a source-drain clamp voltage threshold, the first PMOS is turned on, the second PMOS is used for mirroring a current of the first PMOS to obtain a current of the second PMOS, and the inverter is used for outputting a low level when the current of the second PMOS is greater than a preset constant current, so that the first NMOS is turned off, the resistance of the bias branch is increased, the bias current is decreased, and the current of the power transistor is decreased along with the decrease of the bias current.

6. The circuit of claim 3, further comprising an inverter and a fourth PMOS, wherein an input terminal of the inverter is connected to a drain of the second PMOS, an output terminal of the inverter is connected to a gate of the fourth PMOS, a source of the fourth PMOS is connected to the input terminal, and a drain of the fourth PMOS is connected to a gate of the power transistor.

7. The circuit according to any one of claims 1 to 6, wherein the bias branch comprises a plurality of bias resistors, at least one of the plurality of bias resistors is connected in parallel with a switch, and the switch connected in parallel with the bias resistor is used for adjusting the resistance of the bias branch.

8. The circuit of claim 7, wherein the bias branch further comprises a basic PMOS, a gate of the basic PMOS is connected with the gate of the power transistor, a source of the basic PMOS is connected with the input terminal, and a drain of the basic PMOS is connected with the bias resistor.

9. The circuit of claim 8, wherein the bias branch further comprises an operational amplifier, a first input terminal of the operational amplifier is connected to a reference voltage, and a second input terminal of the operational amplifier is connected to the drain of the basic PMOS.

10. A power protection chip, characterized in that the power protection chip comprises a power tube and a protection circuit of the power tube according to any one of claims 1 to 9.

11. An electronic device characterized in that it comprises a power supply and a power protection chip as claimed in claim 10.