CN114325357A - DEBUG system, method, device and medium - Google Patents

Abstract

The present application discloses a DEBUG system, including a main controller and a collector. The main controller is connected with the JTAG emulator, and the main controller accepts the access of the JTAG emulator and decodes the access information to obtain the IP where the signal to be observed is located. The main controller is connected with each collector through the JTAG protocol to exchange information. Each collector is connected to the signal to be observed in the chip, and acquires the data of the signal to be observed. The main controller controls the corresponding target collector to acquire the data of the signal to be observed according to the IP of the signal to be observed. With this technical solution, the signal to be observed is directly connected to the collector of the system, and the main controller directly controls the collector to obtain the data of the signal to be observed through the access of the simulator, without acquiring the data of other signals. , reducing the waste of resources and time. The present application also discloses a DEBUG method, a device and a medium, which correspond to the above system and have the same effects as above.

Description

A DEBUG system, method, device and medium

technical field

The present application relates to the technical field of troubleshooting, and in particular, to a DEBUG system, method, device and medium.

Background technique

Boundary scan test technology is a very commonly used technology for troubleshooting (DEBUG), which is used to solve the test difficulties caused by too many pins of chips on a printed circuit board, and is also used for connection testing between chips. problems and testing of the entire system. Boundary scan test technology is a test method of serial transmission by adding a scan chain and a test access port between the boundary of the internal logic of the chip and the external pins, test excitation information, and serial transmission.

However, this method can only observe the chip signal in a step-by-step manner. To observe the signal to be observed, it is necessary to observe the preceding signal first, resulting in a waste of observation resources and time.

It can be seen that how to reduce the waste of resources and time when observing the signal to be observed is an urgent problem to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of this application is to provide a DEBUG system, method, device and medium for reducing the waste of resources and time when observing the signal to be observed.

In order to solve the above-mentioned technical problems, the application provides a DEBUG system, including:

Main controller 1 and collector 2;

The main controller 1 is connected with the JTAG emulator 3, receives the access of the JTAG emulator 3 and decodes to obtain the IP where the signal to be observed is located;

The main controller 1 is connected with each of the collectors 2 through the Joint Test Action Group (JTAG) protocol;

Each of the collectors 2 is connected to the signal to be observed in the chip;

The main controller 1 controls the corresponding target collector to acquire the data of the signal to be observed according to the IP where the signal to be observed is located.

In order to solve the above-mentioned technical problem, the application also provides a kind of DEBUG method, is applied to above-mentioned DEBUG system, comprises:

Obtain the IP of the signal to be observed sent by the JTAG emulator;

Select the corresponding target collector according to the IP where the signal to be observed is located;

The target collector is controlled to latch the data of the signal to be observed.

Preferably, before the step of controlling the target collector to latch the data of the signal to be observed, the method further includes:

acquiring an observation mode of the to-be-observed signal, where the observation mode includes a direct observation mode and a conditional observation mode;

Further, the controlling the target collector to latch the data of the signal to be observed includes: controlling the target collector to latch the data of the signal to be observed according to the observation mode.

Preferably, if the observation mode is a direct observation mode, the controlling the target collector to latch the data of the to-be-observed signal according to the observation mode includes:

The target collector is controlled to latch the data of the signal to be observed at the current moment.

Preferably, if the observation mode is a conditional observation mode, the controlling the target collector to latch the data of the signal to be observed according to the observation mode includes:

Acquire the addresses of each register of the signal to be observed and the corresponding target data;

When the real-time data corresponding to the addresses of the registers of the signal to be observed satisfies the target data, the target collector is controlled to latch the real-time data satisfying the target data and the addresses of the corresponding registers.

Preferably, it also includes:

Query whether the state of each register of the target collector is empty, if not, close the collector.

Preferably, it also includes:

Obtain the time information of the data moment at which the target collector latches the signal to be observed.

Preferably, it also includes:

Obtain the observation chain information sent by the JTAG emulator, where the observation chain information includes the IP where each of the to-be-observed signals on the observation chain is located;

According to the observation chain information, all the target collectors on the observation chain are controlled to latch the corresponding data of the to-be-observed signal.

In order to solve the above-mentioned technical problems, the application also provides a DEBUG device, comprising a memory for storing a computer program;

The processor is configured to implement the steps of the above DEBUG method when executing the computer program.

To solve the above technical problem, the present application also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and the computer program implements the steps of the DEBUG method described above when executed by a processor.

The DEBUG system provided in this application includes a main controller and a collector. The main controller is connected with the JTAG emulator, and when the JTAG emulator sends out access, the main controller accepts the access and decodes the access information, so as to obtain the IP where the signal to be observed is located. The main controller is connected with each collector through the JTAG protocol to exchange information. Each collector is connected to the signal to be observed in the chip, and is used to acquire the data of the signal to be observed. The main controller can control the corresponding target collector to acquire the data of the signal to be observed according to the IP where the signal to be observed is located. Compared with the current technology, the signal of the chip needs to be observed step by step. With this technical solution, the signal to be observed in the chip is directly connected to the collector of the DEBUG system, and the main controller directly controls the collector to obtain the data of the signal to be observed through the access of the JTAG emulator, without the need to obtain the data of other signals. When the signal is observed, the waste of resources and time is reduced.

In addition, the DEBUG method, device and medium provided in this application correspond to the above DEBUG system, and the effects are the same as above.

Description of drawings

In order to describe the embodiments of the present application more clearly, the following will briefly introduce the drawings that are used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, which are not relevant to ordinary skills in the art. As far as personnel are concerned, other drawings can also be obtained from these drawings on the premise of no creative work.

Fig. 1 is the structural diagram of a kind of DEBUG system that the embodiment of this application provides;

2 is a structural diagram of a main controller provided by an embodiment of the present application;

FIG. 3 is a structural diagram of a collector provided by an embodiment of the present application;

Fig. 4 is the flow chart of a kind of DEBUG method that the embodiment of this application provides;

5 is a structural diagram of a DEBUG device provided in an embodiment of the present application;

Reference numerals are as follows: 1 is the main controller, 2 is the collector, 3 is the JTAG emulator, 4 is the TAP controller, 5 is the multiplexer, 6 is the signal acquisition controller, 7 is the decoder, and 8 is the signal latch.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative work fall within the protection scope of the present application.

Boundary scan test technology is a very commonly used technology for DEBUG. It is used to solve the test difficulty caused by too many pins of the chip on the printed circuit board, and it is also used for the connection test problem between chips and the whole system. 's test. Boundary scan test technology is a test method of serial transmission by adding a scan chain and a test access port between the boundary of the internal logic of the chip and the external pins, test excitation information, and serial transmission.

However, this method can only observe the chip signal in a step-by-step manner. To observe the signal to be observed, it is necessary to observe the preceding signal first, resulting in a waste of observation resources and time.

The core of the present application is to provide a DEBUG system, method, device and medium for reducing the waste of resources and time when observing the signal to be observed.

In order to make those skilled in the art better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

Fig. 1 is a structural diagram of a DEBUG system provided by an embodiment of the present application. As shown in Fig. 1, the system includes:

Main controller 1 and collector 2;

The main controller 1 is connected with the JTAG emulator 3, receives the access of the JTAG emulator 3 and decodes it to obtain the IP of the signal to be observed; the main controller 1 is connected with each collector 2 through the JTAG protocol; each collector 2 is connected to the The signal to be observed in the chip is connected; the main controller 1 controls the corresponding target collector to acquire the data of the signal to be observed according to the IP where the signal to be observed is located.

IP: Abbreviation for Intellectual Property, which means: Influence Assets. It is a kind of intellectual property, and in this embodiment, it can be understood as a module of the chip. When each IP is designed, some important signals are uniformly connected to the top layer of the IP, and these signals are the signals to be observed. The signal to be observed can be an independent signal or the data of the IP internal register.

In the embodiment of the present application, the main controller 1 is connected to the JTAG emulator 3 through the JTAG pins, receives the access of the JTAG emulator 3 and decodes it to obtain the IP where the signal to be observed is located, and controls the corresponding acquisition through the IP The device 2 works to obtain the data of the signal to be observed.

FIG. 2 is a structural diagram of a main controller according to an embodiment of the present application. As shown in FIG. 2 , the main controller 1 includes a TAP controller 4 and a multiplexer 5 . Among them, the TAP controller 4 includes the JTAG protocol state machine and part of the control logic, which realizes the preliminary analysis of the JTAG protocol coming in from the JTAG pins of the JTAG emulator 3, and chooses to control a certain collector 2, or choose to control a certain one. The JTAG link is connected between the TDI and TDO interfaces of the JTAG protocol to complete the access to the inside of the chip, and send the selected information to the multiplexer 5 for implementation. The multiplexer 5 parses the output information according to the output of the TAP controller 4, selects a certain JTAG link, outputs the TDI to the selected JTAG chain, and returns the output TDO signal of the JTAG link to the TAP controller 4 to realize The information exchange between the main controller 1 and the collector 2.

FIG. 3 is a structural diagram of a collector provided by an embodiment of the present application. As shown in FIG. 3 , the collector 2 includes a signal acquisition controller 6 , a decoder 7 and a signal latch 8 . Among them, the signal acquisition controller 6 is used to parse the JTAG protocol transmitted by the main controller 1 or other collectors 2, and convert it into an internal register reading and writing protocol, that is, convert the serial TDI into parallel reading or writing, and convert the read and write protocols. The data is converted to serial TDO output. Meanwhile, the signal acquisition controller 6 provides a self-defined control register group, and the self-defined control register group mainly realizes the following functions: controlling the enable switch of the collector 2; selecting the latch mode of the register. Among them, the latch mode of the selection register is mainly realized by the following registers:

Mode selection register: Provides direct latch mode and conditional latch mode. When the configuration is in direct latch mode, after the configuration signal latch 8 is enabled, the collector 2 will directly latch the latch value of the currently selected signal to be observed. When configured as conditional latch mode, after the configuration signal latch 8 is enabled, the latch of the selected signal to be observed will be monitored until it reaches the configured target value, and all the pending signals in the IP will be monitored. The latch value of the observation signal is latched.

Latch register: After configuring this register, control the collector 2 to latch the current latch value of the signal to be observed, and no real-time changes will occur.

Latch condition register: The latch condition includes two conditions of address and data. When the signal value of the collector 2 corresponding to the configured address reaches the configured data value, it is latched.

Latch state register: used to feed back the latch state of the currently selected signal latch 8.

The decoder 7 in the collector 2 can select a corresponding offset address register according to the address of the register read-write protocol converted by the signal acquisition controller 6 to collect specific data in the signal to be observed.

The signal latch 8 in the collector 2 receives the observation signal and receives the control information of the signal acquisition controller 6 . When the latched signal is received, the latching of the signal to be observed is realized, and the value of the latched signal no longer changes in real time.

The DEBUG system provided by the embodiments of the present application includes a main controller and a collector. The main controller is connected with the JTAG emulator, and when the JTAG emulator sends out access, the main controller accepts the access and decodes the access information, so as to obtain the IP where the signal to be observed is located. The main controller is connected with each collector through the JTAG protocol to exchange information. Each collector is connected to the signal to be observed in the chip, and is used to acquire the data of the signal to be observed. The main controller can control the corresponding target collector to acquire the data of the signal to be observed according to the IP where the signal to be observed is located. Compared with the current technology, the signal of the chip needs to be observed step by step. With this technical solution, the signal to be observed in the chip is directly connected to the collector of the DEBUG system, and the main controller directly controls the collector to obtain the data of the signal to be observed through the access of the JTAG emulator, without the need to obtain the data of other signals. When the signal is observed, the waste of resources and time is reduced.

In the above-mentioned embodiments, the DEBUG system is described in detail, and the embodiments of the present application further provide a DEBUG method, which is applied to the above-mentioned DEBUG system. FIG. 4 is a flowchart of a DEBUG method provided by an embodiment of the present application. As shown in FIG. 4 , the method includes:

S10: Obtain the IP where the signal to be observed sent by the JTAG emulator 3 is located.

JTAG emulator 3, also called JTAG debugger, is a device that debugs through the JTAG boundary scan port of the ARM chip. In step S10, the user selects the signal to be observed of the chip to be observed by setting the JTAG emulator 3, and the main controller 1 obtains the information sent by the JTAG emulator 3 through the JTAG pin and parses it to obtain the IP where the signal to be observed is located. . The to-be-observed signal may be one or multiple.

S11: Select a corresponding target collector according to the IP where the signal to be observed is located.

In a specific implementation, each signal to be observed has a corresponding collector 2 . There are often multiple collectors 2 on a JTAG chain. If multiple signals to be observed are located on the same JTAG chain, all collectors 2 on the chain can be selected according to the JTAG chain.

S12: Control the target collector to latch the data of the signal to be observed.

In step S12, the main controller 1 controls the target collector to latch the data of the signal to be observed. The latching time can be latched immediately when the target acquisition receives the control signal from the main controller 1 , or latched when the value of the register of the signal to be observed reaches a preset threshold.

The DEBUG method provided in the embodiment of the present application is applied to the above DEBUG system. The main controller is connected with the JTAG emulator. When the JTAG emulator sends out access, the main controller obtains the access and decodes the access information, so as to obtain the IP where the signal to be observed is located. The main controller is connected with each collector through the JTAG protocol to exchange information. Each collector is connected to the signal to be observed in the chip, and is used to acquire the data of the signal to be observed. The main controller can control the corresponding target collector to acquire the data of the signal to be observed according to the IP where the signal to be observed is located. Compared with the current technology, the signal of the chip needs to be observed step by step. With this technical solution, the signal to be observed in the chip is directly connected to the collector of the DEBUG system, and the main controller directly controls the collector to obtain the data of the signal to be observed through the access of the JTAG emulator, without the need to obtain the data of other signals. When the signal is observed, the waste of resources and time is reduced.

In a specific implementation, for the latching of the signal to be observed, for some relatively simple DEBUG scenarios, it is only necessary to observe the states of certain signals. For DEBUG scenarios with high complexity, technicians need to obtain the status of certain signals under specific conditions.

Therefore, on the basis of the above embodiment, in this embodiment, before the step of controlling the target collector to latch the data of the signal to be observed, the method further includes:

Obtain the observation mode of the signal to be observed, the observation mode includes direct observation mode and conditional observation mode;

Further, controlling the target collector to latch the data of the signal to be observed includes: controlling the target collector to latch the data of the signal to be observed according to the observation mode.

In this embodiment, the observation mode includes a direct observation mode and a conditional observation mode. It should be noted that when the observation mode is the direct observation mode, the collector 2 latches the data of the signal to be observed at the current moment. When the observation mode is the conditional observation mode, the collector 2 will always monitor the data of the signal to be observed, and will latch when the data of the signal to be observed reaches a preset value. It can be understood that there are different registers in the signal to be observed. When the observation mode is the conditional observation mode, the collector 2 will monitor each register according to the address of each register in the signal to be observed. Each register in the signal to be observed has The corresponding target data, when the data of the register reaches the target data, that is, the latch condition, the collector 2 will latch the latch values of all the signals to be observed in the IP at this moment, so that the technician can obtain the specific data. The data of the signal to be observed in the case.

In the DEBUG method provided in the embodiment of the present application, the observation of the signal to be observed is divided into a direct observation mode and a conditional observation mode. In the direct observation mode, the signal to be observed can be observed dynamically in real time. In the conditional observation mode, the data of the signal to be observed in a special and static scene can be obtained, which can more effectively and directly help the verifier to obtain the desired internal state information of the chip. With this technical solution, technicians can choose different observation modes according to their needs, which increases the flexibility of observation.

On the basis of the above embodiment, in this embodiment, if the observation mode is the direct observation mode, controlling the target collector to latch the data of the signal to be observed according to the observation mode includes:

Control the target collector to latch the data of the signal to be observed at the current moment.

In the DEBUG method provided by the embodiments of the present application, when the observation mode is the direct observation mode, the target collector latches the data of each register of the signal to be observed at the current moment, which is conducive to real-time and dynamic observation of the signal to be observed.

On the basis of the above embodiment, in this embodiment, if the observation mode is the conditional observation mode, controlling the target collector to latch the data of the signal to be observed according to the observation mode includes:

Obtain the address of each register of the signal to be observed and the corresponding target data;

In the case that the real-time data corresponding to the addresses of each register of the signal to be observed satisfies the target data, the registers of the target collector are controlled to latch the real-time data satisfying the target data and the address of the corresponding register.

In this embodiment, after setting the address of each register of the signal to be observed and the corresponding target data, the collector 2 monitors each register. When the real-time data corresponding to each register reaches the target data, the collector 2 performs latching. Specifically, the decoder 7 in the collector 2 selects the corresponding offset address according to the address of the register read-write protocol converted by the signal acquisition controller 6, and can be obtained by adding the offset address to the address of the register read-write protocol The address of the register of the signal to be observed, which is used to collect specific data in the signal to be observed. It can be understood that the collector 2 latches when the real-time data in the register in the signal to be observed reaches the target data, and if the target data is not reached, the collector 2 continues to monitor and latches after it reaches the target data. .

The DEBUG method provided in the embodiment of the present application, when the observation mode is the conditional observation mode, acquires the data of the signal to be observed in a special and static scene, which can more effectively and directly help the verifier to obtain the desired chip Internal status information.

In a specific implementation, after each register in the collector 2 acquires the data of the signal to be observed, the collector 2 is no longer used, but the collector 2 is still in an enabled state, resulting in a waste of resources.

On the basis of the above embodiment, in this embodiment, it also includes:

Check whether the status of each register of the target collector is empty, if not, turn off collector 2.

The DEBUG method provided in the embodiment of the present application queries whether the status of each register of the target collector is empty. If not, it means that the collector has acquired the data of the signal to be observed. Therefore, the collector is turned off to reduce the waste of resources. .

As the test clock input pin of JTAG, TCK can add time information to the JTAG system. On the basis of the above embodiment, in this embodiment, it also includes:

Obtain the time information of the data moment when the target collector latches the signal to be observed.

In the DEBUG method provided by the embodiment of the present application, the main controller acquires time information, and adds a timestamp to the data of the signal to be observed each time the target collector latches, so that the change trend of the signal to be observed can be judged.

It should be noted that the collector 2 is located on the JTAG chain, and the JTAG is linked to the TDI and TDO of the main controller 1. There may be many collectors 2 on a JTAG chain. In the specific implementation, if you want to observe the signal to be observed on a JTAG chain, it also includes:

Obtain the observation chain information sent by the JTAG emulator 3, the observation chain information includes the IP where each signal to be observed on the observation chain is located; according to the observation chain information, all collectors 2 on the observation chain are controlled to latch the data of the corresponding signal to be observed.

The DEBUG method provided by the embodiment of the present application controls the operation of all collectors on a JTAG chain according to the observation chain information, acquires data of all the signals to be observed on the JTAG chain, and realizes large-scale monitoring of the signals to be observed.

In the above embodiments, the DEBUG method is described in detail, and the present application also provides the corresponding embodiments of the DEBUG device.

Since the embodiment of the apparatus part corresponds to the embodiment of the method part, for the embodiment of the apparatus part, please refer to the description of the embodiment of the method part, which will not be repeated here.

FIG. 5 is a structural diagram of a DEBUG device provided by an embodiment of the application. As shown in FIG. 5 , the device includes: a memory 20 for storing a computer program;

The processor 21 is configured to implement the steps of the DEBUG method in the above-mentioned embodiment when executing the computer program.

The DEBUG device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.

The processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 21 may be implemented in at least one hardware form among digital signal processing (Digital Signal Processing, DSP), field-programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). . The processor 21 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake-up state, also called a central processing unit (CPU); A low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a graphics processor (Graphics Processing Unit, GPU), and the GPU is responsible for rendering and drawing the content that needs to be displayed on the display screen. In some embodiments, the processor 21 may further include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.

Memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201, where, after the computer program is loaded and executed by the processor 21, the relevant steps of the DEBUG method disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory 20 may also include an operating system 202, data 203, etc., and the storage mode may be short-term storage or permanent storage. The operating system 202 may include Windows, Unix, Linux, and the like. The data 203 may include, but is not limited to, the IP where the signal to be observed is located, the data of the signal to be observed, time information, and the like.

In some embodiments, the DEBUG device may further include a display screen 22 , an input/output interface 23 , a communication interface 24 , a power supply 25 and a communication bus 26 .

Those skilled in the art can understand that the structure shown in FIG. 5 does not constitute a limitation on the DEBUG device, and may include more or less components than those shown.

The DEBUG device provided by the embodiment of the present application includes a memory and a processor, and when the processor executes a program stored in the memory, the processor can implement the following method: obtain the IP where the signal to be observed and sent by the JTAG emulator are located; according to the IP where the signal to be observed is located Select the corresponding target collector; control the target collector to latch the data of the signal to be observed.

In the DEBUG device provided by the embodiment of the present application, when the JTAG emulator issues an access, the main controller accepts the access and decodes the access information, so as to obtain the IP where the signal to be observed is located. The main controller is connected with each collector through the JTAG protocol to exchange information. Each collector is connected to the signal to be observed in the chip, and is used to acquire the data of the signal to be observed. The main controller can control the corresponding target collector to acquire the data of the signal to be observed according to the IP where the signal to be observed is located. Compared with the current technology, the signal of the chip needs to be observed step by step. With this technical solution, the signal to be observed in the chip is directly connected to the collector of the DEBUG system, and the main controller directly controls the collector to obtain the data of the signal to be observed through the access of the JTAG emulator, without the need to obtain the data of other signals. When the signal is observed, the waste of resources and time is reduced.

Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the steps described in the foregoing method embodiments are implemented.

It can be understood that, if the methods in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

In the computer-readable storage medium provided by the embodiment of the present application, when the JTAG emulator issues an access, the main controller accepts the access and decodes the access information, so as to obtain the IP where the signal to be observed is located. The main controller is connected with each collector through the JTAG protocol to exchange information. Each collector is connected to the signal to be observed in the chip, and is used to acquire the data of the signal to be observed. The main controller can control the corresponding target collector to acquire the data of the signal to be observed according to the IP where the signal to be observed is located. Compared with the current technology, the signal of the chip needs to be observed step by step. With this technical solution, the signal to be observed in the chip is directly connected to the collector of the DEBUG system, and the main controller directly controls the collector to obtain the data of the signal to be observed through the access of the JTAG emulator, without the need to obtain the data of other signals. When the signal is observed, the waste of resources and time is reduced.

The DEBUG system, method, device and medium provided by the present application have been described in detail above. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or operations. There is no such actual relationship or sequence between operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion such that a process, method, article or device comprising a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Claims (10)

1. a DEBUG system, is characterized in that, comprises: a main controller (1) and a collector (2); The main controller (1) is connected with the JTAG emulator (3), receives the access of the JTAG emulator (3) and decodes to obtain the IP where the signal to be observed is located; The main controller (1) is connected with each of the collectors (2) through the JTAG protocol; Each of the collectors (2) is connected to the signal to be observed in the chip; The main controller (1) controls a corresponding target collector to acquire data of the to-be-observed signal according to the IP where the to-be-observed signal is located. 2. a DEBUG method, is characterized in that, is applied to the described DEBUG system of claim 1, comprises: Obtain the IP of the signal to be observed sent by the JTAG emulator; Select the corresponding target collector according to the IP where the signal to be observed is located; The target collector is controlled to latch the data of the signal to be observed. 3. DEBUG method according to claim 2, is characterized in that, before the described control described target collector latches the step of the data of the signal to be observed, also comprises: acquiring an observation mode of the to-be-observed signal, where the observation mode includes a direct observation mode and a conditional observation mode; Further, the controlling the target collector to latch the data of the signal to be observed includes: controlling the target collector to latch the data of the signal to be observed according to the observation mode. 4. The DEBUG method according to claim 3, wherein if the observation mode is a direct observation mode, the control of the target collector to latch the data of the signal to be observed according to the observation mode comprises: : The target collector is controlled to latch the data of the signal to be observed at the current moment. 5 . The DEBUG method according to claim 3 , wherein if the observation mode is a conditional observation mode, the control of the target collector to latch the data of the signal to be observed according to the observation mode comprises: 6 . : Acquiring addresses of each register of the signal to be observed and corresponding target data; In the case that the real-time data corresponding to the addresses of the registers of the signal to be observed satisfies the target data, the target collector is controlled to latch the real-time data satisfying the target data and the addresses of the corresponding registers. 6. the DEBUG method according to any one of claims 2 to 5, is characterized in that, also comprises: Query whether the state of each register of the target collector is empty, if not, close the collector. 7. DEBUG method according to claim 6, is characterized in that, also comprises: Acquire time information of the data moment at which the target collector latches the signal to be observed. 8. DEBUG method according to claim 2, is characterized in that, also comprises: Obtain the observation chain information sent by the JTAG emulator, where the observation chain information includes the IP where each of the to-be-observed signals on the observation chain is located; According to the observation chain information, all the target collectors on the observation chain are controlled to latch the corresponding data of the to-be-observed signal. 9. a DEBUG device, is characterized in that, comprises memory, is used for storing computer program; The processor is configured to implement the steps of the DEBUG method according to any one of claims 2 to 8 when executing the computer program. 10. A computer-readable storage medium, characterized in that, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the DEBUG as described in any one of claims 2 to 8 is realized steps of the method.

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