CN101382583B - JTAG debugging method for multi-core microprocessor - Google Patents

Abstract

The invention discloses a multi-core microprocessor JTAG debugging method, and the technical problem to be solved is to debug multiple IP cores in the multi-core processor through a single JTAG debugging interface. The technical solution is to first add a debugging support module composed of chain selection instruction register, decoder, first multiplexer and second multiplexer in the multi-core microprocessor as the debugging interface of the whole multi-core chip, and in A chain selection command is added in the debugging software of the multi-core chip, and then the enable signal of the chain selection command of k TCK clock low levels is maintained by the JTAG emulator, and finally the multi-core microprocessor is debugged by using the debugging support module. The invention can debug a plurality of cores in a multi-core chip through a JTAG debugging interface, the number of supported cores is up to 2 ^k , and the original single-core debugging software can be reused.

Description

JTAG debugging method for multi-core microprocessor

Technical field: the present invention relates to a debugging method based on the JTAG standard of a microprocessor chip, especially a method for JTAG debugging of a multi-core microprocessor chip.

Background technology: With the increase of the scale of the problem and the improvement of the real-time requirement, the processing capability of the single-core microprocessor has been difficult to meet the requirement. Multi-core technology brings unprecedented advantages to device developers, including higher processor performance, higher power utilization efficiency and smaller physical memory size for embedded devices. However, the multi-core structure significantly increases the complexity of the system. With the popularization of the multi-core structure in a single chip, the debugging problem of the multi-processor system becomes more and more prominent.

At present, most IP (Intellectual Property, intellectual property rights) modules use the JTAG interface of the IEEE1149.1 standard as their debugging interface, which brings a problem: there are multiple TAP (Test Access Port, test access ports) ) controller. Some IP providers have used their own developed chip-level channels to support debugging a single IP block. In order to be able to debug multiple cores, a standard on-chip access to all TAP controllers is necessary. In addition, on a complex system chip, multiple different cores will use different debugging tools. How to make the debugging tools of these single IP modules continue to function is also an important issue. It is obviously a waste to develop new debugging software if only integrating multiple IPs that need to be debugged on a multi-core microprocessor chip. The best way is to be able to reuse those debugging tools for a single IP, with no or only a small amount of modification on the software.

In multi-core processors, developers hope to debug these cores by accessing multiple cores integrated on-chip through a single JTAG interface off-chip. At present, the most commonly used method for JTAG debugging of multi-core processors is the daisy-chain method. TDI (Test DataInput, test data input) and TDO (Test Data Output, test data output) of all IP cores are connected into a serial The chain of rows, the TDO of IP _i is connected to the TDI of IP _i+1 (1≤i≤n-1, n is the number of IP cores). The control signals TCK (Test Clock, test clock), TMS (Test Mode Select, test mode selection) and TRST (Test Reset, test reset) are connected to the TAP controllers of all IP cores. During the instruction scanning operation, the instruction is serially shifted into the instruction register of each IP core TAP, so that multiple TAP controllers can be accessed at the same time, and the input and output signals on the boundaries of each IP core can be captured at the same time. For interconnection testing Great value. However, this daisy-chain connection on a single chip has two disadvantages: first, it is not compatible with the IEEE 1149.1 protocol; second, it complicates test access to a single TAP controller in n IP cores.

In order to achieve compatibility with the IEEE 1149.1 protocol, someone proposed a scheme to increase the TAP connection module TLM (TAP Linking Module), which only provides a TAP interface fully compatible with the IEEE 1149.1 protocol on the multi-core microprocessor chip, and provides TDI externally. , TMS, TCK, TRST and TD05 pins, the JTAG debugging interface of the emulator is connected to each TAP through the TLM, and the TLM is responsible for connecting the signal of the JTAG debugging interface to the TAP of a specified IP core to be tested, and the chip The TAP of the internal IP core is interconnected with the TLM. In addition to the 5 signal lines of the bound JTAG debugging interface, each TAP also adds a selection signal SEL and an enable signal ENA. Which one or which ones are determined by SEL and ENA The TAP of each IP core is connected to the JTAG debugging interface of the emulator. TLM transmits the test signals TDI, TMS, TCK, and TRST of the emulator to the corresponding TDI, TMS, TCK, and TRST ports of a certain TAP in the chip according to SEL and ENA, and the data output by the TDO port of the TAP passes through the TDO pin. The JTAG emulator is sent to the debugging host to implement JTAG debugging of a certain IP core in the multi-core chip. However, this method must add additional selection and enable signals to the TAP inside the IP core, which requires modifying the TAP inside the IP core and adding the ENA and SEL signals to the design of the TAP. The TAP controller of each TAP obtains ENA from the TLM as an input to enable or disable the TAP, and the instruction register in the TAP increases the SEL signal output to the TLM in response to the instruction scanned into its instruction register, which makes the hardware design complicated. This modification is not possible if the IP core is a hard core. Since TLM can connect multiple IP-core TAPs, and the modification of TAP on the hardware makes it necessary to integrate the modified single-core debugging software into multi-core chip debugging in addition to modifying the original single-IP-core debugging software. Software, which also makes the design of the debugging software complicated, and the reusability is not good.

Therefore, in the field of multi-core processor debugging, there is an urgent need for a debugging method that is compatible with the IEEE 1149.1 protocol and can reuse each core to debug each core of the multi-core processor.

Invention content:

The technical problem to be solved by the present invention is exactly how to make it possible to carry out JTAG debugging to multiple IP cores integrated in a multi-core processor through a single JTAG debugging interface based on the IEEE 1149.1 standard.

Technical scheme of the present invention comprises the following steps:

The first step is to add a chip-level TAP controller in the multi-core microprocessor with n IP cores - Debug Support Module DSM (Debug Support Module). The design approach for the debug support module is:

The debugging support module is the debugging interface of the entire multi-core chip. It has a JTAG interface compatible with the IEEE 1149.1 protocol. In addition to the five pins TDI, TMS, TCK, TRST, and TDO, which are connected to the JTAG debugging interface of the emulator, it also adds A multi-core debug selection pin accepts the enable signal MDS (Mutil-core Debug Select) of the chain selection command; MDS is generated by the emulator, and selects EMU0 (Emulation 0, emulation pin 0) or EMU1 ((Emulation 1) of the JTAG emulator , the emulation pin 1) pin is used as the output pin of the MDS signal. The debugging support module is connected with all the IP cores in the chip, and it transmits the test signals TDI, TMS, TCK and TRST signals input from the emulator to an on-chip The corresponding TDI, TMS, TCK and TRST ports of each TAP, the data output by the TDO port of the TAP is delivered to the debugging host through the TDO pin through the JTAG emulator, so as to realize the JTAG debugging of a certain IP core in the multi-core chip.

The debugging support module is composed of a chain selection instruction register, a decoder, a first multiplexer and a second multiplexer. TCK and TRST of the JTAG emulator are connected with the TAP controller of each IP core through the debugging support module. The length of the chain selection instruction register is k( $k=\left\{\begin{array}{c}\left[{\mathrm{<figure-callout\; id="2"\; label="log"\; filenames="H200810143445XE00012.png"\; state="\{\{state\}\}">log</figure-callout>}}_2\mathrm{no}\right]+1(k\&NotEqual;2^{\mathrm{no}})\\ {\mathrm{<figure-callout\; id="2"\; label="log"\; filenames="H200810143445XE00012.png"\; state="\{\{state\}\}">log</figure-callout>}}_2\mathrm{no}(k=2^{\mathrm{no}})\end{array}\right.,$ n is the number of IP cores integrated in the multi-core chip), its input terminal is connected to the TDI and EMU0 (or EMU1) pins of the JTAG emulator, TDI and MDS are obtained from the JTAG emulator, and its output terminal is connected to the decoding When MDS is low level and keeps k TCK clocks, the serial input TDI is shifted into the chain selection instruction register bit by bit, and MDS changes from low level to high level on the rising edge of the k+1 TCK clock , at this moment, the chain selection instruction register transmits the k-bit binary code obtained from TDI as the chain selection instruction code to the decoder; the input terminal of the decoder is connected with the EMU0 (or EMU1) pin and the chain selection instruction register, and the output terminal Connected with the first multiplexer and the second multiplexer, when MDS is high level, the decoder decodes the chain selection instruction code input from the chain selection instruction register into the identification number of a certain IP core (ie IP The serial number of the core), and the decoding result is sent to the first multiplexer and the second multiplexer; the input of the first multiplexer is connected with TDI and TMS of the JTAG emulator, and is connected with the decoding Connected to the output of the device, the output is connected to the TDI and TMS of all TAPs of the IP core, it obtains TDI and TMS from the JTAG emulator, obtains the decoding result from the decoder, and sends TDI and TMS to a certain TDI and TMS of each IP core TAP; the input end of the second multiplexer is connected with the TDO of all IP core TAPs, and is connected with the output end of the decoder again, and its output end is connected with the TDO of JTAG emulator, according to The decoding result sends the TDO from an IP core to the TDO pin of the JTAG emulator.

The second step is to integrate the original single IP core debugging software into multi-core chip debugging software, and add a chain selection command in the multi-core chip debugging software. The chain selection command format is: intSelectIP(int IpNum), the function is to Sent to the emulator, the parameter IpNum is the identification number of each IP core. When IpNum is j, it means that the jth (1≤j≤n) IP core is selected for debugging.

位、计数单位为k的计数器Counter，将Counter初值置为k，JTAG仿真器接收到调试主机发送的链选命令后，Counter在TCK时钟控制下开始计数，将EMU0(或EMU1)引脚的输出置为低电平，同时将从调试主机传来的IpNum从仿真器TDI引脚串行输出；Counter的值减到0时，将EMU0(或EMU1)引脚的输出置为高电平。这样在JTAG仿真器的可编程逻辑中就生成了k个TCK周期低电平的MDS信号。In the third step, the JTAG emulator keeps the MDS signal of k low-level TCK clocks. The method is: define a length of p in the programmable logic of the JTAG emulator

Bit, counting unit is the counter Counter of k, the initial value of Counter is set to k, after the JTAG emulator receives the link selection command sent by the debugging host, the Counter starts counting under the control of the TCK clock, and the EMU0 (or EMU1) pin The output is set to low level, and the IpNum transmitted from the debugging host is serially output from the TDI pin of the emulator; when the value of Counter is reduced to 0, the output of the EMU0 (or EMU1) pin is set to high level. In this way, in the programmable logic of the JTAG emulator, low-level MDS signals of k TCK cycles are generated.

The fourth step is to use the debugging support module to debug the multi-core microprocessor, the method is:

Step 1, the debugging host executes the chain selection command, and sends the parameter IpNum to the JTAG emulator.

Step 2, after the JTAG emulator receives the IpNum, it generates an MDS signal that keeps k TCK clock low levels, and outputs it to the multi-core debug selection pin of the debug support module from the EMU0 (or EMU1) pin of the emulator, and simultaneously sets the IpNum Bit by bit output to the TDI pin of the JTAG debug interface.

Step 3, when MDS is low level (the first k TCK clocks), TDI is serially shifted into the chain selection instruction register of the debugging support module, when MDS changes from low level to high level (the k+1th TCK clock) , the decoder starts decoding.

Step 4, according to the difference of IpNum, the decoder decodes the chain selection instruction code into the identification number of the jth IP core, and the TDI and TMS obtained from the JTAG emulator will be obtained by the first multiplexer after receiving the decoding result TDI _j and TMS _j of the TAP transmitted to the jth IP core, the second multiplexer receives the decoding result and transmits the output TDO _j of the IP core TAP to the TDO of the chip debugging interface and then delivered by the emulator Debugging host, the debugging host invokes the original single IP core debugging software of IP _j integrated in the multi-core chip debugging software to debug IP _j .

Adopt the present invention can obtain following technical effect:

1. Adopt the developer of the present invention to debug the core of a plurality of discrete states in the multi-core chip via a JTAG debugging interface, it has avoided the bit shift that encounters in the daisy chain method and changes with the number of integrated cores, Therefore, it has higher performance in multi-core chip structure.

2. Just add a simple chain selection command to the debugging software of the multi-core chip. After executing the chain selection command, call the original debugging software of the IP core integrated in the multi-core chip debugging software to control any IP core of the multi-core chip. Debugging, so the debugging software of the original IP core can be reused. On the host side, whether it is the on-chip debugging hardware or debugging software of the original IP core, good reusability can be obtained. In a multi-core chip, no matter what kind of structure of the IP core is integrated in the chip, the on-chip of these IP cores can be reused in the multi-core chip only by interconnecting the original debugging interface of these IP cores with the debugging support module. Debug hardware and legacy debug capabilities.

3. It is a highly extensible solution. Since the chain selection instruction register is k bits, it can support up to 2 ^k chain selection commands, so it can support debugging of up to 2 ^k cores.

Description of drawings

Fig. 1 is the connection schematic diagram of a plurality of TAPs when the background technology adopts the daisy chain method to debug the multi-core microprocessor;

Fig. 2 is the connection schematic diagram of a plurality of TAPs when multi-core microprocessor is debugged by adopting the method of adding TLM;

Fig. 3 is the interconnection structural diagram of debugging support module and each kernel TAP in chip of the present invention;

Fig. 4 is a diagram of the internal logic structure of the debugging support module of the present invention;

Fig. 5 is a timing diagram of the MDS signal required when the debugging support module of the present invention executes the chain selection command.

Detailed ways

Figure 1 is the connection diagram of n TAPs when debugging a multi-core microprocessor using the daisy chain connection method: the TDI of the TAP of IP ₁ is connected to the TDI of the off-chip JTAG debugging interface, and the TDO of the TAP of IP _i is connected to the IP _{i+ 1} (1≤i≤n-1) TDI of TAP, IP _n TDO of TAP is connected to TDO of off-chip JTAG debug interface. The TDI signal and TDO signal of each IP core TAP are connected into a serial chain, and the control signals TMS, TCK and TRST are shared by all TAPs, that is, TMS, TCK and TRST of the off-chip JTAG debugging interface and TMS and TCK of all TAPs Both are connected to TRST. This method is widely used in PCB board-level chip interconnection testing, and can also be used in a single chip to realize access to all embedded TAPs to realize debugging of each IP core of a multi-core microprocessor. But it is not compatible with the IEEE 1149.1 protocol, and the daisy chain connection makes the test access to a single TAP in n IP cores complicated.

FIG. 2 is a schematic diagram of connection of multiple TAPs when debugging a multi-core microprocessor by adding a TLM method. TLM is the only debug interface of the chip, its input is TDI, TMS, TCK and TRST, and its output is TDO. The 5-pin signals TDI, TMS, TCK, TRST and TDO of each IP core TAP are interconnected with the TLM, and the TLM is responsible for connecting the signal of the JTAG debugging interface to a specified TAP of the IP core to be tested. This method needs to add a selection signal SEL and an enable signal ENA for each TAP to be connected to the TLM, and determine which or which TAPs of the IP core are selected to be connected to the TAP interface of the chip through SEL and ENA. Therefore, this method must modify the TAP inside the IP core, and add SEL and ENA to the design of the TAP, which makes the hardware design complicated. Since the TLM can connect multiple IP core TAPs, and the modification of the TAP on the hardware makes the original IP core debugging software must be modified before it can be integrated into the multi-core chip debugging software, which makes the design of the debugging software complicated. Bad reusability.

Fig. 3 is a diagram of the interconnection structure between the debugging support module and each core TAP in the chip according to the present invention.

In addition to the five input pins of TDI, TMS, TCK, TRST, and TDO connected to the JTAG debug interface of the emulator, the debug support module also has a multi-core debug selection pin to accept the enable signal MDS of the chain selection command. MDS is controlled by Generated by the emulator, the EMU0 (or EMU1) pin of the JTAG emulator is the input pin of the MDS signal. The output TDI ₁ ~ TDI _n , TMS ₁ ~ TMS _n , TCK_N, TRST_N of the debugging support module are respectively connected with the TDI, TMS, TCK, TRST of the TAP of IP ₁ ~ IP _n (that is, the TDI, TMS, TCK of the TAP of IP _j , TRST are input signals TDI _j , TMS _j , TCK_N, TRST_N respectively), the debugging support module transmits the test signals TDI, TMS, TCK and TRST signals of the emulator to the TAP corresponding TDI of a certain IP core to be debugged in the chip , TMS, TCK and TRST ports; the debugging support module also has n inputs TDO ₁ ~ TDO _n , which are respectively connected to the TAP output signal TDO of IP ₁ ~ IP _n , and the data output by the TAP of the IP core to be debugged is passed through TDO The pins are sent to the debug host via the JTAG emulator. The input TDI, TMS, TCK, TRST, MDS and output TDO of the debugging support module are connected to the off-chip as the unified JTAG interface of the whole chip, and each IP core on the multi-core chip is implemented through a chip-level TAP controller channel such as the debugging support module. JTAG debugging.

Fig. 4 is a logical structure diagram of the debugging support module of the present invention. The debugging support module is composed of a chain selection instruction register, a decoder, a first multiplexer and a second multiplexer. The input end of the chain selection instruction register is connected with TDI and EMU0 (or EMU1) of the JTAG emulator, TDI and MDS are obtained from the emulator, the output end is connected with the decoder, and the chain selection instruction code is sent to the decoder; decoding The input end of the device is connected with EMU0 (or EMU1) and the chain selection instruction register, and the output end is connected with the first multiplexer and the second multiplexer; the input end of the second multiplexer is connected with all IP cores respectively The TDO of TAP is connected to the output terminal of the decoder, and its output terminal is connected to the TDO of the JTAG emulator. Under the control of the decoding result, it selects the TDO of an IP core TAP and sends it to the TDO pin of the emulator. When the MDS signal is at low level, the chain selection instruction register in the debugging support module is enabled, and TDI is serially shifted into the chain selection instruction register. After the MDS signal is maintained for k TCK clock cycles, it changes from low level to high level. At this time, the chain selection command register stores the chain selection command code. When the chain selection command is to select IP _j (1≤j≤n), the first multiplexer connects TDI to the test input signal TDI _j of IP _j , TMS is connected to the test input signal TMS _j of IP _j , and the second multiplexer The multiplexer connects the test output signal TDO _j of IP _j to the off-chip test output signal TDO. At this time, a path is formed between the JTAG debug interface (TDI, TMS, TCK, TRST, TDO) of the chip and the debug interface of IP _j (TDI _j , TMS _j , TCK_N, TRST_N, TDO _j ), and the on-chip The only external JTAG debugging interface is used for JTAG debugging of the integrated IP _j on-chip.

Fig. 5 is a timing diagram of the MDS signal required when the debugging support module executes the chain selection command: after the JTAG emulator receives the chain selection command request, it generates k MDS signals with a low level of the TCK clock, which is sent by the EMU0 (or The EMU1) pin is output to the multi-core debug selection pin of the debug support module, and the parameter IpNum is output to the TDI of the debug support module by the TDI pin of the JTAG emulator.

Claims (1)

1. a multi-core microprocessor JTAG debugging method is characterized in that comprising the following steps: The first step is to add a chip-level TAP controller in the multi-core microprocessor with n IP cores—the debugging support module DSM as the debugging interface of the entire multi-core chip. Compatible JTAG interface, in addition to the five pins TDI, TMS, TCK, TRST, TDO connected to the JTAG debugging interface of the emulator, a multi-core debugging selection pin is added to accept the enable signal MDS of the chain selection command, MDS Generated by the emulator, select the emulation pin 0 of the JTAG emulator, that is, EMU0 or the emulation pin 1, that is, EMU1, as the output pin of the MDS signal; the debugging support module is connected to all IP cores in the chip, and it will be input from the emulator The test signals TDI, TMS, TCK and TRST signals are transmitted to the corresponding TDI, TMS, TCK and TRST ports of a certain TAP in the chip, and the data output by the TDO port of the TAP is sent to the debugging host through the JTAG emulator through the TDO pin ;The debugging support module is composed of chain selection instruction register, decoder, first multiplexer and second multiplexer; TCK and TRST of the JTAG emulator are connected to the TAP controller of each IP core through the debugging support module ;The length of the chain selection instruction register is k bits,

Its input terminal is connected to the TDI and EMU0 or EMU1 pins of the JTAG emulator, TDI and MDS are obtained from the JTAG emulator, and its output terminal is connected to the decoder. When MDS is low and keeps k TCK clocks, the serial The TDI input by the row is shifted into the chain selection instruction register bit by bit, and the MDS changes from low level to high level on the rising edge of the k+1 TCK clock. At this time, the chain selection instruction register uses the k-bit binary code obtained from TDI as The chain selection instruction code is sent to the decoder; the input end of the decoder is connected with the EMU0 or EMU1 pin and the chain selection instruction register, the output end is connected with the first multiplexer and the second multiplexer, MDS is high When the level is high, the decoder decodes the chain selection instruction code input from the chain selection instruction register into an identification number of a certain IP core, and transmits the decoding result to the first multiplexer and the second multiplexer; The input end of the first multiplexer is connected with TDI and TMS of the JTAG emulator, and is connected with the output end of the decoder, and the output end is connected with TDI and TMS of TAP of all IP cores, and it is obtained from the JTAG emulator TDI and TMS, obtain the decoding result from the decoder, and send TDI and TMS to the TDI and TMS of a certain IP core TAP according to the decoding result; the input terminal of the second multiplexer is connected to the TDO of all IP core TAPs It is connected to the output terminal of the decoder, and its output terminal is connected to the TDO of the JTAG emulator, and the TDO from a certain IP core is sent to the TDO pin of the JTAG emulator according to the decoding result; The second step is to integrate the original single IP core debugging software into multi-core chip debugging software, and add a chain selection command in the multi-core chip debugging software. The chain selection command format is: int SelectIP(intIpNum), the function is Send to the emulator, the parameter IpNum is the identification number of each IP core, when IpNum is j, it means that the jth IP core is selected for debugging, 1≤j≤n; In the third step, the MDS signals of k TCK clock low levels are maintained by the JTAG emulator. The method is: in the programmable logic of the JTAG emulator, define a counter Counter with a length of p bits and a counting unit of k. Set the initial value of Counter to k, and after the JTAG emulator receives the chain selection command sent by the debugging host, the Counter starts counting under the control of the TCK clock, and sets the output of the EMU0 or EMU1 pin to low level, and at the same time the slave debugging The IpNum from the host is serially output from the TDI pin of the emulator; when the value of the Counter is reduced to 0, the output of the EMU0 or EMU1 pin is set to a high level, so that it is generated in the programmable logic of the JTAG emulator The low-level MDS signal of k TCK cycles; The fourth step is to use the debugging support module to debug the multi-core microprocessor, the method is: Step 1, the debugging host executes the chain selection command, and sends the parameter IpNum to the JTAG emulator; Step 2, after the JTAG emulator receives the IpNum, generate the MDS signal that keeps k TCK clock low levels, output to the multi-core debugging selection pin of the debug support module by the EMU0 or EMU1 pin of the emulator, and simultaneously set the IpNum one by one bit output to the TDI pin of the JTAG debug interface; Step 3, when MDS is at low level, TDI is serially shifted into the chain selection instruction register of the debugging support module, and when MDS is changed from low level to high level, the decoder starts to decode; Step 4, according to the difference of IpNum, the decoder decodes the chain selection instruction code into the identification number of the jth IP core, and the TDI and TMS obtained from the JTAG emulator will be obtained by the first multiplexer after receiving the decoding result TDI _j and TMS _j of the TAP transmitted to the jth IP core, the second multiplexer receives the decoding result and transmits the output TDO _j of the IP core TAP to the TDO of the chip debugging interface and then delivered by the emulator Debugging host, the debugging host invokes the original single IP core debugging software of IP _j integrated in the multi-core chip debugging software to debug IP _j .

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