CN114461142B - Method, system, device and medium for reading and writing Flash data - Google Patents

Abstract

The application discloses a method, system, device and medium for reading and writing Flash data. The CPLD is respectively connected to the main control chip and the Flash memory. After receiving the data sent by the Flash memory, the CPLD sends the data to the main control chip. The CPLD is used in When the main control chip reads and writes the data in the Flash memory, it is used as a monitoring device to judge whether the data in the main control chip and the Flash memory are synchronized. If it is judged that the data in the main control chip and the Flash memory are not Send a reset signal, and the CPLD realizes the monitoring when the main control chip reads and writes the Flash memory.

Description

A method, system, device and medium for reading and writing Flash data

technical field

The present application relates to the technical field of data reading, in particular to a method, system, device and medium for reading and writing Flash data.

Background technique

As an important part of information infrastructure, servers are playing an increasingly important role in the rapidly developing information society. The design of the server generally has a Flash memory for storing the running program. When the system is started, the main control chip loads the program in the Flash memory, so as to correctly configure the system and ensure the normal operation of the server. Currently, the main control chip is directly connected to the Flash memory. When the system starts, the main control chip directly starts to read the data in the Flash memory. After the reading is completed, it is loaded into the internal register, configures the register, and runs the program. .

The process of the main control chip reading the data in the Flash memory is uncontrollable. If there is a loading failure during the data loading process, effective positioning analysis cannot be performed. The hardware circuit design of the Flash memory cannot make the Flash memory follow the system. Together with the reset, there is a conflict between the address mode of the main control chip and the address mode of the Flash memory after the reset, causing data in the Flash memory to be damaged and erased.

It can be seen that how to strengthen the monitoring of the read and write actions of the flash memory by the main control chip is a technical problem to be solved urgently by those skilled in the art.

Contents of the invention

The purpose of this application is to provide a method, system, device and medium for reading and writing Flash data.

In order to solve the above-mentioned technical problems, the application provides a method for reading and writing Flash data, which is applied to a CPLD, and the CPLD is respectively connected with a main control chip and a Flash memory, and the method includes:

Receive data sent by the Flash memory;

Sending the data to the main control chip and storing the data to the UFM register of the CPLD;

Judging whether the main control chip is synchronized with the data in the Flash memory;

If not, send a reset signal to the main control chip and the Flash memory, where the reset signal is used to control the main control chip and the Flash memory to reset simultaneously.

Preferably, in the described Flash data reading and writing method, after the described data is stored in the UFM register, it also includes:

When the main control chip restarts or fails to load the data, send a reset signal to the main control chip and the Flash memory.

Preferably, in the described Flash data reading and writing method, after the described data is stored in the UFM register, it also includes:

When receiving the signal sent by the BMC that the data in the Flash memory is inconsistent with the data in the UFM register, send a reset signal to the main control chip and the Flash memory.

Preferably, in the described Flash data reading and writing method, after the described data is sent to the main control chip, it also includes:

When the main control chip fails to read the data, store the current data.

The application also provides a Flash data reading and writing system, including:

Main control chip, CPLD, Flash memory;

Described CPLD comprises UFM register;

The main control chip is connected to the CPLD, and the CPLD is connected to the Flash memory,

The CPLD is used to receive the data sent by the Flash memory, and send the data to the main control chip and store the data to the UFM register; the CPLD is also used as the main control chip When the data in the Flash memory is not synchronized, a reset signal is sent to the main control chip and the Flash memory, and the reset signal is used to control the main control chip and the Flash memory to reset simultaneously.

Preferably, in the described Flash data reading and writing system, also include: BMC;

The BMC is connected with the CPLD and the Flash memory, and the BMC is used to check whether the data in the Flash memory and the UFM register are consistent.

Preferably, in the described Flash data reading and writing system, the main control chip is connected to the CPLD through the SPI bus, the CPLD is connected to the Flash memory through the SPI bus, and the CPLD is connected to the BMC through the IIC bus connection.

The application also provides a Flash data reading and writing device, which is applied to CPLD, and the CPLD is respectively connected with the main control chip and the Flash memory, and the device includes:

A receiving module, configured to receive data sent by the Flash memory;

A storage module, configured to send the data to the main control chip and store the data to the UFM register of the CPLD;

The judging module is used to judge whether the main control chip is synchronized with the data in the Flash memory; if not, trigger the reset module.

The reset module is configured to send a reset signal to the main control chip and the Flash memory, and the reset signal is used to control the main control chip and the Flash memory to reset simultaneously.

A sending module, configured to send a reset signal to the main control chip and the Flash memory when the main control chip restarts or fails to load the data.

The receiving control module is configured to send a reset signal to the main control chip and the Flash memory when receiving the signal sent by the BMC that the data in the Flash memory is inconsistent with the data in the UFM register.

The error storage module is used to store the current data when the main control chip fails to read the data.

The application also provides a Flash data reading and writing device, including:

memory for storing computer programs;

The processor is configured to implement the steps of the method for reading and writing Flash data when executing the computer program.

The present application also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method for reading and writing Flash data are realized.

The method for reading and writing Flash data provided by this application is applied to a complex programmable logic device (Complex Programmable Logic Device) CPLD. The CPLD is connected to the main control chip and the Flash memory respectively. After receiving the data sent by the Flash memory, the CPLD sends the data to the main control chip, and store the data in the UFM register of the CPLD; the CPLD judges whether the data in the main control chip and the Flash memory are synchronized; if not, sends a reset signal to the main control chip and the Flash memory. The CPLD is used as a monitoring device when the main control chip reads and writes data in the Flash memory, and judges whether the data in the main control chip and the Flash memory are synchronized. If it is judged that the data in the main control chip and the Flash memory are not The chip and the Flash memory send a reset signal, and the CPLD realizes the monitoring when the main control chip reads and writes the Flash memory.

In addition, the present application also provides a Flash data reading and writing system, a device and a computer-readable storage medium, corresponding to the above method, and the effect is the same as above.

Description of drawings

In order to illustrate the embodiments of the present application more clearly, the following will briefly introduce the accompanying drawings used in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. As far as people are concerned, other drawings can also be obtained based on these drawings on the premise of not paying creative work.

Fig. 1 is the flowchart of a kind of Flash data reading and writing method that the embodiment of the present application provides;

Fig. 2 is the structural diagram of a kind of Flash data reading and writing system that the embodiment of the application provides;

Fig. 3 is the structural diagram of a kind of Flash data reading and writing device that the embodiment of the application provides;

FIG. 4 is a structural diagram of a Flash data reading and writing device provided by another embodiment of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of this application.

The core of the application is to provide a method for strengthening the monitoring and management of reading and writing data in the Flash memory.

In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the drawings and specific implementation methods.

Fig. 1 is the flow chart of a kind of Flash data reading and writing method that the embodiment of the present application provides, is applied to CPLD22, and described CPLD22 is connected with main control chip 21 and Flash memory 24 respectively, as shown in Figure 1, Flash data reading and writing method include:

S10: receiving the data sent by the Flash memory 24;

S11: sending data to the main control chip 21 and storing the data to the UFM register 23 of the CPLD22;

S12: judging whether the data in the main control chip 21 and the Flash memory 24 are synchronized;

S13: If not, send a reset signal to the main control chip 21 and the Flash memory 24, the reset signal is used to control the main control chip 21 and the Flash memory 24 to reset simultaneously.

The CPLD22 mentioned in this embodiment refers to a complex programmable logic device, which is composed of a fully programmable and/or array and a macro cell library. The AND/OR array is reprogrammable and capable of performing numerous logic functions. Macrocells are functional blocks that implement combinational or sequential logic, while also providing greater flexibility such as true-value or complement output and feedback in different paths. In addition, the CPLD22 includes a user storage space (User Flash Memory, UFM), and the data stored in the UFM register 23 still exists after the CPLD22 is powered off, and will not be cleared.

Flash memory 24, also known as flash memory, not only has electronic erasable and programmable performance, but also will not lose data due to power failure, and can read data quickly, and is used to store BIOS programs, BMC25 programs, etc. on the server. The main control chip 21 of the server reads the data stored in the Flash memory 24, and after the reading is completed, loads the data into the internal registers, configures the registers, and runs the program. In the process of the main control chip 21 reading data, if the main control chip 21 fails to read, or the main control chip 21 suddenly loses power, the main control chip 21 will be powered on again, but the Flash memory 24 will not follow the main control chip 21. Performing a reset will result in data asynchrony between the main control chip 21 and the Flash memory 24 .

The CPLD22 mentioned in step S10 receives the data sent by the Flash memory 24, and step S11 sends the data to the main control chip 21, so that the main control chip 21 reads and loads. In this process, the CPLD22 is only used as a main control chip 21 An intermediary in the process of reading the data of the Flash memory 24, the CPLD22 is serially connected on the connection line between the main control chip 21 and the Flash memory 24. In addition, in step S11, CPLD22 stores data to the UFM register 23 of CPLD22, which can also be regarded as when main control chip 21 reads the data of Flash memory 24, CPLD22 reads data on the communication bus between main control chip 21 and Flash memory 24 , and store the data into the UFM register 23. In addition, the data is stored in the UFM register 23. When the main control chip 21 fails to read the data, the reason for the failure of the main control chip 21 to load can be analyzed by loading the data stored in the CPLD22, so as to solve the error.

Step S12 judges whether the data in the main control chip 21 and the Flash memory 24 are synchronous, including judging the clock state of the data in the main control chip 21 and the Flash memory 24, whether the address state is synchronous, if the data in the main control chip 21 and the Flash memory 24 are not synchronous , the memory stored in the Flash memory 24 may be damaged because the main control chip 21 and the Flash memory 24 work in different address modes. Judging by step S12 whether the data in the main control chip 21 and the Flash memory 24 are synchronous, if not synchronous, step S13 sends a reset signal to the main control chip 21 and the Flash memory 24, and the reset signal is used to control the main control chip 21 and the Flash memory 24 simultaneously Carry out reset, main control chip 21 and Flash memory 24 carry out reset action simultaneously, have just guaranteed like this main control chip 21 and Flash memory 24 work under the same address mode, stopped the problem that Flash memory 24 content is damaged.

In addition, the present embodiment does not limit the connection mode between the main control chip 21 and the CPLD22, nor does it limit the connection mode between the CPLD22 and the Flash memory 24, it can be designed according to actual needs; in addition, the present embodiment does not limit the specific configuration of the main control chip 21. Type, such as CPU, MCU, PCH, MCH, etc.

Through the method provided by this embodiment, the CPLD22 is serially connected between the main control chip 21 and the Flash memory, and the CPLD22 receives the data sent by the Flash memory 24 and sends the data to the main control chip 21, and stores the data in the UFM register 23 of the CPLD22 ; CPLD22 judges whether the data in the main control chip 21 and the Flash memory 24 are synchronized; if not, send a reset signal to the main control chip 21 and the Flash memory 24. CPLD22 is used as monitoring device when main control chip 21 reads and writes the data in Flash memory 24, judges whether the data in main control chip 21 and Flash memory 24 are synchronous, if judge main control chip 21 and data in Flash memory 24 are out of sync, Send reset signal to main control chip 21 and Flash memory 24 simultaneously by CPLD22, like this has just guaranteed the data synchronization in main control chip 21 and Flash memory 24, realizes main control chip 21 when carrying out read-write action to Flash memory 24 by CPLD22 monitor.

According to the above-mentioned embodiment, when the main control chip 21 restarts due to power failure or other reasons, it is likely to cause the data in the main control chip 21 and the Flash memory 24 to be out of sync. Therefore, this embodiment provides a preferred solution. Step S11 will After the data is stored in the UFM register 23 , it also includes: sending a reset signal to the main control chip 21 and the Flash memory 24 when the main control chip 21 restarts or fails to load data.

When the CPLD22 detects that the main control chip 21 is powered off and restarts or fails to load data, it directly sends a reset signal to the main control chip 21 and the Flash memory 24. The reset signal is used to control the main control chip 21 and the Flash memory 24 to reset simultaneously, and the main control The chip 21 and the Flash memory 24 reset at the same time, which ensures that the main control chip 21 and the Flash memory 24 work in the same address mode, and prevents the problem that the content of the Flash memory 24 is damaged.

By the method provided by this embodiment, when the main control chip 21 restarts or fails to load data, a reset signal is sent to the main control chip 21 and the Flash memory 24, and the reset signal is sent to the main control chip 21 and the Flash memory 24 by the CPLD22 simultaneously, thus This ensures that the data in the main control chip 21 and the Flash memory 24 are synchronized, and the CPLD22 realizes the monitoring when the main control chip 21 reads and writes to the Flash memory 24 .

According to the foregoing embodiment, in order to ensure that the CPLD22 reads the data in the Flash memory 24 accurately, therefore, this embodiment provides a preferred solution, after step S11 stores the data to the UFM register 23, it also includes: when receiving the baseboard management controller ( When the Flash memory 24 sent by the Baseboard Management Controller (BMC25) is inconsistent with the data in the UFM register 23, a reset signal is sent to the main control chip 21 and the Flash memory 24.

The baseboard management controller BMC25 that present embodiment mentions is connected with CPLD22 and Flash memory 24, is used for monitoring whether the data information stored in CPLD22 is consistent with the data in Flash memory 24, checks the accuracy of data, and the staff can read through Take the test result of BMC25 to analyze the problems existing in the data communication between main control chip 21 and Flash memory 24 . When BMC25 detects that the data stored in the UFM register 23 of CPLD22 is inconsistent with the data in the Flash memory 24, the BMC25 sends a signal to the CPLD22, and the CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24, thus ensuring that the main control The data in the chip 21 and the Flash memory 24 are synchronized, and the CPLD22 realizes the monitoring when the main control chip 21 reads and writes the Flash memory 24 .

Through the method provided in this embodiment, the BMC25 is allowed to participate in the verification of data reading and writing, which improves the security and reliability of the data, and further improves the reliability of the overall system.

According to the above-mentioned embodiment, when the main control chip 21 reads the data in the Flash memory 24, it may fail to read. In order to analyze the reason why the main control chip 21 fails to read the data, so as to solve the problem, this embodiment provides a preferred The scheme, after step S11 sends the data to the main control chip 21, also includes:

When the main control chip 21 fails to read the data, the current data is stored.

When the main control chip 21 failed to read data, the main control chip 21 would lose this data, and provide CPLD22 to store this data, and the staff can analyze the reason for the failure of reading by checking the type of this data, so that Solve the problem.

The embodiment of the present application also provides a Flash data reading and writing system, and Fig. 2 is a structural diagram of a Flash data reading and writing system provided by the present application embodiment, as shown in Fig. 2 , including:

Main control chip 21, CPLD22, Flash memory 24;

CPLD22 includes UFM register 23;

Main control chip 21 is connected with CPLD22, and CPLD22 is connected with Flash memory 24,

CPLD22 is used for receiving the data that Flash memory 24 sends, and data is sent to main control chip 21 and data is stored in UFM register 23; The control chip 21 and the Flash memory 24 send a reset signal, and the reset signal is used to control the main control chip 21 and the Flash memory 24 to reset simultaneously.

CPLD22 stores data to the UFM register 23 of CPLD22, also can be regarded as when main control chip 21 reads the data of Flash memory 24, CPLD22 reads the data on the communication bus of main control chip 21 and Flash memory 24, and stores the data to UFM register 23. In addition, the data is stored in the UFM register 23. When the main control chip 21 fails to read the data, the reason for the failure of the main control chip 21 to load can be analyzed by loading the data stored in the CPLD22, so as to solve the error.

CPLD22 sends reset signal to main control chip 21 and Flash memory 24 when main control chip 21 and data in Flash memory 24 are out of sync, reset signal is used to control main control chip 21 and Flash memory 24 to reset simultaneously, main control chip 21 The reset action is performed simultaneously with the Flash memory 24, which ensures that the main control chip 21 and the Flash memory 24 work in the same address mode, and prevents the problem that the content of the Flash memory 24 is damaged.

Through the Flash data reading and writing system provided by this embodiment, the CPLD22 is serially connected between the main control chip 21 and the Flash memory, and the CPLD22 receives the data sent by the Flash memory 24 and sends the data to the main control chip 21, and stores the data in the CPLD22 UFM register 23; CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24 when the data in the main control chip 21 and the Flash memory 24 are not synchronized, and the reset signal is used to control the main control chip 21 and the Flash memory 24 to reset simultaneously , CPLD22 is used as monitoring device when main control chip 21 reads and writes the data in Flash memory 24, guarantees the data synchronization in main control chip 21 and Flash memory 24, realizes that main control chip 21 reads and writes Flash memory 24 by CPLD22 Monitoring during operation.

According to the foregoing embodiments, the present application also provides a preferred solution, the Flash data reading and writing system, which also includes: BMC25;

The BMC25 is connected with the CPLD22 and the Flash memory 24, and the BMC25 is used to check whether the data in the Flash memory 24 and the UFM register 23 are consistent.

The baseboard management controller BMC25 is connected with the CPLD22 and the Flash memory 24, and is used to monitor whether the data information stored in the CPLD22 is consistent with the data in the Flash memory 24, and check the accuracy of the data. The staff can analyze the results by reading the BMC25. Problems existing in the data communication between the main control chip 21 and the Flash memory 24 . When BMC25 detects that the data stored in the UFM register 23 of CPLD22 is inconsistent with the data in the Flash memory 24, the BMC25 sends a signal to the CPLD22, and the CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24, thus ensuring that the main control The data in the chip 21 and the Flash memory 24 are synchronized, and the CPLD22 realizes the monitoring when the main control chip 21 reads and writes the Flash memory 24 .

According to the foregoing embodiments, the present application also provides a preferred solution, a Flash data read-write system, the main control chip 21 and the CPLD22 are connected by a serial peripheral interface (Serial Peripheral Interface, SPI) bus, and the CPLD22 and the The Flash memory 24 is connected through the SPI bus, and the CPLD22 is connected with the BMC25 through an integrated circuit bus (Inter-Integrated Circuit, IIC) bus.

It should be noted that the SPI bus is a high-speed, full-duplex, synchronous communication bus that supports full-duplex communication, simple communication, and fast data transfer rates. The IIC bus is mainly used to connect the overall circuit. IIC is a multi-directional control bus, which means that multiple chips can be connected to the same bus structure, and each chip can be used as a control source for real-time data transmission. This approach simplifies the bus interface for signal transmission.

Realize the communication connection between CPLD22 and the main control chip 21 and Flash memory 24 through SPI bus, the communication is simple, the data transmission speed block; Realize the communication connection between CPLD22 and BMC25 through IIC bus, simple structure, low power consumption, anti-interference Strong, long transmission distance.

In the foregoing embodiments, the method for reading and writing Flash data is described in detail, and the present application also provides corresponding embodiments of a device for reading and writing Flash data. It should be noted that this application describes the embodiments of the device part from two perspectives, one is based on the perspective of functional modules, and the other is based on the perspective of hardware.

Fig. 3 is the structural diagram of the Flash data read-write device that the embodiment of the present application provides, as shown in Fig. 3, Flash data read-write device comprises:

Receiving module 31, for receiving the data that Flash memory 24 sends;

The storage module 32 is used to send data to the main control chip 21 and store the data to the UFM register 23 of the CPLD22;

The judgment module 33 is used to judge whether the data in the main control chip 21 and the Flash memory 24 are synchronized; if not, trigger the reset module 34 .

The reset module 34 is configured to send a reset signal to the main control chip 21 and the Flash memory 24, and the reset signal is used to control the main control chip 21 and the Flash memory 24 to reset simultaneously.

The Flash data reading and writing device is applied to CPLD22, and CPLD22 is connected with main control chip 21 and Flash memory 24 respectively, and receiving module 31 receives the data that Flash memory 24 sends, and storage module 32 sends data to main control chip 21 and stores data to CPLD22 UFM register 23, judging module 33 judges whether the data in main control chip 21 and Flash memory 24 are synchronized; If not, trigger reset module 34, send reset signal to main control chip 21 and Flash memory 24, reset signal is used for controlling The chip 21 and the Flash memory 24 are reset simultaneously.

The CPLD22 is serially connected between the main control chip 21 and the Flash memory, and is used as a monitoring device when the main control chip 21 reads and writes the data in the Flash memory 24 to judge whether the data in the main control chip 21 and the Flash memory 24 are synchronous. Data in the chip 21 and the Flash memory 24 are asynchronous, and the reset signal is sent to the main control chip 21 and the Flash memory 24 by the CPLD22 simultaneously, so that the data synchronization in the main control chip 21 and the Flash memory 24 has been guaranteed, and the main control chip is realized by the CPLD22 21 Monitoring when the Flash memory 24 is read and written.

The unit also includes:

The sending module is used to send a reset signal to the main control chip and the Flash memory when the main control chip restarts or fails to load data.

The receiving control module is used to send a reset signal to the main control chip and the Flash memory when receiving a signal that the Flash memory sent by the BMC is inconsistent with the data in the UFM register.

The error storage module is used to store the current data when the main control chip fails to read the data.

Since the embodiment of the device part corresponds to the embodiment of the method part, please refer to the description of the embodiment of the method part for the embodiment of the device part, and details will not be repeated here.

FIG. 4 is a structural diagram of a Flash data read-write device provided by another embodiment of the present application. As shown in FIG. 4, the Flash data read-write device includes: a memory 40 for storing computer programs;

The processor 41 is configured to implement the steps of the method for reading and writing Flash data in the above-mentioned embodiment when executing the computer program.

The Flash data reading and writing device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer or a desktop computer, and the like.

Wherein, the processor 41 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 41 can be realized by using at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field-programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable LogicArray, PLA) . The processor 41 may also include a main processor and a coprocessor, the main processor is a processor for processing data in the wake-up state, and is also called a central processing unit (Central Processing Unit, CPU); Low-power processor for processing data in standby state. In some embodiments, the processor 41 may be integrated with a graphics processor (Graphics Processing Unit, GPU), and the GPU is used for rendering and drawing the content that needs to be displayed on the display screen. In some embodiments, the processor 41 may also include an artificial intelligence (AI) processor, and the AI processor is used to process calculation operations related to machine learning.

Memory 40 may include one or more computer-readable storage media, which may be non-transitory. The memory 40 may also include high-speed random access memory, and non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 40 is at least used to store the following computer program 401, wherein, after the computer program is loaded and executed by the processor 41, the relevant steps of the method for reading and writing Flash data disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory 40 may also include an operating system 402 and data 403, etc., and the storage method may be temporary storage or permanent storage. Wherein, the operating system 402 may include Windows, Unix, Linux and so on. The data 403 may include, but is not limited to, the steps involved in implementing the method for reading and writing Flash data.

In some embodiments, the Flash data reading and writing device may further include a display screen 42 , an input and output interface 43 , a communication interface 44 , a power supply 45 and a communication bus 46 .

Those skilled in the art can understand that the structure shown in FIG. 4 does not constitute a limitation on the Flash data reading and writing device, and may include more or less components than those shown in the figure.

The Flash data read-write device that the embodiment of the present application provides, comprises memory and processor, and processor can realize following method when executing the program stored in memory: Flash data read-write method, CPLD22 is used for reading and writing Flash at main control chip 21 When the data in the memory 24 is used as a monitoring device, it is judged whether the data in the main control chip 21 and the Flash memory 24 are synchronous; 24 sends a reset signal, so that the data synchronization in the main control chip 21 and the Flash memory 24 is guaranteed, and the monitoring when the main control chip 21 performs read and write actions to the Flash memory 24 is realized by the CPLD22.

Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the steps described in the above-mentioned embodiment of the Flash data reading and writing method are implemented.

It can be understood that if the methods in the above embodiments are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , executing all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, and various media capable of storing program codes.

The computer-readable storage medium provided by the present embodiment stores a computer program on it, and when the processor executes the program, the following methods can be realized: the Flash data reading and writing method, and the CPLD22 is used to read and write the Flash memory 24 at the main control chip 21 When the data in the data is used as a monitoring device, it is judged whether the data in the main control chip 21 and the Flash memory 24 are synchronous. If it is judged that the data in the main control chip 21 and the Flash memory 24 are out of sync, the CPLD22 sends the data to the main control chip 21 and the Flash memory 24 simultaneously. reset signal, thus ensuring the data synchronization between the main control chip 21 and the Flash memory 24, and the monitoring when the main control chip 21 performs read and write actions to the Flash memory 24 by the CPLD22.

The Flash data reading and writing method, Flash data reading and writing system, device and medium provided by this application have been introduced in detail above. Each embodiment in the description is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for relevant details, please refer to the description of the method part. It should be pointed out that those skilled in the art can make some improvements and modifications to the application without departing from the principles of the application, and these improvements and modifications also fall within the protection scope of the claims of the application.

It should also be noted that in this specification, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations There is no such actual relationship or order between the operations. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Claims (10)

1. a Flash data reading and writing method, is characterized in that, is applied to CPLD, and described CPLD is connected with main control chip and Flash memory respectively, and described method comprises: Receive data sent by the Flash memory; Sending the data to the main control chip and storing the data to the UFM register of the CPLD; Judging whether the main control chip is synchronized with the data in the Flash memory; If not, send a reset signal to the main control chip and the Flash memory, where the reset signal is used to control the main control chip and the Flash memory to reset simultaneously. 2. Flash data reading and writing method according to claim 1, is characterized in that, described data is stored after the UFM register of described CPLD, also comprises: When the main control chip restarts or fails to load the data, send a reset signal to the main control chip and the Flash memory. 3. Flash data reading and writing method according to claim 1, is characterized in that, described data is stored after the UFM register of described CPLD, also comprises: When receiving the signal that the data in the Flash memory sent by the BMC is inconsistent with the data in the UFM register, send a reset signal to the main control chip and the Flash memory; The BMC is connected with the CPLD and the Flash memory, and the BMC is used to check whether the data in the Flash memory and the UFM register are consistent. 4. Flash data reading and writing method according to claim 1, is characterized in that, after described described data is sent to described main control chip, also comprise: When the main control chip fails to read the data, store the current data. 5. A Flash data read-write system is characterized in that, comprising: Main control chip, CPLD, Flash memory; Described CPLD comprises UFM register; The main control chip is connected to the CPLD, and the CPLD is connected to the Flash memory, The CPLD is used to receive the data sent by the Flash memory, and send the data to the main control chip and store the data to the UFM register of the CPLD; the CPLD is also used when the main When the control chip and the data in the Flash memory are not synchronized, a reset signal is sent to the main control chip and the Flash memory, and the reset signal is used to control the main control chip and the Flash memory to reset simultaneously. 6. The Flash data reading and writing system according to claim 5, further comprising: BMC; The BMC is connected with the CPLD and the Flash memory, and the BMC is used to check whether the data in the Flash memory and the UFM register are consistent. 7. Flash data reading and writing system according to claim 6, is characterized in that, described main control chip and described CPLD are connected by SPI bus, and described CPLD and described Flash memory are connected by described SPI bus, and described The CPLD is connected with the BMC through the IIC bus. 8. A Flash data read-write device, is characterized in that, is applied to CPLD, and described CPLD is connected with main control chip and Flash memory respectively, and described device comprises: A receiving module, configured to receive data sent by the Flash memory; A storage module, configured to send the data to the main control chip and store the data to the UFM register of the CPLD; Judging module, used to judge whether the data in the main control chip and the Flash memory are synchronized; if not, trigger the reset module; The reset module is configured to send a reset signal to the main control chip and the Flash memory, and the reset signal is used to control the main control chip and the Flash memory to reset simultaneously. 9. A Flash data read-write device, characterized in that, comprising: memory for storing computer programs; The processor is configured to implement the steps of the method for reading and writing Flash data according to any one of claims 1 to 4 when executing the computer program. 10. A computer-readable storage medium, characterized in that, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the Flash memory according to any one of claims 1 to 4 is realized. The steps of the data read and write methods.