CN114285300B - Power supplies that eliminate ringing - Google Patents

Abstract

A power supply capable of eliminating ringing effects, comprising: a bridge rectifier, a first transformer, a second transformer, a third transformer, a power switch, a delay and stabilization circuit, an output stage circuit, and a controller. The bridge rectifier can generate a rectification potential according to a first input potential and a second input potential. The first transformer can generate an induction potential according to the rectification potential, wherein an excitation inductor is built in the first transformer. The power switch has a parasitic capacitor built in. The second transformer generates a control potential according to a resonance potential between the exciting inductor and the parasitic capacitor. The output stage circuit comprises a plurality of discharge paths and can generate an output potential, wherein the discharge paths are selectively enabled or disabled according to the control potential.

Description

Power supplies that eliminate ringing

technical field

The invention relates to a power supply, in particular to a power supply capable of eliminating the ringing effect.

Background technique

In a traditional power supply, the non-ideal parasitic capacitance of the power switch often produces a ringing effect, which not only causes a large switching loss, but also reduces the overall conversion efficiency of the power supply. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the existing technologies.

Contents of the invention

In a preferred embodiment, the present invention proposes a power supply for eliminating the ringing effect, comprising: a bridge rectifier, which generates a rectified potential according to a first input potential and a second input potential; a first transformer, It includes a first primary coil and a first secondary coil, wherein the first transformer has a built-in excitation inductor, the first primary coil is used to receive the rectified potential, and the first secondary coil is used to generate an induction potential; a power switcher selectively couples the first main coil to the ground according to a clock potential, wherein the power switcher has a built-in parasitic capacitor; a delay and stabilization circuit; a second transformer including a a second primary coil and a second secondary coil, wherein the second primary coil is used to receive a resonance potential between the magnetizing inductor and the parasitic capacitor, and the second secondary coil is used to generate a control potential; An output stage circuit, including a plurality of discharge paths, wherein the output stage circuit generates an output potential and a feedback potential according to the induction potential and the control potential, and the plurality of discharge paths are selectively selected according to the control potential ground enable or disable; a third transformer, including a third primary coil and a third secondary coil, wherein the third primary coil is used to receive the feedback potential, and the third secondary coil is coupled to the delay and a stabilization circuit; and a controller generating the clock potential, wherein the clock potential is transmitted to the power switch through the delay and stabilization circuit.

Description of drawings

FIG. 1 is a schematic diagram showing a power supply according to an embodiment of the invention.

FIG. 2 is a schematic diagram showing a power supply according to an embodiment of the invention.

FIG. 3 is a potential waveform diagram showing a conventional power supply.

FIG. 4 is a diagram showing potential waveforms of the power supply according to an embodiment of the invention.

Explanation of reference signs:

100, 200: power supply

110, 210: bridge rectifier

120, 220: the first transformer

121, 221: the first main coil

122, 222: the first secondary coil

130, 230: power switcher

140, 240: delay and stabilization circuit

150, 250: second transformer

151, 251: Second main coil

152, 252: the second secondary coil

160, 260: output stage circuit

161, 162: discharge path

170, 270: The third transformer

171, 271: the third main coil

172, 272: the third secondary coil

180, 280: Controller

190, 290: Earth

310: first dotted frame

410: Second dotted frame

C1: first capacitor

C2: second capacitor

CP: Parasitic capacitor

D1: first diode

D2: second diode

D3: third diode

D4: fourth diode

D5: fifth diode

D6: sixth diode

D7: seventh diode

DZ: Zener diode

IM: Inductor current

L1: Inductor

LM: Magnetizing inductor

M1: first transistor

M2: second transistor

M3: third transistor

N1: the first node

N2: second node

N3: the third node

N4: the fourth node

N5: fifth node

N6: sixth node

N7: seventh node

N8: eighth node

N9: ninth node

N10: tenth node

NIN1: first input node

NIN2: second input node

NOUT: output node

R1: first resistor

R2: second resistor

TD: set time

VA: clock potential

VC: control potential

VF: feedback potential

VIN1: the first input potential

VIN2: second input potential

VN: resonance potential

VOUT: output potential

VR: rectified potential

VS: Induction potential

VSS: ground potential

Detailed ways

In order to make the purpose, features and advantages of the present invention more comprehensible, the specific embodiments of the present invention are listed below, together with the accompanying drawings, which are described in detail as follows.

Certain terms are used in the description and claims to refer to particular elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. The words "comprising" and "comprising" mentioned throughout the specification and claims are open-ended terms, so they should be interpreted as "including but not limited to". The term "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if it is described that a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. Two devices.

FIG. 1 is a schematic diagram showing a power supply 100 according to an embodiment of the invention. For example, the power supply 100 can be applied to a desktop computer, a notebook computer, or an all-in-one computer. As shown in Figure 1, the power supply 100 includes: a bridge rectifier 110, a first transformer 120, a power switch 130, a delay and stabilization circuit 140, a second transformer 150, an output stage circuit 160, a The third transformer 170, and a controller 180. It should be noted that, although not shown in FIG. 1 , the power supply 100 may also include other components, such as a voltage regulator and/or a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2 . Both the first input potential VIN1 and the second input potential VIN2 can come from an external input power source, wherein an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2 . For example, the frequency of the AC voltage can be about 50 Hz or 60 Hz, and the root mean square value of the AC voltage can be about 90V to 264V, but it is not limited thereto. The first transformer 120 includes a first primary coil 121 and a first secondary coil 122 , wherein the first transformer 120 may have a built-in magnetizing inductor LM. The magnetizing inductor LM can be an inherent component produced when the first transformer 120 is manufactured, and it is not an external independent component. Both the first primary winding 121 and the magnetizing inductor LM can be located on the same side of the first transformer 120 , while the first secondary winding 122 can be located on the opposite side of the first transformer 120 . The first primary coil 121 can receive the rectified potential VR, and in response to the rectified potential VR, the first secondary coil 122 can generate an induced potential VS. The power switch 130 can selectively couple the first main coil 121 and the magnetizing inductor LM to the ground 190 according to a clock potential VA. The ground 190 may refer to the earth, or any ground path coupled to the earth, which is not an internal component of the power supply 100 . For example, if the clock potential VA is a high logic level (that is, logic “1”), the power switch 130 is to couple both the first main coil 121 and the magnetizing inductor LM to the ground 190 (that is, the power switch 130 130 can be approximated as a short-circuit path); otherwise, if the clock potential VA is a low logic level (that is, logic “0”), the power switch 130 will not couple the first main coil 121 and the magnetizing inductor LM to ground 190 (ie, power switch 130 may approximate an open path). In addition, the power switch 130 may have a built-in parasitic capacitor CP. It must be understood that the total parasitic capacitance between the two terminals of the power switch 130 can be modeled as the aforementioned parasitic capacitor CP, which is not an external independent component. The delay and stabilization circuit 140 can be used to adjust and limit the clock potential VA. The second transformer 150 includes a second primary coil 151 and a second secondary coil 152, wherein the second primary coil 151 can be located at one side of the second transformer 150, and the second secondary coil 152 can be located at the opposite side of the second transformer 150 The other side. The second main coil 151 can receive a resonant potential VN between the magnetizing inductor LM and the parasitic capacitor CP, and in response to the resonant potential VN, the second secondary coil 152 can generate a control potential VC. The output stage circuit 160 includes a plurality of discharge paths 161 , 162 , the total number of which is not particularly limited in the present invention. The output stage circuit 160 can generate an output potential VOUT and a feedback potential VF according to the sensing potential VS and the control potential VC. For example, the output potential VOUT can be a DC potential, and its potential level can be from 18V to 22V, but it is not limited thereto. The aforementioned discharge paths 161 and 162 can be selectively enabled or disabled according to the control potential VC. The third transformer 170 includes a third primary coil 171 and a third secondary coil 172, wherein the third secondary coil 172 can be located on one side of the third transformer 170, and the third primary coil 171 can be located on the opposite side of the third transformer 170 The other side. The third primary coil 171 can receive the feedback potential VF, and the third secondary coil 172 is coupled to the delay and stabilization circuit 140 . That is, the delay and stabilization circuit 140 can be controlled according to the feedback potential VF. The controller 180 can generate a clock potential VA, wherein the clock potential VA is transmitted to the power switch 130 through the delay and stabilization circuit 140 . For example, the controller 180 can be a pulse width modulation integrated circuit, but it is not limited thereto. Under this design, once the ringing effect occurs between the magnetizing inductor LM of the first transformer 120 and the parasitic capacitor CP of the power switch 130, the output stage circuit 160 and the delay and stabilization circuit 140 can properly limit the resonance potential VN range, thus weakening this non-ideal characteristic. Therefore, the present invention can reduce the switching loss of the power switch 130 while improving the conversion efficiency of the power supply 100 .

The following embodiments will introduce the detailed structure and operation of the power supply 100 . It must be understood that these drawings and descriptions are only examples and not intended to limit the scope of the present invention.

FIG. 2 is a schematic diagram showing a power supply 200 according to an embodiment of the invention. 2, the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a first transformer 220, a power switch 230, a delay and stabilization circuit 240, a second transformer 250, an output stage circuit 260, a third transformer 270, and a controller 280. The first input node NIN1 and the second input node NIN2 of the power supply 200 can respectively receive a first input potential VIN1 and a second input potential VIN2 from an external input power source, wherein the first input potential VIN1 and the second input potential VIN2 An alternating voltage with any frequency and any amplitude can be formed between them. The output node NOUT of the power supply 200 can output an output voltage, an output potential VOUT, to an electronic device, wherein the output potential VOUT can be approximately a DC potential.

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The anode of the first diode D1 is coupled to the first input node NIN1 , and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The anode of the third diode D3 is coupled to the ground 290 , and the cathode of the third diode D3 is coupled to the first input node NIN1 . The ground 290 may refer to the earth, or any ground path coupled to the earth, which is not an internal component of the power supply 200 . The anode of the fourth diode D4 is coupled to the ground 290 , and the cathode of the fourth diode D4 is coupled to the second input node NIN2 .

The first transformer 220 includes a first primary coil 221 and a first secondary coil 222 , wherein the first transformer 220 may have a built-in magnetizing inductor LM. The magnetizing inductor LM can be an inherent component produced when the first transformer 220 is manufactured, and it is not an external independent component. Both the first main coil 221 and the magnetizing inductor LM can be located on the same side of the first transformer 220 , while the first secondary coil 222 can be located on the opposite side of the first transformer 220 . The first end of the first main coil 221 is coupled to the first node N1 to receive the rectified potential VR, and the second end of the first main coil 221 is coupled to a second node N2. The first terminal of the first secondary coil 222 is coupled to a third node N3 to output a sense potential VS, and the second terminal of the first secondary coil 222 is coupled to a ground potential VSS (for example: 0V). A first terminal of the magnetizing inductor LM is coupled to the first node N1, and a second terminal of the magnetizing inductor LM is coupled to the second node N2.

The power switch 230 includes a first transistor M1. The first transistor M1 can be an NMOS field effect transistor. The control terminal of the first transistor M1 is coupled to a fourth node N4 to receive a clock potential VA from the controller 280, the first terminal of the first transistor M1 is coupled to the ground 290, and the second terminal of the first transistor M1 coupled to the second node N2. The power switch 230 can have a built-in parasitic capacitor CP. In detail, the first end of the parasitic capacitor CP is coupled to the second node N2 , and the second end of the parasitic capacitor CP is coupled to the ground 290 . It must be understood that the total parasitic capacitance between the first terminal and the second terminal of the first transistor M1 can be modeled as the aforementioned parasitic capacitor CP, which is not an external independent component.

The controller 280 can output the clock potential VA at the fourth node N4 , and the clock potential VA can be used to adjust the duty cycle of the power switch 230 . For example, the clock potential VA can be maintained at a fixed potential when the power supply 200 is initialized, and a periodic clock waveform can be provided after the power supply 200 enters a normal use phase. It should be noted that the clock potential VA can also be adjusted and limited by the delay and stabilization circuit 240 .

The delay and stabilization circuit 240 includes a Zener diode DZ, a first capacitor C1, and a fifth diode D5. The anode of the Zener diode DZ is coupled to the ground 290, and the cathode of the Zener diode DZ is coupled to the fourth node N4. A first terminal of the first capacitor C1 is coupled to the second node N2, and a second terminal of the first capacitor C1 is coupled to the fourth node N4. The anode of the fifth diode D5 is coupled to a fifth node N5, and the cathode of the fifth diode D5 is coupled to the second node N2.

The second transformer 250 includes a second primary coil 251 and a second secondary coil 252, wherein the second primary coil 251 can be located on one side of the second transformer 250, and the second secondary coil 252 can be located on the opposite side of the second transformer 250 The other side. A first end of the second main coil 251 is coupled to the second node N2 to receive a resonant potential VN between the magnetizing inductor LM and the parasitic capacitor CP, and a second end of the second main coil 251 is coupled to the ground 290 . The first terminal of the second secondary coil 252 is coupled to a sixth node N6 to output a control potential VC, and the second terminal of the second secondary coil 252 is coupled to the ground potential VSS.

The output stage circuit 260 includes a second transistor M2, a third transistor M3, a sixth diode D6, a seventh diode D7, an inductor L1, a second capacitor C2, and a first resistor R1 , and a second resistor R2. The second transistor M2 and the third transistor M3 may each be an NMOS field effect transistor. The control terminal of the second transistor M2 is coupled to the sixth node N6 to receive the control potential VC, the first terminal of the second transistor M2 is coupled to the output node NOUT, and the second terminal of the second transistor M2 is coupled to the third node N3 to receive the induced potential VS. A first end of the first resistor R1 is coupled to the third node N3, and a second end of the first resistor R1 is coupled to a seventh node N7. A first terminal of the inductor L1 is coupled to the seventh node N7, and a second terminal of the inductor L1 is coupled to an eighth node N8. The control terminal of the third transistor M3 is coupled to the sixth node N6 to receive the control potential VC, the first terminal of the third transistor M3 is coupled to a ninth node N9, and the second terminal of the third transistor M3 is coupled to the first node N9. Eight nodes N8. The anode of the sixth diode D6 is coupled to the ninth node N9, and the cathode of the sixth diode D6 is coupled to the output node NOUT. A first terminal of the second capacitor C2 is coupled to the output node NOUT, and a second terminal of the second capacitor C2 is coupled to the ground potential VSS. A first end of the second resistor R2 is coupled to the eighth node N8, and a second end of the second resistor R2 is coupled to the ground potential VSS. The anode of the seventh diode D7 is coupled to the eighth node N8, and the cathode of the seventh diode D7 is coupled to a tenth node N10 to output a feedback potential VF.

The third transformer 270 includes a third primary coil 271 and a third secondary coil 272, wherein the third secondary coil 272 can be located on one side of the third transformer 270, and the third primary coil 271 can be located on the opposite side of the third transformer 270 The other side. A first end of the third main coil 271 is coupled to the tenth node N10 to receive the feedback potential VF, and a second end of the third main coil 271 is coupled to the ground potential VSS. A first terminal of the third secondary coil 272 is coupled to the fifth node N5 , and a second terminal of the third secondary coil 272 is coupled to the ground 290 . In some embodiments, the first transformer 220, the second transformer 250, and the third transformer 270 together form an integrated transformer, wherein the first primary winding 221, the third secondary winding 272, and the second primary winding 251 are all They can be located on the same side of the integrated transformer, while the first secondary winding 222 , the third primary winding 271 , and the second secondary winding 252 can all be located on the opposite side of the integrated transformer.

In some embodiments, the power supply 200 can operate in an initial mode, a first mode, a second mode, or a third mode, and the operating principles thereof will be described as follows.

In the initial mode, the power supply 200 has not received the first input potential VIN1 and the second input potential VIN2, wherein the first transistor M1, the second transistor M2, the third transistor M3, the fifth diode D5, the sixth and second Both the transistor D6 and the seventh diode D7 are disabled.

In the first mode, the power supply 200 has received the first input potential VIN1 and the second input potential VIN2, wherein the clock potential VA is at a high logic level and the first transistor M1 is enabled. At this time, the zener diode DZ collapses backwards to stabilize the clock potential VA, and an inductor current IM passing through the magnetizing inductor LM gradually increases. The second transistor M2, the third transistor M3, the fifth diode D5, the sixth diode D6, and the seventh diode D7 are all disabled.

In the second mode, the clock potential VA is at a low logic level and the first transistor M1 is disabled. At this time, the resonant potential VN at the second node N2 will be pulled up sharply instantaneously, so that the relatively high control potential VC enables the second transistor M2 and the second transistor M3 at the same time. The energy stored in the magnetizing inductor LM is indirectly released to the ground potential VSS by the three discharge paths of the output stage circuit 260 via the first transformer 220 . In detail, the second transistor M2 and the second capacitor C2 can jointly form a first discharge path; the first resistor R1, the inductor L1, and the second resistor R2 can jointly form a second discharge path; and the first The resistor R1, the inductor L1, the third transistor M3, the sixth diode D6, and the second capacitor C2 can jointly form a third discharge path. When the inductor current IM passing through the magnetizing inductor LM drops to zero (that is, the energy stored in the magnetizing inductor LM is completely released), the power supply 200 will switch from the second mode to the third mode.

In the third mode, the second transistor M2 and the third transistor M3 are switched from an enabled state to a disabled state, and the magnetizing inductor LM of the first transformer 220 starts to resonate with the parasitic capacitor CP of the power switch 230 . At this time, due to the cold second law, the magnetizing inductor LM without any inductive current IM will undergo a voltage reversal (that is, the potential at the eighth node N8 will become high), so that the seventh diode D7 is enabled and pulls Raise the feedback potential VF. By using the third transformer 270 and the delay and stabilization circuit 240, the relatively high feedback potential VF can adjust and limit the resonant potential VN while delaying the clock potential VA. Then, the power supply 200 will return to the first mode again.

FIG. 3 is a potential waveform diagram showing a conventional power supply, wherein the horizontal axis represents time, and the vertical axis represents potential levels. According to the measurement results of FIG. 3 , if the output stage circuit 260 and its discharge path are not used, a relatively large ringing effect will easily occur between the parasitic capacitor CP and the magnetizing inductor LM (as shown in a first dashed box 310 ).

FIG. 4 is a potential waveform diagram showing the power supply 200 according to an embodiment of the present invention, wherein the horizontal axis represents time, and the vertical axis represents potential levels. It must be noted that under the premise of using the output stage circuit 260 and its discharge path, the resonant potential VN between the magnetizing inductor LM and the parasitic capacitor CP will be limited to its first valley, and subsequent unnecessary up and down oscillation. Therefore, the ringing effect between the parasitic capacitor CP and the magnetizing inductor LM can be almost completely eliminated (as shown by a second dashed box 410 ). On the other hand, the first capacitor C1 can delay the clock potential VA for a predetermined time TD, so that the first transistor M1 can perform zero voltage switching (ZVS), which can reduce the switching loss of the power switch 230 . Under this design, the discharge time period of the output stage circuit 260 can be dynamically adjusted according to different requirements, and the conversion efficiency of the voltage converter 200 can be further improved no matter under the conditions of light load, heavy load, high voltage, or low voltage. .

In some embodiments, the component parameters of the power supply 200 may be as follows. The inductance of the magnetizing inductor LM can be between 328.5 μH to 401.5 μH, preferably 365 μH. The inductance of the inductor L1 can be between 24.7 μH to 28.6 μH, preferably 26 μH. The capacitance of the parasitic capacitor CP can be between 120pF and 180pF, preferably 150pF. The capacitance of the first capacitor C1 can be between 108pF and 132pF, preferably 120pF. The capacitance of the second capacitor C2 can be between 612 μF and 748 μF, preferably 680 μF. The resistance value of the first resistor R1 may be between 45.6KΩ to 50.4KΩ, preferably 48KΩ. The resistance value of the second resistor R2 can be between 11.4KΩ and 12.6KΩ, preferably 12KΩ. The turn ratio of the first primary coil 221 to the first secondary coil 222 can be between 1 and 100, preferably 10. The turn ratio of the second primary coil 251 to the second secondary coil 252 can be between 1 and 100, preferably 20. The turn ratio of the third primary coil 271 to the third secondary coil 272 may be between 0.1 and 10, preferably 1. The breakdown voltage of the Zener diode DZ is about 15V. The established time TD is about 10ns. The above parameter ranges are obtained according to the results of multiple experiments, which help to optimize the conversion efficiency of the power supply 200 .

The present invention proposes a novel power supply, which includes an output stage circuit and its discharge path to suppress the ringing effect. According to actual measurement results, using the power supply of the aforementioned design can almost completely eliminate the non-ideal characteristics between the transformer and the power switch. Since the invention can effectively improve the conversion efficiency of the power supply and reduce electromagnetic interference, it is very suitable for various electronic devices.

It should be noted that the potential, current, resistance value, inductance value, capacitance value, and other component parameters mentioned above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the states shown in FIGS. 1 to 4 . The invention may comprise only any one or more features of any one or more of the embodiments of FIGS. 1-4 . In other words, not all the illustrated features must be implemented in the power supply of the present invention at the same time. Although the embodiment of the present invention uses metal-oxide-semiconductor field-effect transistors as an example, the present invention is not limited thereto, and those skilled in the art can use other types of transistors, such as: junction field-effect transistors, or fin-type field effect transistors, etc., without affecting the effect of the present invention.

Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall prevail as defined by the appended claims.

Claims (7)

1. A power supply for eliminating ringing effects, comprising:

a bridge rectifier for generating a rectified potential according to a first input potential and a second input potential;

the first transformer comprises a first main coil and a first auxiliary coil, wherein an excitation inductor is built in the first transformer, the first main coil is used for receiving the rectification potential, and the first auxiliary coil is used for generating an induction potential;

a power switch selectively coupling the first primary winding to ground according to a time Zhong Dianwei, wherein the power switch has a parasitic capacitor built therein;

a delay and stabilization circuit;

a second transformer including a second primary winding for receiving a resonance potential between the excitation inductor and the parasitic capacitor and a second secondary winding for generating a control potential;

an output stage circuit including a plurality of discharge paths, wherein the output stage circuit generates an output potential and a feedback potential according to the sensing potential and the control potential, and the plurality of discharge paths are selectively enabled or disabled according to the control potential;

a third transformer including a third main winding for receiving the feedback potential and a third sub-winding coupled to the delay and stabilization circuit; and

a controller for generating the clock potential, wherein the clock potential is transmitted to the power switch via the delay and stabilization circuit,

wherein the bridge rectifier comprises:

a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential;

a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node;

a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground and the cathode of the third diode is coupled to the first input node; and

a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground and the cathode of the fourth diode is coupled to the second input node,

wherein the first main coil has a first end and a second end, the first end of the first main coil is coupled to the first node to receive the rectifying potential, the second end of the first main coil is coupled to a second node, the first sub-coil has a first end and a second end, the first end of the first sub-coil is coupled to a third node to output the sensing potential, the second end of the first sub-coil is coupled to a ground potential, the exciting inductor has a first end and a second end, the first end of the exciting inductor is coupled to the first node, and the second end of the exciting inductor is coupled to the second node,

wherein the power switch comprises:

a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is coupled to a fourth node to receive the clock potential from the controller, the first terminal of the first transistor is coupled to the ground, and the second terminal of the first transistor is coupled to the second node;

wherein the parasitic capacitor has a first end and a second end, the first end of the parasitic capacitor is coupled to the second node, and the second end of the parasitic capacitor is coupled to the ground,

wherein the delay and stabilization circuit comprises:

a zener diode having an anode and a cathode, wherein the anode of the zener diode is coupled to the ground and the cathode of the zener diode is coupled to the fourth node.

2. The power supply of claim 1, wherein the delay and stabilization circuit further comprises:

a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the second node, and the second end of the first capacitor is coupled to the fourth node; and

a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to a fifth node and the cathode of the fifth diode is coupled to the second node.

3. The power supply of claim 2, wherein the second primary winding has a first end and a second end, the first end of the second primary winding is coupled to the second node to receive the resonance potential, the second end of the second primary winding is coupled to the ground, the second secondary winding has a first end and a second end, the first end of the second secondary winding is coupled to a sixth node to output the control potential, and the second end of the second secondary winding is coupled to the ground potential.

4. The power supply of claim 3, wherein the output stage circuit comprises:

a second transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the second transistor is coupled to the sixth node to receive the control potential, the first terminal of the second transistor is coupled to an output node to output the output potential, and the second terminal of the second transistor is coupled to the third node to receive the sensing potential;

a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the third node, and the second end of the first resistor is coupled to a seventh node; and

an inductor having a first end and a second end, wherein the first end of the inductor is coupled to the seventh node and the second end of the inductor is coupled to an eighth node.

5. The power supply of claim 4, wherein the output stage circuit further comprises:

a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to the sixth node for receiving the control potential, the first terminal of the third transistor is coupled to a ninth node, and the second terminal of the third transistor is coupled to the eighth node;

a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the ninth node and the cathode of the sixth diode is coupled to the output node; and

a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the output node and the second end of the second capacitor is coupled to the ground potential.

6. The power supply of claim 5, wherein the output stage circuit further comprises:

a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the eighth node, and the second end of the second resistor is coupled to the ground potential; and

a seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the eighth node and the cathode of the seventh diode is coupled to a tenth node to output the feedback potential.

7. The power supply of claim 6, wherein the third main winding has a first end and a second end, the first end of the third main winding is coupled to the tenth node to receive the feedback potential, the second end of the third main winding is coupled to the ground potential, the third sub winding has a first end and a second end, the first end of the third sub winding is coupled to the fifth node, and the second end of the third sub winding is coupled to the ground;

when the energy stored in the exciting inductor is released, the output stage circuit adjusts and limits the resonance potential through the third transformer and the delay and stabilization circuit.