CN114285300A

CN114285300A - Power Supplies that Eliminate Ringing Effects

Info

Publication number: CN114285300A
Application number: CN202011042236.3A
Authority: CN
Inventors: 詹子增
Original assignee: Acer Inc
Current assignee: Acer Inc
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2022-04-05
Anticipated expiration: 2040-09-28
Also published as: CN114285300B

Abstract

A power supply capable of eliminating ringing effect, comprising: a bridge rectifier, a first transformer, a second transformer, a third transformer, a power switch, a delay and stabilization circuit, and an output stage circuit, and a controller. The bridge rectifier can generate a rectified potential according to a first input potential and a second input potential. The first transformer can generate an induced potential according to the rectified potential, wherein the first transformer has a built-in magnetizing inductor. A parasitic capacitor is built into the power switch. The second transformer can generate a control potential according to a resonant potential between the magnetizing inductor and the parasitic capacitor. The output stage circuit includes a plurality of discharge paths and can generate an output potential, wherein the discharge paths are selectively enabled or disabled according to the control potential.

Description

Power supply for eliminating ringing effect

Technical Field

The present invention relates to a power supply, and more particularly, to a power supply capable of eliminating ringing.

Background

In a conventional power supply, the non-ideal parasitic capacitance of the power switch often generates ringing effect, which not only causes large switching loss, but also causes the overall conversion efficiency of the power supply to decrease. In view of the above, a new solution is proposed to overcome the dilemma faced by the prior art.

Disclosure of Invention

In a preferred embodiment, the present invention provides a power supply for eliminating ringing, comprising: a bridge rectifier for generating a rectified potential according to a first input potential and a second input potential; a first transformer including a first primary winding and a first secondary winding, wherein the first transformer has an exciting inductor therein, the first primary winding is for receiving the rectified potential, and the first secondary winding is for generating an induced potential; a power switch for selectively coupling the first primary winding to ground according to a clock potential, wherein the power switch has a parasitic capacitor built therein; a delay and stabilization circuit; a second transformer including a second primary winding for receiving a resonant potential between the excitation inductor and the parasitic capacitor and a second secondary winding for generating a control potential; an output stage circuit, including a plurality of discharge paths, wherein the output stage circuit generates an output potential and a feedback potential according to the sensing potential and the control potential, and the plurality of discharge paths are selectively enabled or disabled according to the control potential; a third transformer including a third primary winding for receiving the feedback potential and a third secondary winding coupled to the delay and stabilization circuit; and a controller for generating the clock potential, wherein the clock potential is transmitted to the power switch via the delay and stabilization circuit.

Drawings

Fig. 1 is a schematic diagram illustrating a power supply according to an embodiment of the invention.

Fig. 2 is a schematic diagram illustrating a power supply according to an embodiment of the invention.

Fig. 3 is a waveform diagram showing the potential of a conventional power supply.

FIG. 4 is a diagram showing a potential waveform of the power supply according to an embodiment of the invention.

Description of reference numerals:

100. 200: power supply

110. 210: bridge rectifier

120. 220, and (2) a step of: first transformer

121. 221: a first main coil

122. 222: first secondary coil

130. 230: power switcher

140. 240: delay and stabilization circuit

150. 250: second transformer

151. 251: second main coil

152. 252: second sub-coil

160. 260: output stage circuit

161. 162: discharge path

170. 270: third transformer

171. 271: third main coil

172. 272: third secondary coil

180. 280: controller

190. 290: ground (earth)

310: first dotted line frame

410: second dotted line frame

C1: first capacitor

C2: second capacitor

And (3) CP: parasitic capacitor

D1: first diode

D2: second diode

D3: third diode

D4: fourth diode

D5: fifth diode

D6: sixth diode

D7: seventh diode

DZ: zener diode

IM: inductive current

L1: inductor

LM: exciting inductor

M1: a first transistor

M2: second transistor

M3: a third transistor

N1: first node

N2: second node

N3: third node

N4: fourth node

N5: the fifth node

N6: sixth node

N7: seventh node

N8: eighth node

N9: the ninth node

N10: the tenth node

NIN 1: first input node

NIN 2: second input node

NOUT: output node

R1: a first resistor

R2: second resistor

TD: set time

VA: clock potential

VC: controlling electric potential

VF: feedback potential

VIN 1: first input potential

VIN 2: second input potential

VN: resonance potential

VOUT: output potential

VR: rectified potential

VS: induced potential

VSS: ground potential

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "substantially" means within an acceptable error range, within which a person skilled in the art can solve the technical problem to achieve the basic technical result. In addition, the term "coupled" is used herein to encompass any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Fig. 1 is a schematic diagram illustrating a power supply 100 according to an embodiment of the invention. For example, the power supply 100 may be applied to a desktop computer, a notebook computer, or an integrated computer. As shown in fig. 1, the power supply 100 includes: a bridge rectifier 110, a first transformer 120, a power switch 130, a delay and stabilization circuit 140, a second transformer 150, an output stage circuit 160, a third transformer 170, and a controller 180. It should be noted that, although not shown in fig. 1, the power supply 100 may also include other components, such as: a voltage regulator or (and) a negative feedback circuit.

The bridge rectifier 110 generates a rectified voltage VR according to a first input voltage VIN1 and a second input voltage VIN 2. The first input potential VIN1 and the second input potential VIN2 can be derived from an external input power source, wherein an ac voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN 2. For example, the frequency of the ac voltage may be about 50Hz or 60Hz, and the root mean square value of the ac voltage may be from about 90V to about 264V, but is not limited thereto. The first transformer 120 includes a first primary winding 121 and a first secondary winding 122, wherein the first transformer 120 may have an exciting inductor LM. The magnetizing inductor LM may be an inherent element generated in the first transformer 120 when it is manufactured, and it is not an external independent element. The first primary winding 121 and the exciting inductor LM may be located on the same side of the first transformer 120, and the first secondary winding 122 may be located on the opposite side of the first transformer 120. The first primary winding 121 receives the rectified potential VR, and in response to the rectified potential VR, the first secondary winding 122 generates a sensing potential VS. The power switch 130 can selectively couple the first primary winding 121 and the exciting inductor LM to the ground 190 according to a clock potential VA. Ground 190 may refer to the earth, or any ground path coupled to the earth that is not an internal component of power supply 100. For example, if the clock level VA is at a high logic level (i.e., logic "1"), the power switch 130 couples both the first primary winding 121 and the exciting inductor LM to the ground 190 (i.e., the power switch 130 may approximate a short-circuit path); conversely, if the clock potential VA is at a low logic level (i.e., logic "0"), the power switch 130 does not couple the first primary winding 121 and the exciting inductor LM to the ground 190 (i.e., the power switch 130 may approximate an open circuit path). In addition, the power switch 130 may have a parasitic capacitor CP built therein. It should be understood that the total parasitic capacitance between the two ends of the power switch 130 can be modeled as the aforementioned parasitic capacitor CP, which is not an external independent component. The delay and stabilization circuit 140 may be used to adjust and limit the clock potential VA. The second transformer 150 includes a second primary winding 151 and a second secondary winding 152, wherein the second primary winding 151 may be located on one side of the second transformer 150, and the second secondary winding 152 may be located on the opposite side of the second transformer 150. The second primary winding 151 receives a resonant potential VN between the exciting inductor LM and the parasitic capacitor CP, and the second secondary winding 152 generates a control potential VC in response to the resonant potential VN. The output stage circuit 160 includes a plurality of

discharge paths

161, 162, the total number of which is not particularly limited in the present invention. The output stage circuit 160 can generate an output voltage VOUT and a feedback voltage VF according to the sensing voltage VS and the control voltage VC. For example, the output potential VOUT can be a dc potential, and the potential level can be from 18V to 22V, but is not limited thereto. The

aforementioned discharge paths

161, 162 can be selectively enabled or disabled according to the control potential VC. The third transformer 170 includes a third primary winding 171 and a third secondary winding 172, wherein the third secondary winding 172 may be located on one side of the third transformer 170, and the third primary winding 171 may be located on the opposite side of the third transformer 170. The third primary winding 171 receives a feedback potential VF, and the third secondary winding 172 is coupled to the delay and stabilization circuit 140. That is, the delay and stabilization circuit 140 can be controlled according to the feedback potential VF. The controller 180 generates a clock level VA, wherein the clock level VA is transmitted to the power switch 130 through the delay and stabilization circuit 140. For example, the controller 180 may be a pwm ic, but is not limited thereto. With this design, once the ringing effect is generated between the exciting inductor LM of the first transformer 120 and the parasitic capacitor CP of the power switch 130, the output stage circuit 160 and the delay and stabilization circuit 140 can appropriately limit the range of the resonant potential VN, thereby weakening the non-ideal characteristic. Therefore, the switching loss of the power switch 130 can be reduced, and the conversion efficiency of the power supply 100 can be improved.

The following embodiments will describe the detailed structure and operation of the power supply 100. It must be understood that these drawings and descriptions are only exemplary and are not intended to limit the scope of the present invention.

Fig. 2 is a schematic diagram illustrating a power supply 200 according to an embodiment of the invention. In the embodiment of fig. 2, the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a first transformer 220, a power switch 230, a delay and stabilization circuit 240, a second transformer 250, an output stage circuit 260, a third transformer 270, and a controller 280. The first input node NIN1 and the second input node NIN2 of the power supply 200 may respectively receive a first input potential VIN1 and a second input potential VIN2 from an external input power source, wherein an ac voltage with any frequency and any amplitude may be formed between the first input potential VIN1 and the second input potential VIN 2. The output node NOUT of the power supply 200 can output an output voltage VOUT to an electronic device, wherein the output voltage VOUT can be substantially a dc voltage.

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 for outputting a rectified voltage VR. An anode of the second diode D2 is coupled to the second input node NIN2, and a cathode of the second diode D2 is coupled to the first node N1. The anode of the third diode D3 is coupled to ground 290, and the cathode of the third diode D3 is coupled to the first input node NIN 1. Ground 290 may refer to the earth, or any ground path coupled to the earth, which is not an internal component of power supply 200. The anode of the fourth diode D4 is coupled to ground 290, and the cathode of the fourth diode D4 is coupled to the second input node NIN 2.

The first transformer 220 includes a first primary winding 221 and a first secondary winding 222, wherein the first transformer 220 may have an exciting inductor LM built therein. The magnetizing inductor LM may be an inherent element generated in the first transformer 220 when it is manufactured, and it is not an external independent element. The first primary winding 221 and the exciting inductor LM may be located on the same side of the first transformer 220, and the first secondary winding 222 may be located on the opposite side of the first transformer 220. The first terminal of the first primary winding 221 is coupled to a first node N1 for receiving the rectified voltage VR, and the second terminal of the first primary winding 221 is coupled to a second node N2. The first end of the first secondary winding 222 is coupled to a third node N3 for outputting a sensing potential VS, and the second end of the first secondary winding 222 is coupled to a ground potential VSS (e.g., 0V). A first terminal of the magnetizing inductor LM is coupled to the first node N1, and a second terminal of the magnetizing inductor LM is coupled to the second node N2.

The power switch 230 includes a first transistor M1. The first transistor M1 may be an nmos field effect transistor. The control terminal of the first transistor M1 is coupled to a fourth node N4 for receiving a clock potential VA from the controller 280, the first terminal of the first transistor M1 is coupled to the ground 290, and the second terminal of the first transistor M1 is coupled to the second node N2. The power switch 230 may have a parasitic capacitor CP built therein. In detail, a first terminal of the parasitic capacitor CP is coupled to the second node N2, and a second terminal of the parasitic capacitor CP is coupled to the ground 290. It should be understood that the total parasitic capacitance between the first terminal and the second terminal of the first transistor M1 can be modeled as the aforementioned parasitic capacitor CP, which is not an external independent component.

The controller 280 may output a clock level VA at the fourth node N4, and the clock level VA may be used to adjust the duty cycle of the power switch 230. For example, the clock level VA may be maintained at a fixed level during initialization of the power supply 200, and may provide a periodic clock waveform after the power supply 200 enters a normal use stage. It should be noted that the clock potential VA can also be adjusted and limited by the delay and stabilization circuit 240.

The delay and stabilization circuit 240 includes a Zener diode DZ, a first capacitor C1, and a fifth diode D5. The anode of the zener diode DZ is coupled to the ground 290, and the cathode of the zener diode DZ is coupled to the fourth node N4. A first terminal of the first capacitor C1 is coupled to the second node N2, and a second terminal of the first capacitor C1 is coupled to the fourth node N4. An anode of the fifth diode D5 is coupled to a fifth node N5, and a cathode of the fifth diode D5 is coupled to the second node N2.

The second transformer 250 includes a second primary winding 251 and a second secondary winding 252, wherein the second primary winding 251 can be located on one side of the second transformer 250, and the second secondary winding 252 can be located on the opposite side of the second transformer 250. A first end of the second main winding 251 is coupled to the second node N2 to receive a resonant potential VN between the exciting inductor LM and the parasitic capacitor CP, and a second end of the second main winding 251 is coupled to the ground 290. The first terminal of the second sub-coil 252 is coupled to a sixth node N6 for outputting a control potential VC, and the second terminal of the second sub-coil 252 is coupled to the ground potential VSS.

The output stage circuit 260 includes a second transistor M2, a third transistor M3, a sixth diode D6, a seventh diode D7, an inductor L1, a second capacitor C2, a first resistor R1, and a second resistor R2. The second transistor M2 and the third transistor M3 may each be an nmos field effect transistor. The control terminal of the second transistor M2 is coupled to the sixth node N6 for receiving the control potential VC, the first terminal of the second transistor M2 is coupled to the output node NOUT, and the second terminal of the second transistor M2 is coupled to the third node N3 for receiving the sensing potential VS. The first terminal of the first resistor R1 is coupled to the third node N3, and the second terminal of the first resistor R1 is coupled to a seventh node N7. The first terminal of the inductor L1 is coupled to the seventh node N7, and the second terminal of the inductor L1 is coupled to an eighth node N8. The control terminal of the third transistor M3 is coupled to the sixth node N6 for receiving the control potential VC, the first terminal of the third transistor M3 is coupled to a ninth node N9, and the second terminal of the third transistor M3 is coupled to the eighth node N8. An anode of the sixth diode D6 is coupled to the ninth node N9, and a cathode of the sixth diode D6 is coupled to the output node NOUT. A first terminal of the second capacitor C2 is coupled to the output node NOUT, and a second terminal of the second capacitor C2 is coupled to the ground potential VSS. The first end of the second resistor R2 is coupled to the eighth node N8, and the second end of the second resistor R2 is coupled to the ground potential VSS. The anode of the seventh diode D7 is coupled to the eighth node N8, and the cathode of the seventh diode D7 is coupled to a tenth node N10 to output a feedback potential VF.

Third transformer 270 includes a third primary winding 271 and a third secondary winding 272, wherein third secondary winding 272 may be located on one side of third transformer 270, and third primary winding 271 may be located on the opposite side of third transformer 270. A first terminal of the third primary winding 271 is coupled to the tenth node N10 for receiving the feedback potential VF, and a second terminal of the third primary winding 271 is coupled to the ground potential VSS. A first end of the third sub-coil 272 is coupled to the fifth node N5, and a second end of the third sub-coil 272 is coupled to the ground 290. In some embodiments, the first transformer 220, the second transformer 250, and the third transformer 270 together form an integrated transformer, wherein the first primary winding 221, the third secondary winding 272, and the second primary winding 251 are all located on the same side of the integrated transformer, and the first secondary winding 222, the third primary winding 271, and the second secondary winding 252 are all located on the opposite side of the integrated transformer.

In some embodiments, the power supply 200 can operate in an initial mode, a first mode, a second mode, or a third mode, which respectively have the following operation principles.

In the initial mode, the power supply 200 has not received the first input voltage VIN1 and the second input voltage VIN2, wherein the first transistor M1, the second transistor M2, the third transistor M3, the fifth diode D5, the sixth diode D6, and the seventh diode D7 are disabled.

In the first mode, the power supply 200 has received the first input potential VIN1 and the second input potential VIN2, wherein the clock potential VA is at a high logic level and the first transistor M1 is enabled. At this time, the zener diode DZ is reversely broken to stabilize the clock potential VA, and an inductor current IM passing through the exciting inductor LM gradually rises. The second transistor M2, the third transistor M3, the fifth diode D5, the sixth diode D6, and the seventh diode D7 are disabled.

In the second mode, the clock potential VA is at a low logic level and the first transistor M1 is disabled. At this time, the resonant potential VN at the second node N2 is instantly pulled up greatly, so that the relatively high control potential VC enables the second transistor M2 and the second transistor M3 at the same time. The energy stored in the exciting inductor LM is indirectly discharged to the ground potential VSS by the three discharge paths of the output stage circuit 260 via the first transformer 220. In detail, the second transistor M2 and the second capacitor C2 may form a first discharge path together; the first resistor R1, the inductor L1, and the second resistor R2 may collectively form a second discharge path; the first resistor R1, the inductor L1, the third transistor M3, the sixth diode D6, and the second capacitor C2 may collectively form a third discharge path. When the inductor current IM through the magnetizing inductor LM just drops to 0 (i.e., all the energy stored in the magnetizing inductor LM is released), the power supply 200 switches from the second mode to the third mode.

In the third mode, the second transistor M2 and the third transistor M3 are switched from the enabled state to the disabled state, and the exciting inductor LM of the first transformer 220 starts to resonate with the parasitic capacitor CP of the power switch 230. At this time, because of the cold-order law, the exciting inductor LM through which no inductor current IM passes is inverted (i.e., the potential at the eighth node N8 becomes high) to enable the seventh diode D7 and pull up the feedback potential VF. By using the third transformer 270 and the delay and stabilization circuit 240, the relatively high feedback potential VF adjusts and limits the resonance potential VN while delaying the clock potential VA. Then, the power supply 200 returns to the first mode again.

Fig. 3 is a diagram showing potential waveforms of a conventional power supply, in which the horizontal axis represents time and the vertical axis represents potential level. According to the measurement results of fig. 3, if the output stage circuit 260 and its discharge path are not used, a relatively large ringing effect (as shown at a first dashed box 310) will easily occur between the parasitic capacitor CP and the exciting inductor LM.

Fig. 4 is a diagram showing potential waveforms of the power supply 200 according to an embodiment of the invention, in which the horizontal axis represents time and the vertical axis represents potential level. It should be noted that, in the case of using the output stage circuit 260 and its discharge path, the resonant potential VN between the exciting inductor LM and the parasitic capacitor CP is limited to its first trough, so as to eliminate the subsequent unnecessary up-and-down oscillation. Thus, the ringing effect between parasitic capacitor CP and exciting inductor LM can be almost completely eliminated (as shown at a second dashed box 410). On the other hand, the first capacitor C1 can delay the clock potential VA by a predetermined time TD, so that the first transistor M1 can perform Zero Voltage Switching (ZVS), which can reduce the switching loss of the power Switch 230. With this design, the discharge time period of the output stage circuit 260 can be dynamically adjusted according to different requirements, and the conversion efficiency of the voltage converter 200 can be further improved under light load, heavy load, high voltage, or low voltage conditions.

In some embodiments, the component parameters of the power supply 200 may be as follows. The inductance of the exciting inductor LM may be between 328.5 muH and 401.5 muH, and preferably 365 muH. The inductance of inductor L1 may be between 24.7 μ H and 28.6 μ H, and may preferably be 26 μ H. The capacitance value of parasitic capacitor CP may be between 120pF and 180pF, and preferably may be 150 pF. The capacitance of the first capacitor C1 may be between 108pF and 132pF, and preferably may be 120 pF. The second capacitor C2 may have a capacitance value between 612 μ F and 748 μ F, and preferably 680 μ F. The resistance value of the first resistor R1 may be between 45.6K Ω and 50.4K Ω, and may preferably be 48K Ω. The resistance value of the second resistor R2 may be between 11.4K Ω and 12.6K Ω, and may preferably be 12K Ω. The ratio of the number of turns of the first primary winding 221 to the first secondary winding 222 may be between 1 and 100, and preferably may be 10. The ratio of the number of turns of the second primary winding 251 to the second secondary winding 252 may be between 1 and 100, and preferably may be 20. The ratio of the number of turns of the third primary winding 271 to the third secondary winding 272 may be between 0.1 and 10, and preferably may be 1. The breakdown voltage of the zener diode DZ is about 15V. The predetermined time TD is about 10 ns. The above parameter ranges are derived from a plurality of experimental results, which help to optimize the conversion efficiency of the power supply 200.

The present invention provides a novel power supply, which includes an output stage circuit and a discharge path thereof to suppress the ringing effect. According to the actual measurement results, the power supply using the aforementioned design can almost completely eliminate the non-ideal characteristics between the transformer and the power switch. The invention can effectively improve the conversion efficiency of the power supply and reduce the electromagnetic interference phenomenon, so the invention is suitable for being applied to various electronic devices.

It should be noted that the above-mentioned potential, current, resistance, inductance, capacitance, and other device parameters are not limitations of the present invention. The designer can adjust these settings according to different needs. The power supply of the present invention is not limited to the states illustrated in fig. 1 to 4. The present disclosure may include only any one or more features of any one or more of the embodiments of fig. 1-4. In other words, not all illustrated features may be implemented in a power supply of the present invention. Although the embodiments of the present invention use mosfet as an example, the present invention is not limited thereto, and other kinds of transistors can be used by those skilled in the art, such as: junction field effect transistors, fin field effect transistors, etc., without affecting the effect of the present invention.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A power supply for eliminating ringing effects, comprising:

a bridge rectifier, generating a rectified potential according to a first input potential and a second input potential;

A first transformer includes a first primary coil and a first secondary coil, wherein a magnetizing inductor is built in the first transformer, the first primary coil is used for receiving the rectified potential, and the first secondary coil is used for generate an induced potential;

a power switch selectively coupling the first main coil to the ground according to a clock potential, wherein the power switch has a built-in parasitic capacitor;

a delay and stabilization circuit;

a second transformer, comprising a second primary coil and a second secondary coil, wherein the second primary coil is used for receiving a resonant potential between the excitation inductor and the parasitic capacitor, and the second secondary coil is used for generating a control potential;

An output stage circuit includes a plurality of discharge paths, wherein the output stage circuit generates an output potential and a feedback potential according to the induced potential and the control potential, and the plurality of discharge paths selectively enable the discharge according to the control potential enable or disable;

a third transformer including a third main coil and a third sub-coil, wherein the third main coil is used for receiving the feedback potential, and the third sub-coil is coupled to the delay and stabilization circuit; and

A controller generates the clock potential, wherein the clock potential is transmitted to the power switch through the delay and stabilization circuit.

2. The power supply of claim 1, wherein the bridge rectifier comprises:

a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode coupled to a first node to output the rectified potential;

a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode coupled to the first node;

a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground, and the cathode of the third diode is coupled to the first input node; and

A fourth diode has an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground, and the cathode of the fourth diode is coupled to the second input node.

3. The power supply of claim 2, wherein the first main coil has a first end and a second end, the first end of the first main coil is coupled to the first node to receive the first node rectifying potential, the second end of the first main coil is coupled to a second node, the first sub coil has a first end and a second end, the first end of the first sub coil is coupled to A third node outputs the induced potential, the second end of the first sub-coil is coupled to a ground potential, the magnetizing inductor has a first end and a second end, the first end of the magnetizing inductor is coupled to the first node, and the second end of the magnetizing inductor is coupled to the second node.

4. The power supply of claim 3, wherein the power switch comprises:

a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is coupled to a fourth node to receive the clock potential from the controller, the first transistor The first end of a transistor is coupled to the ground, and the second end of the first transistor is coupled to the second node;

The parasitic capacitor has a first terminal and a second terminal, the first terminal of the parasitic capacitor is coupled to the second node, and the second terminal of the parasitic capacitor is coupled to the ground.

5. The power supply of claim 4, wherein the delay and stabilization circuit comprises:

a Zener diode having an anode and a cathode, wherein the anode of the Zener diode is coupled to the ground, and the cathode of the Zener diode is coupled to the fourth node;

a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the second node, and the second end of the first capacitor is coupled to the fourth node node; and

A fifth diode has an anode and a cathode, wherein the anode of the fifth diode is coupled to a fifth node, and the cathode of the fifth diode is coupled to the second node.

6. The power supply of claim 5, wherein the second main coil has a first end and a second end, the first end of the second main coil is coupled to the second node to receive the Resonant potential, the second end of the second main coil is coupled to the ground, the second sub coil has a first end and a second end, the first end of the second sub coil is coupled to a first end The six nodes are used to output the control potential, and the second end of the second sub-coil is coupled to the ground potential.

7. The power supply of claim 6, wherein the output stage circuit comprises:

a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to the sixth node to receive the control potential, the first terminal of the second transistor one end is coupled to an output node to output the output potential, and the second end of the second transistor is coupled to the third node to receive the induced potential;

a first resistor having a first end and a second end, wherein the first end of the first resistor is coupled to the third node, and the second end of the first resistor is coupled to a seventh node; and

An inductor has a first end and a second end, wherein the first end of the inductor is coupled to the seventh node, and the second end of the inductor is coupled to an eighth node.

8. The power supply of claim 7, wherein the output stage circuit further comprises:

a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to the sixth node to receive the control potential, the first terminal of the third transistor one end is coupled to a ninth node, and the second end of the third transistor is coupled to the eighth node;

a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the ninth node, and the cathode of the sixth diode is coupled to the output node; and

A second capacitor has a first end and a second end, wherein the first end of the second capacitor is coupled to the output node, and the second end of the second capacitor is coupled to the ground potential.

9. The power supply of claim 8, wherein the output stage circuit further comprises:

a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the eighth node, and the second end of the second resistor is coupled to the ground potential; and

A seventh diode has an anode and a cathode, wherein the anode of the seventh diode is coupled to the eighth node, and the cathode of the seventh diode is coupled to a tenth node to This feedback potential is output.

10. The power supply of claim 9, wherein the third main coil has a first end and a second end, the first end of the third main coil is coupled to the tenth node to receive the feedback potential, the second end of the third main coil is coupled to the ground potential, the third sub coil has a first end and a second end, the first end of the third sub coil is coupled to the ground potential a fifth node, and the second end of the third sub-coil is coupled to the ground;

When the energy stored in the excitation inductor is released, the output stage circuit adjusts and limits the resonant potential through the third transformer and the delay and stabilization circuit.