CN114200994A - Low dropout linear regulator and laser ranging circuit - Google Patents
Low dropout linear regulator and laser ranging circuit Download PDFInfo
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- CN114200994A CN114200994A CN202111485935.XA CN202111485935A CN114200994A CN 114200994 A CN114200994 A CN 114200994A CN 202111485935 A CN202111485935 A CN 202111485935A CN 114200994 A CN114200994 A CN 114200994A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
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Abstract
The application discloses low dropout regulator and laser ranging circuit, produce the module including voltage generation module and output, the operational amplifier non inverting input end that the voltage produced the module is as the input, and the output is connected with first PMOS pipe grid, and the inverting input end is connected with first PMOS pipe source, and the common port is connected with first current source. The drain electrode of a second PMOS tube of the output generation module is connected with the source electrode of a first NMOS tube, the source electrode of the second PMOS tube is connected with the drain electrode of a third PMOS tube, the source electrode of the third PMOS tube is connected with a second current source, the grid electrode of the third PMOS tube is connected with the second current source, the common end of the third PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the first NMOS tube is used as the bias voltage input end. The output generation module and the voltage generation module form stable loops, stability of the loops is not affected by each other, the number of the output generation modules can be changed, output current can be adjusted, and time and labor cost are saved.
Description
Technical Field
The application relates to the field of electronics, in particular to a low dropout regulator and a laser ranging circuit.
Background
In recent years, a chip low-power design is concerned, the inside of the chip is generally divided into a plurality of modules, the modules need to be independently powered, and the power supply of one or more modules is turned off according to actual business requirements, so that the purpose of saving power consumption is achieved. Currently, a Low Dropout Regulator (LDO) has a simple structure, a Low cost, and a good power supply ripple rejection performance, and is widely applied to various chips, and the requirement of independent power supply of multiple modules in the chip is realized by multiple LDOs.
Fig. 1 Is a structural diagram of a low dropout linear regulator circuit, as shown in fig. 1, the LDO Is composed of an operational amplifier U1, a PMOS transistor PM and a current source Is, an external input reference voltage Is input from a non-inverting input terminal VREF1 of the operational amplifier U1, an output terminal of the operational amplifier U1 Is connected to a gate of the PMOS transistor PM, an inverting input terminal Is connected to a drain of the PMOS transistor PM1, and a common terminal of the inverting input terminal and the PM drain Is used as a voltage output terminal VOUT1, and the common terminal Is further connected to one end of the current source Is, the other end of the current source Is grounded, and a source of the PMOS transistor PM Is connected to a power supply VDD. The input voltage is input through a non-inverting input terminal VREF1 of the operational amplifier U1, and drives the PMOS transistor PM to control the gate of the PM to generate an output voltage, and an output current is generated by the PMOS transistor PM, so that the output terminal VOUT1 supplies power to the load circuit.
The operational amplifier U1 and the PMOS transistor PM together form a loop, and different load currents are required for different load circuits, so all circuits in the LDO need to be redesigned to change their load carrying capability, for example, the current of the output terminal VOUT1 is increased to 2 times, the aspect ratio of the PMOS transistor PM is increased to 2 times, the driving in the operational amplifier needs to be increased to 2 times, and the redesign increases manpower and cost.
Therefore, how to solve the problem that the whole circuit needs to be redesigned to adjust the current of the load circuit, which saves labor and cost, is a problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The utility model aims at providing a low dropout regulator, output produces the module and has formed stable return circuit through three MOS pipe and a current source, voltage produces the module and passes through operational amplifier, a MOS pipe and a current source have also formed a stable return circuit, then the output produces the module and the complementary influence of stability of voltage production module, therefore, load circuit can produce the electric current of module's quantity adjustment output through changing the output according to actual demand, when having avoided using LDO, adjust whole circuit of needs redesign to some circuit, save time and human cost.
In order to solve the above technical problem, the present application provides a low dropout regulator, including: the device comprises a voltage generation module and an output generation module;
the voltage generation module comprises an operational amplifier, a first PMOS (P-channel metal oxide semiconductor) tube, a first current source and a first resistor, wherein the non-inverting input end of the operational amplifier is used as the reference voltage input end of the voltage generation module, the inverting input end of the operational amplifier is connected with the source electrode of the first PMOS tube, the common end of the operational amplifier is connected with one end of the first current source, the other end of the first current source is connected with a power supply, the drain electrode of the first PMOS tube is connected with one end of the first resistor, the other end of the first resistor is grounded, the output end of the operational amplifier is connected with the grid electrode of the first PMOS tube, and the common end of the operational amplifier is used as the output end of the voltage generation module;
the output generation module comprises a second PMOS tube, a third PMOS tube, a second current source, a first NMOS tube and a second resistor, wherein the drain electrode of the second PMOS tube is connected with the source electrode of the first NMOS tube, the common end of the second PMOS tube is connected with one end of the second resistor, the other end of the second resistor is grounded, the source electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with one end of the second current source, the common end of the third PMOS tube is connected with the power supply, the grid electrode of the third PMOS tube is connected with the other end of the second current source, and the common end of the third PMOS tube is connected with the drain electrode of the first NMOS tube;
the grid electrode of the first NMOS tube is used as a bias voltage input end, the grid electrode of the second PMOS tube is used as a control end of the output generation module, the source electrode of the second PMOS tube is used as an output end of the output generation module, and the output end of the voltage generation module is connected with the control end of the output generation module.
Preferably, the output generation modules are multiple, and the output end of each output generation module is connected with the power end of the same load circuit.
Preferably, the number of the output generating modules is multiple, so as to form multiple groups of output generating circuits, and the output end of each group of the output generating circuits is connected with the power end of one load circuit; each group of the output generation circuits comprises at least two output generation modules which are connected in parallel.
Preferably, the device is characterized by further comprising a bias voltage generation module;
and a first bias voltage output end of the bias voltage generation module is connected with the grid electrode of the first NMOS tube.
Preferably, the second current source is a fourth PMOS transistor;
the grid electrode of the fourth PMOS tube is connected with the second bias voltage output end of the bias voltage generation module, the source electrode of the fourth PMOS tube is connected with the source electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube.
Preferably, the first current source is a fifth PMOS transistor, and the voltage generation module further includes a sixth PMOS transistor and a second NMOS transistor;
the drain electrode of the fifth PMOS tube is connected with the source electrode of the first PMOS tube, the source electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, the common end of the fifth PMOS tube is connected with the power supply, the grid electrode of the sixth PMOS tube is connected with the second bias voltage output end, the grid electrode of the fifth PMOS tube is connected with the drain electrode of the sixth PMOS tube, the common end of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube.
Preferably, the width-to-length ratio of the second PMOS transistor is N times of the width-to-length ratio of the first PMOS transistor, the width-to-length ratio of the fourth PMOS transistor is N times of the width-to-length ratio of the sixth PMOS transistor, the width-to-length ratio of the first NMOS transistor is N times of the width-to-length ratio of the second NMOS transistor, the resistance value of the second resistor is 1/N times of the resistance value of the first resistor, where N is a positive rational number.
Preferably, the bias voltage generation module includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a third resistor, a fourth resistor, and a third current source;
the source electrodes of the seventh PMOS tube, the eighth PMOS tube and the ninth PMOS tube are connected in pairs, a common end of the seventh PMOS tube is connected with one end of the third current source and is connected with a power supply, the other end of the third current source is connected with the drain electrode of the third NMOS tube, the grid electrode and the drain electrode of the seventh PMOS tube are connected with the grid electrode of the eighth PMOS tube, and the common end of the seventh PMOS tube is connected with the drain electrode of the fourth NMOS tube;
a grid electrode of the ninth PMOS tube is connected with a drain electrode, a common end of the ninth PMOS tube is used as the second bias voltage output end and is connected with a drain electrode of the sixth NMOS tube, a grid electrode of the fifth NMOS tube is connected with a grid electrode of the sixth NMOS tube, and a common end of the fifth NMOS tube is used as the first bias voltage output end and is respectively connected with a drain electrode of the eighth PMOS tube and a drain electrode of the fifth NMOS tube;
the drain electrode of the third NMOS tube is connected with the grid electrode, the common end of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the source electrode of the third NMOS tube is grounded, the source electrode of the fourth NMOS tube is grounded, one end of the third resistor is connected with the source electrode of the fifth NMOS tube, the other end of the third resistor is grounded, one end of the fourth resistor is connected with the source electrode of the sixth NMOS tube, and the other end of the fourth resistor is grounded.
Preferably, the width-to-length ratio of the ninth PMOS transistor is M times of the width-to-length ratio of the sixth PMOS transistor, the width-to-length ratio of the fifth NMOS transistor is M times of the width-to-length ratio of the second NMOS transistor, and the resistance of the third resistor is equal to the resistance of the fourth resistor, where M is a positive rational number.
In order to solve the technical problem, the present application further provides a laser ranging circuit, which includes the low dropout regulator.
The low dropout regulator provided by the invention comprises: the voltage generation module comprises an operational amplifier, a first PMOS (P-channel metal oxide semiconductor) tube, a first current source and a first resistor, wherein the non-inverting input end of the operational amplifier is used as the reference voltage input end of the voltage generation module, the inverting input end of the operational amplifier is connected with the source electrode of the first PMOS tube, the public end of the non-inverting input end of the operational amplifier is connected with one end of the first current source, the other end of the first current source is connected with a power supply, the drain electrode of the first PMOS tube is connected with one end of the first resistor, the other end of the first resistor is grounded, the output end of the operational amplifier is connected with the grid electrode of the first PMOS tube, and the public end of the non-inverting input end of the operational amplifier is used as the output end of the voltage generation module. The output generation module comprises a second PMOS tube, a third PMOS tube, a second current source, a first NMOS tube and a second resistor, wherein the drain electrode of the second PMOS tube is connected with the source electrode of the first NMOS tube, the public end of the second PMOS tube is connected with one end of the second resistor, the other end of the second resistor is grounded, the source electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with one end of the second current source, the public end of the third PMOS tube is connected with the power supply, the grid electrode of the third PMOS tube is connected with the other end of the second current source, and the public end of the third PMOS tube is connected with the drain electrode of the first NMOS tube. The grid electrode of the first NMOS tube is used as a bias voltage input end, the grid electrode of the second PMOS tube is used as a control end of the output generation module, the source electrode of the second PMOS tube is used as an output end of the output generation module, and the output end of the voltage generation module is connected with the control end of the output generation module. Therefore, according to the technical scheme provided by the invention, an independent and stable feedback loop is formed between the three MOS tubes and the current source in the output generation module, namely the stability of the feedback loop is not influenced by the voltage generation module any more, in addition, the voltage generation module also forms a stable loop, the generated output voltage clamps the output voltage of the output generation module, and further the output voltage of the output generation module is ensured to be equal to the reference input voltage of the voltage generation module, therefore, the number of the output generation modules can be changed according to the actual requirement of a load to adjust the output current, the redesign of the whole circuit is avoided, the time cost and the labor cost are further saved, and the user experience is improved.
The application also provides a laser ranging circuit, including foretell low dropout regulator, the effect is the same as above.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
FIG. 1 is a block diagram of a low dropout linear regulator circuit;
fig. 2 is a structural diagram of a low dropout linear regulator according to an embodiment of the present invention;
fig. 3 is a block diagram of a low dropout linear regulator according to another embodiment of the present invention;
fig. 4 is a block diagram of a bias circuit in the low dropout regulator according to the embodiment of the present invention.
The reference signs are: 1 is a voltage generation module, 2 is an output generation module, and 3 is a bias voltage.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
The core of the application is to provide a low dropout regulator, generate the module including voltage generation module and output, output generation module forms stable and independent return circuit, voltage generation module forms stable and independent return circuit, the quantity through adjusting output generation module according to actual demand changes the electric current of output, therefore, produce the module to voltage generation or output and adjust, can not influence the stability of circuit each other, and then need not all to adjust voltage generation module and output generation module, when having avoided using LDO, need redesign whole circuit, time cost and human cost have been practiced thrift.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.
At present, the LDO has the advantages of simple structure, low cost and good power supply ripple rejection performance, and is widely applied to various chips and used for independently supplying power to a plurality of modules in the chips. However, in practical applications, as the number of modules in a chip increases, the need for independent power supply of the LDO increases, thereby incurring a large cost, area and power consumption. In addition, as shown in fig. 1, the LDO is composed of an operational amplifier U1 and a PMOS transistor PM, a non-inverting input terminal VREF1 of the operational amplifier U1 is used as a voltage input terminal of the LDO, an inverting input terminal is connected to a drain of the PMOS transistor PM, an output terminal is connected to a gate of the PMOS transistor PM, an output voltage is generated by controlling a gate voltage of the PMOS transistor PM, a source of the PMOS transistor PM is connected to a power supply to provide an output current for the output terminal VOUT1, and thus, the output terminal VOUT1 of the LDO provides a power supply for a load circuit. It can be seen that the operational amplifier U1 and the PMOS transistor PM form a loop to supply power to the load circuit, and when the load circuit needs to adjust the load capacitance or the load current, all circuits in the LDO need to be redesigned, thereby increasing the labor cost and the time cost.
Therefore, in order to solve the above problem, the present invention provides a low dropout regulator, and fig. 2 is a structural diagram of the low dropout regulator according to an embodiment of the present invention, and as shown in fig. 2, the circuit includes a voltage generating module 1 and an output generating module 2. The voltage generation module 1 comprises an operational amplifier U2, a first PMOS transistor PM1, a first current source Is1 and a first resistor R1, wherein a non-inverting input terminal of the operational amplifier U2 Is used as a reference voltage input terminal VREF2 of the voltage generation module 1, an inverting input terminal Is connected with a source of the first PMOS transistor PM1, a common terminal Is connected with one end of the first current source Is1, the other end of the first current source Is1 Is connected with a power supply VDD, a drain of the first PMOS transistor PM1 Is connected with one end of the first resistor R1, the other end of the first resistor R1 Is grounded, an output terminal of the operational amplifier U2 Is connected with a gate of the first PMOS transistor PM1, and the common terminal Is used as an output terminal of the voltage generation module 1.
The output generation module 2 comprises a second PMOS transistor PM2, a third PMOS transistor PM3, a second current source Is2, a first NMOS transistor NM1 and a second resistor R2, wherein the drain of the second PMOS transistor PM2 Is connected to the source of the first NMOS transistor NM1, the common terminal of the second PMOS transistor NM2 Is connected to one end of the second resistor R2, the other end of the second resistor R2 Is grounded, the source of the second PMOS transistor PM2 Is connected to the drain of the third PMOS transistor PM3, the source of the third PMOS transistor PM3 Is connected to one end of the second current source Is2, the common terminal of the third PMOS transistor PM3 Is connected to the power supply VDD, the gate of the third PMOS transistor PM3 Is connected to the other end of the second current source Is2, and the common terminal of the third PMOS transistor NM1 Is connected to the drain of the first NMOS transistor NM 1.
The gate of the first NMOS transistor NM1 is used as the bias voltage input terminal of the output generation module 2, the gate of the second PMOS transistor PM2 is used as the control terminal of the output generation module 2, the source of the second PMOS transistor PM2 is used as the output terminal VOUT2 of the output generation module 2, and the output terminal of the voltage generation module 1 is connected to the control terminal of the output generation module 2.
As shown in fig. 2, the voltage generating module 1 generates a control voltage to be transmitted to the gate of the second PMOS transistor PM2, and the second PMOS transistor PM2 is used as a source follower, so that the output voltage of the output terminal VOUT2 is clamped by the control voltage, and the output voltage is equal to the reference input voltage of the input terminal VREF 2. In addition, an independent and stable Loop2 Is formed among the second PMOS transistor PM2, the third PMOS transistor PM3, the first NMOS transistor NM1 and the second current source Is2 in the output generation module 2, so that the stability of the output generation module 2 Is not affected by the voltage generation module 1, and the output current of the output terminal VOUT2 Is provided by the third PMOS transistor PM3, so that a plurality of output generation modules 2 can be connected in parallel with the voltage generation module 1 as required to control the output current, and the whole circuit does not need to be redesigned.
In the specific implementation, the operational amplifier U2 of the voltage generating module 1 and the first PMOS transistor PM1 also form an independent and stable loop, so when the voltage generating module 1 needs to be modified, the output generating module 2 does not need to be modified, that is, the stability between the voltage generating module 1 and the output generating module 2 is independent, and the modification of any one module does not affect the normal operation of the other module.
It can be understood that, since the stabilities of the voltage generating module 1 and the output generating module 2 are not affected by each other, redesigning any one of the modules will not affect each other stability, and thus, the number of the output generating modules 2 can be modified according to the actual requirement of the load to change the output current, so in practical application, one output generating module 2 can supply power to one load circuit, or a plurality of output generating modules 2 can be connected in parallel to supply power to one load circuit, of course, a plurality of output generating modules 2 can also form a plurality of sets of output generating circuits, each output generating circuit at least includes two output generating modules 2, and each output generating circuit supplies power to one load.
In specific implementation, in order to ensure that the output voltage of the output terminal VOUT2 is equal to the reference input voltage of the input terminal VREF2, the design is simpler, and the low dropout linear regulator provided by the invention adopts more current mirror structures, so that the currents of all branches are proportional. As shown in fig. 3, the first current source Is1 Is a fifth PMOS transistor PM5, the second current source Is2 Is a fourth PMOS transistor PM4, and the voltage generating module 1 further includes a sixth PMOS transistor PM6 and a second NMOS transistor NM 2. In addition, the width-to-length ratio of the second PMOS transistor PM2 is N times the width-to-length ratio of the first PMOS transistor PM1, the width-to-length ratio of the fourth PMOS transistor PM4 is N times the width-to-length ratio of the sixth PMOS transistor PM6, the width-to-length ratio of the first NMOS transistor NM1 is N times the width-to-length ratio of the second NMOS transistor NM2, and the resistance value of the second resistor R2 is 1/N times the resistance value of the first resistor R1, where N is a positive rational number.
It is understood that the gates of the fourth PMOS transistor PM4, the sixth PMOS transistor PM6, the first NMOS transistor NM1 and the second NMOS transistor NM2 need a bias circuit to provide voltages to them, but the present invention is not limited to the bias circuit.
In the low dropout regulator provided by the embodiment of the invention, an independent and stable feedback loop is formed between the three MOS tubes and the current source in the output generation module, namely the stability of the low dropout regulator is not influenced by the voltage generation module any more, in addition, the voltage generation module also forms a stable loop, the generated output voltage clamps the output voltage of the output generation module, and further the output voltage of the output generation module is ensured to be equal to the reference input voltage of the voltage generation module, therefore, the number of the output generation modules can be changed according to the actual requirement of a load to adjust the output current, the redesign of the whole circuit is avoided, the time cost and the labor cost are further saved, and the user experience is improved.
In a specific implementation, as shown in fig. 2, in a steady state, when the load needs a large current, that is, the output terminal VOUT2 of the output generation module 2 is a large current, at this time, the output of the voltage generation module 1 generates a control voltage to the gate of the second PMOS transistor PM2, and clamps the voltage of the output terminal VOUT2, that is, the voltage of the output terminal VOUT2 is equal to the reference voltage of the input terminal VREF2 of the voltage generation module 1. The current passing through the third PMOS pipe PM3 is IPM3＝IPM2+ Iout, when the output terminal Iout suddenly increases to I' out, VOUT2 will drop, the gate voltage through the second PMOS transistor PM2 will not change, and the current I through the second PMOS transistor PM2 will bePM2At this time, when the current passing through the second resistor R2 is also reduced, the voltage at the source of the first NMOS transistor NM1 is reduced, the gate-source voltage of NM1 is increased, and the current at NM1 is increased, and at this time, the gate voltage of the third PMOS transistor PM3 is pulled low, so that the current I 'of PM3 is decreased'PM3Is increased to make I'PM3＝IPM2+ I' out, whereby the output generating module 2 returns to the steady state again.
Therefore, the stability of the output generation module 2 and the stability of the voltage generation module 1 are not interfered with each other, and the actual requirements of different loads can be met by adjusting the size of the second PMOS transistor PM2 in the output generation module 2 or the number of the output generation modules 2. In fact, in practical applications, when the current required by the load is small, the size of the second PMOS transistor PM2 can be adjusted, and when the current required by the load is large, the number of the output generating modules 2 can be changed.
In a specific implementation, one output generation module 2 may provide current for one load, or a plurality of output generation modules 2 may be connected in parallel to provide current for one load, or of course, a plurality of output generation modules 2 may form a plurality of sets of output generation circuits, each output generation circuit provides power for one load, where each output generation circuit at least includes two output generation modules 2, and the output generation modules 2 are connected in parallel.
Fig. 3 Is a block diagram of a low dropout linear regulator according to another embodiment of the present invention, in an implementation, in order to ensure that the voltage of the output terminal VOUT2 Is equal to the reference voltage of the input terminal VREF2 of the voltage generation module, as shown in fig. 3, the first current source Is1 Is configured as a fifth PMOS transistor PM5, the second current source Is2 Is configured as a fourth PMOS transistor PM4, and the voltage generation module further includes a sixth PMOS transistor PM6 and a second NMOS transistor NM 2. The drain of the fifth PMOS transistor PM5 is connected to the source of the first PMOS transistor PM1, the common terminal of the fifth PMOS transistor PM5 is connected to the inverting input terminal of the operational amplifier U2, the source of the fifth PMOS transistor PM5 is connected to the source of the sixth PMOS transistor PM6, the common terminal of the fifth PMOS transistor PM5 is connected to the power supply VDD, the drain of the second NMOS transistor NM2 is connected to the drain of the sixth PMOS transistor PM6, the common terminal of the second PMOS transistor PM5 is connected to the gate of the fifth PMOS transistor PM5, and the gate of the sixth PMOS transistor PM6 and the gate of the second NMOS transistor NM2 are both used as the bias voltage input terminals of the voltage generating module. The source of the fourth PMOS transistor PM4 is connected to the source of the third PMOS transistor PM3, and the common terminal is connected to the power supply VDD, the drain of the fourth PMOS transistor PM4 is connected to the drain of the first NMOS transistor NM1, and the gate of the drain of the fourth PMOS transistor PM4 is used as the second bias voltage input terminal of the output generating module.
It should be noted that the width-to-length ratio of the second PMOS transistor PM2 is N times the width-to-length ratio of the first PMOS transistor PM1, the width-to-length ratio of the fourth PMOS transistor PM4 is N times the width-to-length ratio of the sixth PMOS transistor PM6, the width-to-length ratio of the first NMOS transistor NM1 is N times the width-to-length ratio of the second NMOS transistor NM2, and the resistance value of the second resistor R2 is 1/N times the resistance value of the first resistor R1, where N is a positive rational number. Thus, the control voltage output by the voltage generation module is further guaranteed to clamp the voltage at the output terminal VOUT2 of the output generation module, i.e., the voltage at the output terminal VOUT2 is further guaranteed to be equal to the reference voltage at the input terminal VREF2 of the voltage generation module.
The output generating module 2 is composed of a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4 and a first NMOS transistor NM1, and a second resistor R2, the drain of the second PMOS transistor PM2 is connected to the source of the first NMOS transistor, and the common terminal is connected to one terminal of a second resistor R2, the other terminal of the second resistor R2 is grounded, the source of the second PMOS transistor PM2 is connected to the drain of the third PMOS transistor PM3, and the common terminal is an output terminal VOUT2 of the output generating module 2, the source of the fourth PMOS transistor PM4 is connected to the source of the third PMOS transistor PM3, and the common terminal is connected to a power supply VDD, the drain of the fourth PMOS transistor PM4 is connected to the drain of the first NMOS transistor NM1, and the common terminal is connected to the gate of the third PMOS transistor PM3, the gate of the fourth PMOS transistor PM4 is connected to the first bias voltage output terminal Vbisap of the bias circuit 3, and the gate of the first NMOS transistor PM1 is connected to the second bias circuit Vbisan 3. See detailed description below.
In a specific implementation, the voltage generating module 1 does not directly drive the gate of the third PMOS transistor PM3, but generates a control voltage to be transmitted to the gate of the second PMOS transistor PM2, the second PMOS transistor PM2 serves as a source follower, the control voltage transmitted by the voltage generating module 1 clamps the output voltage of the output terminal VOUT2, the output voltage of the output terminal VOUT2 of the output generating module 2 is equal to the reference voltage of the input terminal VREF2 of the voltage generating module 1, and the voltage generating module 1 does not directly drive the gate of the third PMOS transistor PM3, so the output current of the electrical output terminal VOUT2 is not affected by the control voltage. The stability of the voltage generation module 1 depends on the self-generated stable Loop1, and the stability of the output generation module 2 also depends on the self-generated stable Loop2, so that the circuit only needs to generate a control voltage, and the control voltage is used for clamping the output voltage without providing the output current, therefore, the size, the number and the area of the voltage generation module 1 of the low dropout regulator provided by the invention are not large as LDO (low dropout regulator), and therefore, the number of the output generation modules 2 can be modified according to the actual requirement of a load to change the output current.
The low dropout regulator provided by the embodiment of the invention sets the first current source in the voltage generation module as a PMOS (P-channel metal oxide semiconductor) tube, and additionally sets a PMOS tube and an NMOS tube, and sets the second current source in the output generation module as a PMOS tube, and simultaneously realizes that the output voltage of the output end VOUT2 of the output generation module is equal to the reference voltage of the input end VREF2 by setting the size proportional relation of the voltage generation module and part of MOS tubes in the output generation module, so that the output current of the output generation module is adjusted by changing the number of the output generation modules or the size of the MOS tubes in the output generation module under the condition of ensuring the output voltage of the output end VOUT2 of the output generation module, thereby avoiding that the whole circuit needs to be redesigned when adjusting a part of circuits in the traditional LDO (low dropout regulator), and further saving time and labor cost.
In a specific embodiment, the gates of the fourth PMOS transistor PM4, the sixth PMOS transistor PM6, the first NMOS transistor NM1 and the second NMOS transistor NM2 all input a bias voltage, and the invention is not limited to the circuit for providing the bias voltage. As shown in fig. 3, the gates of the fourth PMOS transistor PM4 and the sixth PMOS transistor PM6 are both connected to the first bias voltage output terminal vbiasp of the bias circuit 3, and the gates of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected to the second bias voltage output terminal vbian of the bias circuit 3.
Fig. 4 Is a structural diagram of the bias circuit 3 in the low dropout regulator according to the embodiment of the present invention, and as shown in fig. 4, the structure of the bias voltage may be composed of a third current source Is3, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a third resistor R3, and a fourth resistor R4.
Wherein, the sources of the seventh PMOS transistor PM7, the eighth PMOS transistor PM8 and the ninth PMOS transistor PM9 are connected in pairs, and the common terminal Is connected with the power supply VDD and one terminal of the third current source Is3, the other terminal of the third current source Is3 Is connected with the drain of the third NMOS transistor NM3, the gate of the seventh PMOS transistor PM7 Is connected with the gate of the eighth PMOS transistor PM8, and the common terminal Is connected with the drain of the fourth NMOS transistor NM4, the drain of the seventh PMOS transistor PM7 Is connected with the drain of the fourth NMOS transistor NM4, the gate of the ninth PMOS transistor PM9 Is connected with the drain, and the common terminal Is used as the first bias voltage output terminal vbiap and Is connected with the drain of the sixth NMOS transistor NM6, the gate of the fifth NMOS transistor NM5 Is connected with the gate of the sixth NMOS transistor NM6, and the common terminal Is used as the second bias voltage output terminal vbian, and the drains of the eighth PMOS transistor PM8 and the fifth NMOS transistor PM5 are connected with the drain of the third NMOS transistor PM3, and the common terminal Is connected with the drain of the fourth NMOS 4, the source of the third NMOS transistor NM3 is grounded, the source of the fourth NMOS transistor NM4 is grounded, one end of the third resistor R3 is connected to the source of the fifth NMOS transistor NM5, the other end is grounded, one end of the fourth resistor R4 is connected to the source of the sixth NMOS transistor NM6, and the other end is grounded.
It should be noted that, in order to better ensure that the voltage of the output terminal VOUT2 is equal to the reference voltage of the input terminal VREF2 of the voltage generation module 1, and to simplify the design, the width-to-length ratio of the ninth PMOS transistor PM9 in the bias voltage is M times of the width-to-length ratio of the sixth PMOS transistor PM5, the width-to-length ratio of the fifth NMOS transistor NM5 is M times of the width-to-length ratio of the second NMOS transistor NM1, and the resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4, where M is a positive rational number.
The low dropout regulator provided by the embodiment of the application is characterized in that the bias circuit is arranged in the voltage generation module and the output generation module and consists of seven MOS transistors, and part of the MOS transistors in the bias circuit is in proportion to the voltage generation module and the MOS transistors in the output generation module, so that the output voltage of the output generation module is further ensured to be equal to the reference input voltage of the voltage generation module, and the overall performance of the circuit is improved.
The present invention further provides a laser ranging circuit, which includes the low dropout regulator mentioned in the above embodiments, and the detailed description of the low dropout regulator is omitted in this embodiment since the detailed description is given above.
The laser ranging circuit provided by the invention comprises the low dropout linear regulator mentioned in the above embodiment, wherein, the low dropout linear regulator comprises a voltage generating module and an output generating module, the voltage generating module comprises an operational amplifier, a first PMOS tube, a first current source and a first resistor, the non-inverting input end of the operational amplifier is used as the reference voltage input end of the voltage generating module, the inverting input end is connected with the source electrode of the first PMOS tube, the common end is connected with one end of a first current source, the other end of the first current source is connected with a power supply, the drain electrode of a first PMOS tube is connected with one end of a first resistor, the other end of the first resistor is grounded, the output end of the operational amplifier is connected with the grid electrode of the first PMOS tube, the common end is used as the output end of the voltage generation module, therefore, an independent and stable loop is formed between the operational amplifier and the first PMOS tube in the voltage generation module. The output generation module comprises a second PMOS tube, a third PMOS tube, a second current source, a first NMOS tube and a second resistor, wherein the drain electrode of the second PMOS tube is connected with the source electrode of the first NMOS tube, the public end of the second PMOS tube is connected with one end of the second resistor, the other end of the second resistor is grounded, the source electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with one end of the second current source, the public end of the third PMOS tube is connected with the power supply, the grid electrode of the third PMOS tube is connected with the other end of the second current source, and the public end of the third PMOS tube is connected with the drain electrode of the first NMOS tube. The grid electrode of the first NMOS tube is used as a bias voltage input end, the grid electrode of the second PMOS tube is used as a control end of the output generation module, the source electrode of the second PMOS tube is used as an output end of the output generation module, and the output end of the voltage generation module is connected with the control end of the output generation module. Therefore, according to the technical scheme provided by the invention, an independent and stable feedback loop is formed between the three MOS tubes and the current source in the output generation module, namely the stability of the feedback loop is not influenced by the voltage generation module any more, in addition, the voltage generation module also forms a stable loop, the generated output voltage clamps the output voltage of the output generation module, and further the output voltage of the output generation module is ensured to be equal to the reference input voltage of the voltage generation module, therefore, the number of the output generation modules can be changed according to the actual requirement of a load to adjust the output current, the situation that the whole circuit needs to be redesigned when a part of circuits are adjusted in an LDO (low dropout regulator) is avoided, and the time cost and the labor cost are further saved.
The low dropout regulator and the laser ranging circuit provided by the present application are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A low dropout linear regulator, comprising: the device comprises a voltage generation module and an output generation module;
the voltage generation module comprises an operational amplifier, a first PMOS (P-channel metal oxide semiconductor) tube, a first current source and a first resistor, wherein the non-inverting input end of the operational amplifier is used as the reference voltage input end of the voltage generation module, the inverting input end of the operational amplifier is connected with the source electrode of the first PMOS tube, the common end of the operational amplifier is connected with one end of the first current source, the other end of the first current source is connected with a power supply, the drain electrode of the first PMOS tube is connected with one end of the first resistor, the other end of the first resistor is grounded, the output end of the operational amplifier is connected with the grid electrode of the first PMOS tube, and the common end of the operational amplifier is used as the output end of the voltage generation module;
the output generation module comprises a second PMOS tube, a third PMOS tube, a second current source, a first NMOS tube and a second resistor, wherein the drain electrode of the second PMOS tube is connected with the source electrode of the first NMOS tube, the common end of the second PMOS tube is connected with one end of the second resistor, the other end of the second resistor is grounded, the source electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with one end of the second current source, the common end of the third PMOS tube is connected with the power supply, the grid electrode of the third PMOS tube is connected with the other end of the second current source, and the common end of the third PMOS tube is connected with the drain electrode of the first NMOS tube;
the grid electrode of the first NMOS tube is used as a bias voltage input end, the grid electrode of the second PMOS tube is used as a control end of the output generation module, the source electrode of the second PMOS tube is used as an output end of the output generation module, and the output end of the voltage generation module is connected with the control end of the output generation module.
2. The low dropout regulator according to claim 1, wherein the output generating module is a plurality of modules, and an output terminal of each of the output generating modules is connected to a power supply terminal of the same load circuit.
3. The low dropout regulator according to claim 1, wherein the output generating module comprises a plurality of output generating circuits, and the output terminal of each output generating circuit is connected to a power supply terminal of a load circuit; each group of the output generation circuits comprises at least two output generation modules which are connected in parallel.
4. The low dropout regulator according to any one of claims 1 to 3, further comprising a bias voltage generating module;
and a first bias voltage output end of the bias voltage generation module is connected with the grid electrode of the first NMOS tube.
5. The LDO of claim 4, wherein the second current source is a fourth PMOS transistor;
the grid electrode of the fourth PMOS tube is connected with the second bias voltage output end of the bias voltage generation module, the source electrode of the fourth PMOS tube is connected with the source electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube.
6. The LDO of claim 5, wherein the first current source is a fifth PMOS transistor, and the voltage generation module further comprises a sixth PMOS transistor and a second NMOS transistor;
the drain electrode of the fifth PMOS tube is connected with the source electrode of the first PMOS tube, the source electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, the common end of the fifth PMOS tube is connected with the power supply, the grid electrode of the sixth PMOS tube is connected with the second bias voltage output end, the grid electrode of the fifth PMOS tube is connected with the drain electrode of the sixth PMOS tube, the common end of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube.
7. The low dropout regulator according to claim 6, wherein the width-to-length ratio of the second PMOS transistor is N times the width-to-length ratio of the first PMOS transistor, the width-to-length ratio of the fourth PMOS transistor is N times the width-to-length ratio of the sixth PMOS transistor, the width-to-length ratio of the first NMOS transistor is N times the width-to-length ratio of the second NMOS transistor, and the resistance of the second resistor is 1/N times the resistance of the first resistor, where N is a positive rational number.
8. The low dropout regulator of claim 4 wherein the bias voltage generating module comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a third resistor, a fourth resistor, and a third current source;
the source electrodes of the seventh PMOS tube, the eighth PMOS tube and the ninth PMOS tube are connected in pairs, a common end of the seventh PMOS tube is connected with one end of the third current source and is connected with a power supply, the other end of the third current source is connected with the drain electrode of the third NMOS tube, the grid electrode and the drain electrode of the seventh PMOS tube are connected with the grid electrode of the eighth PMOS tube, and the common end of the seventh PMOS tube is connected with the drain electrode of the fourth NMOS tube;
a grid electrode of the ninth PMOS tube is connected with a drain electrode, a common end of the ninth PMOS tube is used as the second bias voltage output end and is connected with a drain electrode of the sixth NMOS tube, a grid electrode of the fifth NMOS tube is connected with a grid electrode of the sixth NMOS tube, and a common end of the fifth NMOS tube is used as the first bias voltage output end and is respectively connected with a drain electrode of the eighth PMOS tube and a drain electrode of the fifth NMOS tube;
the drain electrode of the third NMOS tube is connected with the grid electrode, the common end of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the source electrode of the third NMOS tube is grounded, the source electrode of the fourth NMOS tube is grounded, one end of the third resistor is connected with the source electrode of the fifth NMOS tube, the other end of the third resistor is grounded, one end of the fourth resistor is connected with the source electrode of the sixth NMOS tube, and the other end of the fourth resistor is grounded.
9. The low dropout regulator of claim 8, wherein the ninth PMOS transistor has a width-to-length ratio M times that of the sixth PMOS transistor, the fifth NMOS transistor has a width-to-length ratio M times that of the second NMOS transistor, and the third resistor and the fourth resistor have the same resistance, wherein M is a positive rational number.
10. A laser ranging circuit comprising a low dropout regulator according to any one of claims 1 to 9.
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