CN111338413A - A Low Dropout Linear Regulator with High Power Supply Rejection Ratio - Google Patents

Abstract

A low dropout linear regulator with high power supply rejection ratio is provided with an auxiliary module and a buffer stage which are connected with the output end of an error amplifier and the control end of a power switch tube, wherein the power switch tube is scaled down and copied in the auxiliary module to obtain a first switch tube, the first switch tube flows through the current of a first direct current source and forms a current mirror structure with a second switch tube, and the current of the mirror image of the second switch tube generates voltage drop on a first resistor to obtain an auxiliary voltage signal which is connected with the inverting input end of a first operational amplifier; the first operational amplifier, the second resistor and the third resistor form a proportional amplification circuit to process the auxiliary voltage signal and output the auxiliary voltage signal to the buffer stage; when the grid voltage of the power switch tube is increased or decreased, the buffer stage reduces or increases the load current flowing through the power switch tube, so that the output voltage of the low dropout linear regulator is decreased or increased, and the change of the output voltage is counteracted; and the grid voltage of the power switch tube does not change along with the change of the power supply ripple, thereby realizing high power supply rejection ratio.

Description

A Low Dropout Linear Regulator with High Power Supply Rejection Ratio

technical field

The invention belongs to the technical field of electronic circuits, and relates to a low-dropout linear voltage regulator circuit with high power supply rejection ratio.

Background technique

As shown in Figure 1, the traditional low-dropout linear regulator circuit is usually placed in front of the power receiving unit. The typical low-dropout linear regulator structure generally consists of a voltage reference source VREF, an error amplifier EA, a power transistor MP, and a feedback network. Rf1 and Rf2 are composed. Its working principle is as follows: use the negative feedback system to sample the output voltage, then compare it with the reference voltage, and stabilize the output voltage Vout through the adjustment of the loop. The error amplifier EA is used to compare the sampled voltage with the reference voltage; the power transistor is the channel through which the load current flows, and the strength of its conduction is controlled through a negative feedback loop, usually using a PMOS tube.

However, in the traditional low dropout linear regulator circuit, when the output voltage Vout increases, the feedback voltage after passing through the resistor divider feedback network will also increase, resulting in an increase in the output voltage of the error amplifier, making the low dropout linear regulator circuit. The output voltage is unstable. In addition, in the traditional low-dropout linear regulator circuit, there is ripple and noise on the power supply flowing into the load through the power transistor and coupled to the gate terminal of the power transistor, and then converted into the current of the output terminal through the large transconductance of the power transistor and flowing into the load. , which has a large impact on the power supply rejection ratio of the low dropout linear regulator circuit.

SUMMARY OF THE INVENTION

Aiming at the shortcomings of the above-mentioned traditional low-dropout linear voltage regulators, which have unstable output voltage and great influence on the power supply rejection ratio, the present invention proposes a low-dropout linear voltage regulator circuit with high power supply rejection ratio. A buffer stage and an auxiliary module are added between the output terminal of the error amplifier and the gate terminal of the power transistor to achieve a high power supply rejection ratio of the low dropout linear regulator under the condition that the loop remains stable.

The technical scheme of the present invention is as follows:

A low dropout linear voltage regulator with high power supply rejection ratio, comprising an error amplifier, a power switch tube, a first feedback resistor, a second feedback resistor and a first capacitor,

The inverting input end of the error amplifier is connected to the reference voltage, and its output end is connected to the control end of the power switch tube;

Both ends of the power switch tube are respectively connected to the power supply voltage and the output end of the low-dropout linear regulator;

The first feedback resistor and the second feedback resistor are connected in series and between the output end of the low dropout linear regulator and the ground, and the series point is connected to the non-inverting input end of the error amplifier;

the first capacitor is connected between the output end of the low dropout linear regulator and the ground;

The low dropout linear regulator further includes an auxiliary module and a buffer stage,

The auxiliary module includes a first DC current source, a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor and a first operational amplifier, wherein the first switch tube is the power switch tube press button. Scale down and copy to obtain;

The first switch tube flows through the current of the first DC current source, and forms a current mirror structure with the second switch tube, and the mirrored current of the second switch tube generates a voltage drop on the first resistor to obtain an auxiliary voltage signal;

The inverting input terminal of the first operational amplifier is connected to the auxiliary voltage signal, its non-inverting input terminal is connected to one end of the second resistor and one end of the third resistor, and its output terminal is used as the output terminal of the auxiliary module and is connected to the third resistor. The other end; the other end of the second resistor is grounded;

The buffer stage includes a fourth resistor, a second operational amplifier, a second DC current source, a third DC current source, a ninth PMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor,

One end of the fourth resistor is connected to the output end of the auxiliary module, and the other end is connected to the inverting input end of the second operational amplifier;

The gate of the ninth PMOS tube is connected to the non-inverting input terminal and the output terminal of the second operational amplifier, its source is connected to the second DC current source, and its drain is connected to the gate and drain of the fifth NMOS tube and the sixth NMOS tube. grid;

The source of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor and grounded, and its drain serves as the output end of the buffer stage and is connected to the second DC current source;

The output end of the buffer stage is connected to the control end of the power switch tube.

Specifically, the power switch tube is a PMOS power tube, the gate of the PMOS power tube is used as the control end of the power switch tube to connect the output end of the error amplifier and the output end of the buffer stage, and its source is connected to the power supply voltage, Its drain is connected to the output terminal of the low dropout linear regulator.

Specifically, the first switch tube is a seventh PMOS tube, the second switch tube is an eighth PMOS tube, and the gate-drain of the seventh PMOS tube is short-circuited and connected to the gate of the eighth PMOS tube and the first DC current source, Its source is connected to the source of the eighth PMOS transistor and is connected to the power supply voltage; one end of the first resistor is grounded, and the other end is connected to the drain of the eighth PMOS transistor and outputs the auxiliary voltage signal.

Specifically, the power switch tube is an NMOS power tube, and the gate of the NMOS power tube is used as the control end of the power switch tube to connect the output end of the error amplifier and the output end of the buffer stage, and its drain is connected to the power supply voltage, Its source is connected to the output end of the low dropout linear regulator.

Specifically, the first switch tube is a seventh NMOS tube, the second switch tube is an eighth NMOS tube, and the gate-drain of the seventh NMOS tube is short-circuited and connected to the gate of the eighth NMOS tube and the first DC current source, Its source is connected to the source of the eighth NMOS transistor and grounded; one end of the first resistor is connected to the power supply voltage, and the other end is connected to the drain of the eighth NMOS transistor and outputs the auxiliary voltage signal.

Specifically, the error amplifier includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS tube, sixth PMOS tube and fourth DC current source,

The gate of the third PMOS transistor is used as the inverting input terminal of the error amplifier, its source is connected to the source of the fourth PMOS transistor and the drain of the second PMOS transistor, and its drain is connected to the gate of the first NMOS transistor and the drain of the second PMOS transistor. the drain, the gate of the second NMOS transistor and the gate of the fourth NMOS transistor;

The gate of the fourth PMOS transistor is used as the non-inverting input terminal of the error amplifier, and its drain is connected to the drain of the second NMOS transistor and the gate of the third NMOS transistor;

The gate-drain of the first PMOS tube is short-circuited and connected to the gate of the second PMOS tube and the fourth DC current source, and its source is connected to the sources of the second PMOS tube, the fifth PMOS tube and the sixth PMOS tube and is connected to the power supply voltage ;

The gate of the sixth PMOS tube is connected to the drain of the third NMOS tube and the gate and drain of the fifth PMOS tube, and the drain of the sixth PMOS tube is connected to the drain of the fourth NMOS tube and serves as the output end of the error amplifier;

The sources of the first NMOS transistor, the second NMOS transistor and the fourth NMOS transistor are grounded.

The beneficial effects of the present invention are as follows: the present invention introduces a buffer stage and an auxiliary module into the low-dropout linear regulator, which can realize that when the input power supply voltage is higher than the set voltage, the output power supply voltage is constant to the set output voltage, the output voltage is stabilized, and The output power voltage is less affected by temperature changes and process deviations, and at the same time, it can provide a cleaner power supply voltage with less power ripple to the power receiving unit.

Description of drawings

FIG. 1 is a schematic diagram of the circuit structure of a conventional low-dropout linear regulator.

FIG. 2 is a block diagram of the realization of a low dropout linear voltage regulator with a high power supply rejection ratio provided by the present invention when the power transistor switching transistor is a PMOS power transistor.

FIG. 3 is a structural diagram of a circuit implementation of an error amplifier in a low dropout linear voltage regulator with a high power supply rejection ratio provided by the present invention.

4 is a schematic structural diagram of a realization circuit of an auxiliary module and a buffer stage of a low dropout linear regulator with a high power supply rejection ratio provided by the present invention when the power transistor switch is a PMOS power transistor.

FIG. 5 is a block diagram of the implementation of a low dropout linear voltage regulator with a high power supply rejection ratio provided by the present invention when the power transistor switching transistors are NMOS power transistors.

6 is a schematic structural diagram of a realization circuit of an auxiliary module and a buffer stage of a low dropout linear voltage regulator with a high power supply rejection ratio provided by the present invention when the power tube switch tube is an NMOS power tube.

Detailed ways

The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

The present invention proposes a low dropout linear voltage regulator with high power supply rejection ratio, which includes an error amplifier, a power switch tube, a first feedback resistor R ₆ , a second feedback resistor R ₇ and a first capacitor _CL . The input terminal is connected to the reference voltage V _REF , and the output terminal is connected to the control terminal of the power switch tube; the two ends of the power switch tube are respectively connected to the power supply voltage V _DD and the output terminal of the low _- dropout linear regulator; The feedback resistor _R7 forms a feedback network in series and is connected between the output end of the low dropout linear regulator and the ground, and its series point is connected to the non-inverting input end of the error amplifier; the first capacitor _CL is connected to the low dropout linear regulator. between the output and ground.

Among them, the power switch tube generally chooses a PMOS tube. As shown in Figure 2, the power switch tube is a _PMOS power tube MP, and the gate of the _PMOS power tube MP is used as the control end of the power switch tube to connect the output end of the error amplifier and the buffer stage. The output terminal, its source is connected to the power supply voltage V _DD , and its drain is connected to the output terminal of the low-dropout linear regulator.

In some cases, the power switch tube can also be an NMOS tube. As shown in FIG. 5 , the power switch tube is an _NMOS power tube MN , and the gate of the _NMOS power tube MN is used as the control end of the power switch tube and is connected to the output end of the error amplifier. and the output of the buffer stage, the drain of which is connected to the supply voltage V _DD and the source of which is connected to the output of the low dropout linear regulator.

The working principle of the low-dropout linear regulator proposed by the present invention is as follows: after the input power supply Vin, that is, the power supply voltage V _DD , is powered on, the output voltage Vout of the low-dropout linear regulator is sampled by the negative feedback system, and then compared with the reference voltage. That is, the reference voltage V _REF is compared, and the output voltage Vout is stabilized through the adjustment of the loop. The error amplifier is used to compare the sampled voltage with the reference voltage V _REF ; the power switch tube (take the _PMOS power tube MP as an example) is the channel through which the load current flows, and the strength of its conduction is controlled through a negative feedback loop .

When the output voltage Vout increases, the feedback voltage VFB after passing through the resistor divider feedback network will also increase, and the output voltage of the error amplifier will increase, causing the output of the low dropout linear regulator to be unstable. In the present invention, a buffer stage is provided, and the buffer stage is a non-inverting buffer, so the gate voltage of the _PMOS power transistor MP increases, thereby reducing the load current flowing through the _PMOS power transistor MP, so that the output voltage Vout decreases, thereby offsetting Variation in the rise of the output voltage Vout. Similarly, when the output voltage Vout decreases, the load current flowing through the _PMOS power transistor MP increases after loop control, thereby increasing the output voltage Vout, and finally the output voltage Vout is stabilized. In practice, the output impedance of the _PMOS power transistor MP is not infinite, so there will be ripple and noise on the power supply flowing into the load through the output impedance r _ds of the _PMOS power transistor MP and the capacitance C _db between the drain and the substrate, And the gate-source capacitance C _gs of the _PMOS power tube MP is coupled to the gate terminal of the power tube, and then converted into the current of the output terminal through the large transconductance of the power tube, which flows into the load. The above two points will greatly affect the low-voltage dropout. Linear stability Therefore, the present invention proposes an auxiliary module combined with a buffer stage to improve the power supply rejection ratio of the low-dropout linear voltage regulator circuit.

The auxiliary module includes a first DC current source I0, a first switch tube, a second switch tube, a first resistor R2, a second resistor R3, a third resistor R4 and a first operational amplifier OP1, wherein the first switch tube is a power switch The tube is scaled down and copied; the first switch tube flows through the current of the first DC current source I0, and forms a current mirror structure with the second switch tube, and the mirrored current of the second switch tube produces a voltage drop on the first resistor R2 to obtain Auxiliary voltage signal; the inverting input end of the first operational amplifier OP1 is connected to the auxiliary voltage signal, its non-inverting input end is connected to one end of the second resistor R3 and one end of the third resistor R4, and its output end is used as the output end of the auxiliary module and is connected to the first The other end of the three resistors R4; the other end of the second resistor R3 is grounded.

The first switch tube and the second switch tube form a current mirror structure, and the first switch tube is obtained by scaling down the power switch tube, so when the power switch tube is a PMOS tube, the first switch tube and the second switch tube are also It is a PMOS tube, as shown in FIG. 4 , the first switch tube is the seventh PMOS tube MP6, the second switch tube is the eighth PMOS tube MP7, and the gate-drain of the seventh PMOS tube MP6 is short-circuited and connected to the eighth PMOS tube MP7. The gate and the first DC current source I0, the source of which is connected to the source of the eighth PMOS transistor MP7 and the power supply voltage VDD; one end of the first resistor R2 is grounded, and the other end is connected to the drain of the eighth PMOS transistor MP7 and outputs an auxiliary voltage Signal.

Therefore, when the power switch tube is an NMOS tube, the first switch tube and the second switch tube are also NMOS tubes. As shown in FIG. 6 , the first switch tube is the seventh NMOS tube MN6, and the second switch tube is the eighth NMOS tube. MP7, the gate-drain of the seventh NMOS transistor MN6 is short-circuited and connected to the gate of the eighth NMOS transistor MP7 and the first DC current source I0, and its source is connected to the source of the eighth NMOS transistor MP7 and grounded; one end of the first resistor R2 The power supply voltage VDD is connected, and the other end is connected to the drain of the eighth NMOS transistor MP7 and outputs an auxiliary voltage signal.

As shown in FIG. 4 and FIG. 6 , the buffer stage includes a fourth resistor R5, a second operational amplifier OP2, a second DC current source I1, a third DC current source I2, a ninth PMOS transistor, a fifth NMOS transistor MN4 and a sixth NMOS transistor MN5, one end of the fourth resistor R5 is connected to the output end of the auxiliary module, and the other end is connected to the inverting input end of the second operational amplifier OP2; the gate of the ninth PMOS transistor is connected to the non-inverting input end and output of the second operational amplifier OP2 terminal, its source is connected to the second DC current source I1, its drain is connected to the gate and drain of the fifth NMOS transistor MN4 and the gate of the sixth NMOS transistor MN5; the source of the sixth NMOS transistor MN5 is connected to the fifth NMOS The source of the tube MN4 is grounded, and its drain serves as the output end of the buffer stage and is connected to the second DC current source I1; the output end of the buffer stage is connected to the control end of the power switch tube.

Under the condition of medium and low frequency, increasing the loop gain of the low dropout linear regulator circuit can effectively improve the power supply rejection ratio. However, under high frequency conditions, since there is no large off-chip capacitor to filter the power supply noise, it is necessary to design an auxiliary circuit to enhance the performance of the power supply rejection ratio PSR at high frequencies. The main factors that affect the power supply rejection ratio at high frequencies are the small signal path from the power supply to the output and the voltage divider due to the limited output impedance of the power switch. The invention designs a path, and injects the signal into the gate terminal of the power switch tube through a buffer for compensation, so that the gate voltage of the power tube does not change with the change of the power supply ripple, that is, under AC conditions, the gate of the power tube will not change. The voltage is 0, so as to ensure that it can suppress the power supply ripple.

Taking the power switch tube as the _PMOS power tube MP as an example, the specific implementation method is to design a seventh _PMOS tube MP6 that is scaled down and copied with the PMOS power tube MP in the buffer stage and the auxiliary module, and flows through the seventh PMOS tube MP6. The drain current of the PMOS transistor MP6 affected by the power supply ripple is:

Wherein, _{id_mp6} is the drain current of the seventh PMOS transistor MP6 affected by the power supply ripple, C _gdr is the gate-drain capacitance of the seventh PMOS transistor MP6, C _gsr is the gate-source capacitance of the seventh PMOS transistor MP6, g _mp6 is the transconductance of the seventh PMOS transistor MP6, and r _dsmp6 is the output resistance of the seventh PMOS transistor MP6.

Since the second term in the above formula is much smaller than the first term, it can be considered that

The current signal _{id_mp6} can effectively track the change of the power supply ripple. After the current passes through the current mirror formed by the seventh PMOS transistor MP6 and the eighth PMOS transistor MP7, the size is still sC _gdr V _dd , and is generated on the first resistor R2 A voltage drop with a size of sC _gdr V _dd R2, through the proportional amplification circuit composed of the first operational amplifier OP1, the second resistor R3 and the third resistor R4, the amplified voltage is sC _gdr V _dd R2*(1 +R4/R3), the value obtained by the amplified signal through the voltage follower formed by the second operational amplifier OP2 is still sC _gdr V _dd R2*(1+R4/R3), and the signal passes through the ninth PMOS tube The transconductance of MP8 is converted into a current signal sC _gdr V _dd R2*(1+R4/R3)*g _mp8 , by appropriately designing the proportional relationship between the first resistor R2, the second resistor R3 and the third resistor R4 and the ninth PMOS tube MP8, you can get

C _gd is the gate-drain capacitance of the _PMOS power transistor MP, and g _mp8 is the transconductance of the ninth PMOS transistor MP8.

The sC _gd V _dd signal reaches the output end of the buffer stage through the current mirror formed by the fifth NMOS transistor MN4 and the sixth NMOS transistor MN5, and is injected from the output end of the buffer stage to the gate of the _PMOS power transistor MP for Can offset the small signal path from the power supply to the output and the voltage divider due to the limited output impedance of the power switch tube, so as to achieve the function of improving the power supply rejection ratio.

As shown in FIG. 3, an implementation structure of the error amplifier is given. In addition, other voltage amplifiers with suitable input common-mode voltage can also be used. In this embodiment, the error amplifier includes a first NMOS transistor MN0, a second NMOS transistor MN1, a Three NMOS transistors MN2, fourth NMOS transistor MN3, first PMOS transistor MP0, second PMOS transistor MP1, third PMOS transistor, fourth PMOS transistor MP3, fifth PMOS transistor MP4, sixth PMOS transistor MP5 and fourth DC current Source, the gate of the third PMOS transistor is used as the inverting input terminal of the error amplifier, its source is connected to the source of the fourth PMOS transistor MP3 and the drain of the second PMOS transistor MP1, and its drain is connected to the first NMOS transistor MN0. The gate and drain, the gate of the second NMOS transistor MN1 and the gate of the fourth NMOS transistor MN3; the gate of the fourth PMOS transistor MP3 is used as the non-inverting input terminal of the error amplifier, and its drain is connected to the second NMOS transistor MN1. The drain and the gate of the third NMOS transistor MN2; the gate-drain of the first PMOS transistor MP0 is short-circuited and connected to the gate of the second PMOS transistor MP1 and the fourth DC current source, and its source is connected to the second PMOS transistor MP1, the first The sources of the five PMOS transistors MP4 and the sixth PMOS transistor MP5 are connected to the power supply voltage VDD; the gate of the sixth PMOS transistor MP5 is connected to the drain of the third NMOS transistor MN2 and the gate and drain of the fifth PMOS transistor MP4. The drain is connected to the drain of the fourth NMOS transistor MN3 and serves as the output terminal of the error amplifier; the sources of the first NMOS transistor MN0, the second NMOS transistor MN1 and the fourth NMOS transistor MN3 are grounded.

In summary, the present invention reduces or increases the load current flowing through the power switch tube when the gate voltage of the power switch tube increases or decreases by setting the buffer stage and the auxiliary module, so that the low dropout linear regulator can be achieved. The output voltage drops or rises, so as to offset the change of the output voltage. The output power supply voltage is less affected by temperature changes and process deviations, and a stable output voltage is achieved; in addition, the signal is injected into the gate terminal of the power switch tube through the buffer stage. Compensation, so that the gate voltage of the power switch tube does not change with the change of the power supply ripple, realizes the function of suppressing the power supply ripple, and improves the power supply suppression ratio.

Those skilled in the art can make various other specific modifications and combinations without departing from the essence of the present invention according to the technical teaching disclosed in the present invention, and these modifications and combinations still fall within the protection scope of the present invention.

Claims (6)

1. A low dropout regulator with high power supply rejection ratio comprises an error amplifier, a power switch tube, a first feedback resistor, a second feedback resistor and a first capacitor,

the inverting input end of the error amplifier is connected with the reference voltage, and the output end of the error amplifier is connected with the control end of the power switch tube;

two ends of the power switch tube are respectively connected with the power voltage and the output end of the low dropout linear regulator;

the first feedback resistor and the second feedback resistor are connected in series and are connected between the output end of the low-dropout linear voltage regulator and the ground, and the series point of the first feedback resistor and the second feedback resistor is connected with the non-inverting input end of the error amplifier;

the first capacitor is connected between the output end of the low dropout linear regulator and the ground;

characterized in that the low dropout regulator further comprises an auxiliary module and a buffer stage,

the auxiliary module comprises a first direct current source, a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor and a first operational amplifier, wherein the first switch tube is obtained by scaling down and copying the power switch tube;

the first switching tube flows through the current of the first direct current source and forms a current mirror structure with the second switching tube, and the current mirrored by the second switching tube generates voltage drop on the first resistor to obtain an auxiliary voltage signal;

the inverting input end of the first operational amplifier is connected with the auxiliary voltage signal, the non-inverting input end of the first operational amplifier is connected with one end of the second resistor and one end of the third resistor, and the output end of the first operational amplifier is used as the output end of the auxiliary module and connected with the other end of the third resistor; the other end of the second resistor is grounded;

the buffer stage comprises a fourth resistor, a second operational amplifier, a second direct current source, a third direct current source, a ninth PMOS tube, a fifth NMOS tube and a sixth NMOS tube,

one end of the fourth resistor is connected with the output end of the auxiliary module, and the other end of the fourth resistor is connected with the inverting input end of the second operational amplifier;

the grid electrode of the ninth PMOS tube is connected with the non-inverting input end and the output end of the second operational amplifier, the source electrode of the ninth PMOS tube is connected with the second direct current source, and the drain electrode of the ninth PMOS tube is connected with the grid electrode and the drain electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube;

the source electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube and is grounded, and the drain electrode of the sixth NMOS tube is used as the output end of the buffer stage and is connected with a second direct current source;

and the output end of the buffer stage is connected with the control end of the power switch tube.

2. The low dropout regulator according to claim 1, wherein the power switch is a PMOS power transistor, a gate of the PMOS power transistor is used as a control terminal of the power switch to connect the output terminal of the error amplifier and the output terminal of the buffer stage, a source of the PMOS power transistor is connected to the power voltage, and a drain of the PMOS power transistor is connected to the output terminal of the low dropout regulator.

3. The low dropout regulator with high power supply rejection ratio according to claim 2, wherein the first switching tube is a seventh PMOS tube, the second switching tube is an eighth PMOS tube, the gate-drain short circuit of the seventh PMOS tube connects the gate of the eighth PMOS tube and the first direct current power supply, and the source of the seventh PMOS tube is connected to the source of the eighth PMOS tube and the power supply voltage; one end of the first resistor is grounded, and the other end of the first resistor is connected with the drain electrode of the eighth PMOS tube and outputs the auxiliary voltage signal.

4. The low dropout regulator according to claim 1, wherein the power switch is an NMOS power transistor, a gate of the NMOS power transistor is used as a control terminal of the power switch to connect the output terminal of the error amplifier and the output terminal of the buffer stage, a drain of the NMOS power transistor is connected to the power voltage, and a source of the NMOS power transistor is connected to the output terminal of the low dropout regulator.

5. The low dropout regulator according to claim 4, wherein the first switching transistor is a seventh NMOS transistor, the second switching transistor is an eighth NMOS transistor, a gate-drain short circuit of the seventh NMOS transistor connects a gate of the eighth NMOS transistor and the first dc current source, and a source of the seventh NMOS transistor is connected to a source of the eighth NMOS transistor and grounded; one end of the first resistor is connected with a power supply voltage, and the other end of the first resistor is connected with the drain electrode of the eighth NMOS tube and outputs the auxiliary voltage signal.

6. The low dropout regulator with high power supply rejection ratio according to any one of claims 1 to 5, wherein said error amplifier comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor and a fourth DC current source,

the grid electrode of the third PMOS tube is used as the inverting input end of the error amplifier, the source electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is connected with the grid electrode and the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fourth NMOS tube;

the grid electrode of the fourth PMOS tube is used as the non-inverting input end of the error amplifier, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube;

the grid-drain short circuit of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the fourth direct current source, and the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the fifth PMOS tube and the sixth PMOS tube and is connected with power supply voltage;

the grid electrode of the sixth PMOS tube is connected with the drain electrode of the third NMOS tube and the grid electrode and the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth NMOS tube and serves as the output end of the error amplifier;

the source electrodes of the first NMOS tube, the second NMOS tube and the fourth NMOS tube are grounded.

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