CN104750148A - Low-dropout regulator - Google Patents
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- CN104750148A CN104750148A CN201310753547.4A CN201310753547A CN104750148A CN 104750148 A CN104750148 A CN 104750148A CN 201310753547 A CN201310753547 A CN 201310753547A CN 104750148 A CN104750148 A CN 104750148A
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- 239000004065 semiconductor Substances 0.000 abstract 2
- 230000001052 transient effect Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000005405 multipole Effects 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 230000009897 systematic effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003278 mimic effect Effects 0.000 description 1
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Abstract
The invention provides a low-dropout regulator. The low-dropout regulator comprises a primary error amplifier, a secondary error amplifier, a main Miller compensation capacitor, an auxiliary Miller compensation capacitor, a sixth PMOS (positive-channel metal-oxide-semiconductor) tube, a zeroing resistor, a first resistor and a second resistor, wherein the secondary error amplifier comprises a fourth PMOS tube, a fifth PMOS tube, a third NMOS (negative-channel metal-oxide-semiconductor) tube, a fourth NMOS tube and a fifth NMOS tube, the inverting input end of the primary error amplifier is connected with the reference voltage end, the non-inverting input end of the primary error amplifier is connected with the feedback voltage end, one end of the main Miller compensation capacitor is connected with the output end of the primary error amplifier, the other end of the main Miller compensation capacitor is connected with the voltage output end, the auxiliary Miller compensation capacitor is serially connected between a drain electrode of the fifth PMOS tube and the voltage output end. The low-dropout regulator has the advantages that overshoot of the LDO (low-dropout regulator) can be reduced, and response speed of the LDO can be increased.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of low pressure difference linear voltage regulator.
Background technology
SOC (system on a chip) (SOC, System-On-a-Chip) achieves integrates several functions module on a single chip, and as central processing unit, simulation and digital baseband processor, RF transmit-receive circuit etc., several functions module brings the demand of many grades of Power supplies.
Low pressure difference linear voltage regulator (LDO, Low Dropout Regulator) power supply of output ripple and low can be provided for the noise-sensitive such as mimic channel and radio circuit, and structure is relatively simple, peripheral component is few, is thus widely used in the SOC systems such as flash memory (FLASH).
Traditional LDO adopts large external capacitor usually, and this large external capacitor can not only maintain loop stability, and can play good transient response performance when SOC system workload state frequent variations (read-write operation as FLASH); But this large external capacitor is unfavorable for the integrated of SOC system; Therefore, realizing good transient response function when not using large external capacitor, is technical matters urgently to be resolved hurrily in this area.
For solving the problems of the technologies described above, prior art applies the active feedback of an enhancement mode to improve frequency response, the structural representation of a kind of low pressure difference linear voltage regulator of prior art is shown with reference to Fig. 1, wherein, M1, M2, Mb1, M7, M8, M5, M6, M3, M4 constitutes the error amplifier of folded common source and common grid, M9, M11, M12, M10 constitutes the second gain stage, MP0 is power tube, be mainly used in providing output current, Rf1 and Rf2 is potential-divider network, Vout is output voltage terminal, Mt1, Ct1 forms a voltage-controlled phase-shift circuit (RC circuit, resistor – capacitor circuit) network, Mk2, Ck1, Mk1, Mk2 forms the corrective network of the second level, Mf is feedforward level, Vb1 and Vb3 represents bias voltage input, VD represents input supply terminal, Vref represents reference voltage terminal.
Circuit shown in Fig. 1 can improve frequency response performance to a certain extent, but, when load transient changes, transient current required when not having enough electric capacity can provide transient load saltus step, the response time of whole voltage stabilizing feedback control loop is slow simultaneously, cause output voltage Vout can produce very large overshoot (overshoot) along with the change of load current, the technical grade index of high-performance stabilized voltage supply design cannot be met.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of low pressure difference linear voltage regulator, effectively can reduce the overshoot of LDO, and can strengthen the response speed of LDO.
In order to solve the problem, the invention discloses a kind of low pressure difference linear voltage regulator, comprising: first order error amplifier, second level error amplifier, main miller-compensated electric capacity, auxiliary miller-compensated electric capacity, the 6th PMOS, zero-regulator resistor, zeroing electric capacity, the first resistance and the second resistance;
Wherein, described second level error amplifier comprises: the 4th PMOS, the 5th PMOS, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube;
The reverse input end of described first order error amplifier is connected with reference voltage end, and in-phase input end is connected with feedback voltage end;
The output terminal of first order error amplifier described in one termination of the miller-compensated electric capacity of described master, another termination voltage output end;
The grid of described 3rd NMOS tube connects the output terminal of described first order error amplifier, grounded drain; The grid of described 4th PMOS connects described zero-regulator resistor and zeroing electric capacity, and source electrode connects described zero-regulator resistor, the source electrode of described 3rd NMOS tube and the grid of described 5th PMOS; The source electrode of described 6th PMOS connects described voltage output end, and drain electrode connects input power; The drain electrode of described zeroing electric capacity and described 4th PMOS, the 5th PMOS and the 6th PMOS connects input power; The grid of described 4th NMOS tube connects the second bias voltage input, and source electrode connects the drain electrode of described 5th NMOS tube, grounded drain; The grid of described 5th NMOS tube connects the first bias voltage input, and source electrode connects the source electrode of described 5th PMOS and the drain electrode of described 6th PMOS, and drain electrode connects described auxiliary miller-compensated electric capacity;
Described auxiliary miller-compensated capacitance series is between the drain electrode and described voltage output end of described 5th PMOS;
Described first resistance and the second resistance are concatenated into resistance pressure-dividing network, a termination voltage output end of this resistance pressure-dividing network, other end ground connection, in indirect described feedback voltage end.
Preferably, described first order error amplifier comprises: the first PMOS, the second PMOS, the 3rd PMOS, the first NMOS tube and the second NMOS tube;
Wherein, the grid of described first PMOS connects feedback voltage end, and source electrode connects the source electrode of described first NMOS tube and the grid of the second NMOS tube; The grid of described second PMOS connects feedback voltage end, and source electrode connects the output terminal of described first order error amplifier; The grid of described 3rd PMOS connects the 3rd bias voltage input, and source electrode connects the drain electrode of described first PMOS and described second PMOS, and drain electrode connects input power; The grid of described second NMOS tube connects the grid of described first NMOS tube, and source electrode connects the output terminal of described first order error amplifier, grounded drain; The grounded drain of described first NMOS tube.
Compared with prior art, the present invention has the following advantages:
The present invention adopts auxiliary miller-compensated electric capacity and the 5th NMOS tube to form current buffering feedback in LDO, and, introduce an active zero point by zero-regulator resistor Rz, zeroing electric capacity Cz and the 4th PMOS MP4;
On the one hand, when the voltage of voltage output end out reduces because of load transient change time, the source electrode of the 5th NMOS tube can reduce suddenly, this makes the electric current flowing through the 5th NMOS tube increase suddenly, the grid voltage of the 6th PMOS to be dragged down and without the need to through amplifier stage, thus auxiliary miller-compensated electric capacity, the 5th NMOS tube can be exported to the fast path of the 6th PMOS; And this responds the transient state loop bandwidth that path can increase LDO fast, strengthen the output transient response of LDO, therefore, it is possible to reduce the size of output spike voltage, also namely effectively can reduce the overshoot of LDO;
On the other hand, can control Rz and Cz be passed through, make the absolute value at this active zero point be less than the absolute value of the second limit in LDO, to realize with offsetting this second limit this active zero point; In addition, the mutual conductance of miller-compensated electric capacity and the 5th NMOS tube can be assisted by control, to realize with above-mentioned auxiliary miller-compensated electric capacity C
m2the higher order pole in LDO is offset with the zero point of the 5th NMOS tube MN5 introducing; And after stating two counteractings in realization, second limit of LDO and higher order pole are cancelled, and can regard LDO as and only have first limit, the bandwidth due to first order pole is certain to the bandwidth being greater than multipole point, therefore the loop bandwidth of LDO can be increased, the response speed of reinforcing feedback;
To sum up, the present invention when not increasing power consumption and without the need to large external capacitor, can improve the response speed of LDO greatly.After tested, the maximum load electric capacity of LDO when stable of the present embodiment is 200pF, therefore, is very applicable to SOC systematic difference.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of a kind of LDO of prior art;
Fig. 2 is the structural drawing of a kind of low pressure difference linear voltage regulator embodiment 1 of the present invention;
Fig. 3 is the structural drawing of a kind of low pressure difference linear voltage regulator embodiment 2 of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
With reference to Fig. 2, show the structural drawing of a kind of low pressure difference linear voltage regulator embodiment 1 of the present invention, specifically can comprise: first order error amplifier U1, second level error amplifier, main miller-compensated electric capacity C
m1, auxiliary miller-compensated electric capacity C
m2, the 6th PMOS MP6, zero-regulator resistor Rz, zeroing electric capacity Cz, the first resistance R1 and the second resistance R2;
Wherein, described second level error amplifier specifically can comprise: the 4th PMOS MP4, the 5th PMOS MP5, the 3rd NMOS tube MN3, the 4th NMOS tube MN4 and the 5th NMOS tube MN5;
The reverse input end of described first order error amplifier U1 is connected with reference voltage end Vref, and in-phase input end is connected with feedback voltage end V120;
The miller-compensated electric capacity C of described master
m1a termination described in the output terminal of first order error amplifier U1, another termination voltage output end out;
The grid of described 3rd NMOS tube MN3 connects the output terminal of described first order error amplifier U1, grounded drain; The grid of described 4th PMOS MP4 meets described zero-regulator resistor Rz and zeroing electric capacity Cz, and source electrode connects described zero-regulator resistor Rz, the source electrode of described 3rd NMOS tube MN3 and the grid of described 5th PMOS MP5; The source electrode of described 6th PMOS MP6 meets described voltage output end out, and drain electrode connects input power; The drain electrode of described zeroing electric capacity Cz and described 4th PMOS MP4, the 5th PMOS MP5 and the 6th PMOS MP6 connects input power; The grid of described 4th NMOS tube MN4 meets the second bias voltage input VB2, and source electrode connects the drain electrode of described 5th NMOS tube MN5, grounded drain; The grid of described 5th NMOS tube MN5 meets the first bias voltage input VB1, and source electrode connects the source electrode of described 5th PMOS MP5 and the drain electrode of described 6th PMOS MP6, and drain electrode meets described auxiliary miller-compensated electric capacity C
m2;
Described auxiliary miller-compensated electric capacity C
m2between the drain electrode being serially connected in described 5th PMOS MP5 and described voltage output end out;
Described first resistance R1 and the second resistance R2 is concatenated into resistance pressure-dividing network, a termination voltage output end out of this resistance pressure-dividing network, other end ground connection, in indirect described feedback voltage end V120.
The low pressure difference linear voltage regulator of the embodiment of the present invention can be applied in the SOC systems such as flash memory (flash memory), to play, its volume is little, outward element is little, low-power consumption, interference is little, output noise is low, easy to use, cheap advantage.
The present embodiment mainly can comprise three grades of structure for amplifying, and described three grades of structure for amplifying specifically can comprise: the second amplifier stage that the first amplifier stage that first order error amplifier U1 is corresponding, second level error amplifier are corresponding and the 3rd amplifier stage that the 6th PMOS MP6, the first resistance R1 and the second resistance R2 are formed.
In the present embodiment, auxiliary miller-compensated electric capacity C
m2current buffering feedback (current buffer feedback) is formed with the 5th NMOS tube MN5, when the voltage of voltage output end out reduces because of load transient change time, the source electrode of the 5th NMOS tube MN5 also can reduce suddenly, this can make the electric current flowing through the 5th NMOS tube MN5 increase suddenly, the grid voltage of the 6th PMOS MP6 to be dragged down and without the need to through amplifier stage, thus auxiliary miller-compensated electric capacity C can be exported
m2, the 5th NMOS tube MN5 to the 6th PMOS MP6 fast path; And this responds the transient state loop bandwidth that path can increase LDO fast, strengthen the output transient response of LDO, therefore, it is possible to reduce the size of output spike voltage, also namely effectively can reduce the overshoot of LDO.
In addition, in actual applications, because the size of usual 6th PMOS MP6 is very large, therefore the corresponding limit of the 6th PMOS MP6 grid is very near initial point, easily cause LDO unstable, now can only shift onto with stabilizing circuit beyond bandwidth by corresponding for the 6th PMOS MP6 grid limit by increasing power consumption, this just causes the power consumption of circuit very large.
For the problems referred to above, the present embodiment creatively introduces an active zero point to eliminate limit corresponding to the 6th PMOS MP6 grid, specifically can comprise zero-regulator resistor Rz, zeroing electric capacity Cz and the 4th PMOS MP4 this active zero point.
In the performance such as response characteristic, stability of the zero-pole analysis LDO system of this foundation LDO.
The limit of the present embodiment specifically can comprise: the first limit, the second limit and higher order pole; Wherein, the first limit is main miller-compensated electric capacity C
m1the Miller effect introduce, its value is very little, almost near initial point, supposes to use C
∑represent gain and the C of the second amplifier stage and the 3rd amplifier stage
m1product, so the first limit is exactly C
∑with the inverse of the product of amplifier stage output resistance; Second limit is the corresponding limit of above-mentioned 6th PMOS MP6 grid, and its numerical value can be approximated to be (C
m2/ C
2) * (g
m3/ C
l), wherein, g
m3be the mutual conductance of the 3rd amplifier stage, C
2the output stray capacitance of the second error amplifier, C
lrepresent total load output capacitance.
The zero point of the present embodiment specifically can comprise: above-mentioned active zero point and auxiliary miller-compensated electric capacity C
m2with the zero point that the 5th NMOS tube MN5 introduces; Wherein, the numerical value at above-mentioned active zero point equals the inverse of Rz, Cz product, auxiliary miller-compensated electric capacity C
m2g is equaled with the numerical value at the zero point of the 5th NMOS tube MN5 introducing
m5/ C
m2, wherein, g
m5it is the mutual conductance of the 5th NMOS tube MN5.
In specific implementation, those skilled in the art can according to actual conditions, control Rz and Cz, make the absolute value at above-mentioned active zero point be less than the absolute value of above-mentioned second limit, to realize with offsetting this second limit this active zero point; Such as, Rz can be obtained very large.
In addition, those skilled in the art can also according to actual conditions, control g
m5and C
m2, to realize with above-mentioned auxiliary miller-compensated electric capacity C
m2the zero point of introducing with the 5th NMOS tube MN5 offsets above-mentioned higher order pole.
After stating two counteractings in realization, second limit of the present embodiment and higher order pole are cancelled, and can regard LDO as and only have first limit, the bandwidth due to first order pole is certain to the bandwidth being greater than multipole point, therefore the loop bandwidth of LDO can be increased, the response speed of reinforcing feedback.
To sum up, the present embodiment when not increasing power consumption and without the need to large external capacitor, can improve the response speed of LDO greatly.After tested, the maximum load electric capacity of LDO when stable of the present embodiment is 200pF, therefore, is very applicable to SOC systematic difference.
With reference to Fig. 3, show the alternate configurations figure of a kind of low pressure difference linear voltage regulator embodiment 2 of the present invention.The low pressure difference linear voltage regulator of the present embodiment, on above-mentioned basis embodiment illustrated in fig. 2, can also comprise following alternatives further.
As shown in Figure 3, first error amplifier of the present embodiment specifically can comprise: the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the first NMOS tube MN1 and the second NMOS tube MN2;
Wherein, the grid of described first PMOS MP1 meets feedback voltage end V120, and source electrode connects the source electrode of described first NMOS tube MN1 and the grid of the second NMOS tube MN2; The grid of described second PMOS MP2 meets feedback voltage end Vref, and source electrode connects the output terminal of described first order error amplifier, this output terminal and main miller-compensated electric capacity C
m1be connected with the grid of the 3rd NMOS tube; The grid of described 3rd PMOS MP3 meets the 3rd bias voltage input VB3, and source electrode connects the drain electrode of described first PMOS MP1 and described second PMOS MP2, and drain electrode connects input power; The grid of described second NMOS tube MN2 connects the grid of described first NMOS tube MN1, and source electrode connects the output terminal of described first order error amplifier, grounded drain; The grounded drain of described first NMOS tube MN1.
Be appreciated that, the circuit structure of the first error amplifier shown in Fig. 3 is just as preferred embodiment, in fact the circuit structure of other the first error amplifier is also feasible, and the circuit structure of the embodiment of the present invention to the first concrete error amplifier is not limited.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.For system embodiment, due to itself and embodiment of the method basic simlarity, so description is fairly simple, relevant part illustrates see the part of embodiment of the method.
Above to a kind of low pressure difference linear voltage regulator provided by the present invention, be described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (2)
1. a low pressure difference linear voltage regulator, it is characterized in that, comprising: first order error amplifier, second level error amplifier, main miller-compensated electric capacity, auxiliary miller-compensated electric capacity, the 6th PMOS, zero-regulator resistor, zeroing electric capacity, the first resistance and the second resistance;
Wherein, described second level error amplifier comprises: the 4th PMOS, the 5th PMOS, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube;
The reverse input end of described first order error amplifier is connected with reference voltage end, and in-phase input end is connected with feedback voltage end;
The output terminal of first order error amplifier described in one termination of the miller-compensated electric capacity of described master, another termination voltage output end;
The grid of described 3rd NMOS tube connects the output terminal of described first order error amplifier, grounded drain; The grid of described 4th PMOS connects described zero-regulator resistor and zeroing electric capacity, and source electrode connects described zero-regulator resistor, the source electrode of described 3rd NMOS tube and the grid of described 5th PMOS; The source electrode of described 6th PMOS connects described voltage output end, and drain electrode connects input power; The drain electrode of described zeroing electric capacity and described 4th PMOS, the 5th PMOS and the 6th PMOS connects input power; The grid of described 4th NMOS tube connects the second bias voltage input, and source electrode connects the drain electrode of described 5th NMOS tube, grounded drain; The grid of described 5th NMOS tube connects the first bias voltage input, and source electrode connects the source electrode of described 5th PMOS and the drain electrode of described 6th PMOS, and drain electrode connects described auxiliary miller-compensated electric capacity;
Described auxiliary miller-compensated capacitance series is between the drain electrode and described voltage output end of described 5th PMOS;
Described first resistance and the second resistance are concatenated into resistance pressure-dividing network, a termination voltage output end of this resistance pressure-dividing network, other end ground connection, in indirect described feedback voltage end.
2. low pressure difference linear voltage regulator as claimed in claim 1, it is characterized in that, described first order error amplifier comprises: the first PMOS, the second PMOS, the 3rd PMOS, the first NMOS tube and the second NMOS tube;
Wherein, the grid of described first PMOS connects feedback voltage end, and source electrode connects the source electrode of described first NMOS tube and the grid of the second NMOS tube; The grid of described second PMOS connects feedback voltage end, and source electrode connects the output terminal of described first order error amplifier; The grid of described 3rd PMOS connects the 3rd bias voltage input, and source electrode connects the drain electrode of described first PMOS and described second PMOS, and drain electrode connects input power; The grid of described second NMOS tube connects the grid of described first NMOS tube, and source electrode connects the output terminal of described first order error amplifier, grounded drain; The grounded drain of described first NMOS tube.
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| CN105511542A (en) * | 2016-02-01 | 2016-04-20 | 东南大学 | Voltage buffer applied to SAR (Successive Approximation Register) ADC (Analog to Digital Converter) |
| CN106774590A (en) * | 2017-01-11 | 2017-05-31 | 电子科技大学 | A kind of low-dropout linear voltage-regulating circuit of high stability high-power supply noise rejection ratio |
| CN107291138A (en) * | 2017-08-13 | 2017-10-24 | 刘博文 | One kind includes frequency compensated low-dropout regulator |
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| CN107291138A (en) * | 2017-08-13 | 2017-10-24 | 刘博文 | One kind includes frequency compensated low-dropout regulator |
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