CN104750148B - A kind of low pressure difference linear voltage regulator - Google Patents
A kind of low pressure difference linear voltage regulator Download PDFInfo
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- CN104750148B CN104750148B CN201310753547.4A CN201310753547A CN104750148B CN 104750148 B CN104750148 B CN 104750148B CN 201310753547 A CN201310753547 A CN 201310753547A CN 104750148 B CN104750148 B CN 104750148B
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Abstract
The invention provides a kind of low pressure difference linear voltage regulator, including: first order error amplifier, second level error amplifier, main miller-compensated electric capacity, assist miller-compensated electric capacity, the 6th PMOS, zero-regulator resistor, zeroing electric capacity, the first resistance and the second resistance；Wherein, described second level error amplifier includes: the 4th PMOS, the 5th PMOS, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube；The reverse input end of described first order error amplifier is connected with reference voltage end, and in-phase input end is connected with feedback voltage end；The outfan of the one described first order error amplifier of termination of the miller-compensated electric capacity of described master, another terminates voltage output end；The miller-compensated capacitance series of described auxiliary is between source electrode and the described voltage output end of described 5th NMOS tube.The present invention can effectively reduce crossing of LDO and rush, and can strengthen the response speed of LDO.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of low pressure difference linear voltage regulator.
Background technology
SOC(system on a chip) (SOC, System-On-a-Chip) achieves integrates several functions on a single chip
Module, such as central processing unit, simulation and digital baseband processor, RF transmit-receive circuit etc., several functions
Module brings the demand that many grades of power supplys are powered.
Low pressure difference linear voltage regulator (LDO, Low Dropout Regulator) can be analog circuit and
The noise-sensitive such as radio circuit provide the power supply of output ripple and low, and structure is relatively easy, peripheral unit device
Part is few, thus is widely used in the SOC systems such as flash memory (FLASH).
Traditional LDO generally uses big external capacitor, and this big external capacitor can not only maintain loop steady
Fixed, and frequently can change (such as the read-write operation of FLASH) in SOC system workload state
Time play preferable transient response performance；But, this big external capacitor is unfavorable for the integrated of SOC system；
Therefore, in the case of not using big external capacitor, good transient response function is realized, in this area
Technical problem urgently to be resolved hurrily.
For solving above-mentioned technical problem, the active feedback of prior art one enhancement mode of application improves frequency
Response, shows the structural representation of a kind of low pressure difference linear voltage regulator of prior art with reference to Fig. 1, wherein,
M1, M2, Mb1, M7, M8, M5, M6, M3, M4 constitute the error amplifier of folded common source and common grid,
M9, M11, M12, M10 constitute the second gain stage, and MP0 is power tube, are mainly used in providing output
Electric current, Rf1 and Rf2 is potential-divider network, and Vout is output voltage terminal, and Mt1, Ct1 composition one is voltage-controlled
Phase-shift circuit (RC circuit, resistor capacitor circuit) network, Mk2, Ck1, Mk1, Mk2
Constituting the compensation network of the second level, Mf is feedforward level, Vb1 and Vb3 represents bias voltage input,
VD represents that input supply terminal, Vref represent reference voltage terminal.
Circuit shown in Fig. 1 can improve frequency response performance to a certain extent, but, work as load transient
During change, enough electric capacity is not had to be provided that transient current required during transient load saltus step, the most whole
The response time of voltage stabilizing feedback control loop is slow, causes the output voltage Vout can be along with the change of load current
And produce the biggest crossing and rush (overshoot), it is impossible to meet the technical grade index of high-performance regulated power supply design.
Summary of the invention
The technical problem to be solved is to provide a kind of low pressure difference linear voltage regulator, it is possible to effectively drop
Low LDO crosses punching, and can strengthen the response speed of LDO.
In order to solve the problems referred to above, the invention discloses a kind of low pressure difference linear voltage regulator, including: first
Level error amplifier, second level error amplifier, main miller-compensated electric capacity, assist miller-compensated electric capacity,
6th PMOS, zero-regulator resistor, zeroing electric capacity, the first resistance and the second resistance；
Wherein, described second level error amplifier includes: the 4th PMOS, the 5th PMOS,
3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube；
The reverse input end of described first order error amplifier is connected with reference voltage end, in-phase input end with
Feedback voltage end is connected；
The outfan of the one described first order error amplifier of termination of the miller-compensated electric capacity of described master, the other end
Connect voltage output end；
The grid of described 3rd NMOS tube connects the outfan of described first order error amplifier, and source electrode connects
Ground；The grid of described 4th PMOS connects described zero-regulator resistor and zeroing electric capacity, and drain electrode connects described zeroing
Resistance, the source electrode of described 3rd NMOS tube and the grid of described 5th PMOS；Described 6th
The drain electrode of PMOS connects described voltage output end, and source electrode connects input power；Described zeroing electric capacity and described
The source electrode of the 4th PMOS, the 5th PMOS and the 6th PMOS connects input power；Described
The grid of four NMOS tube connects the second bias voltage input, and drain electrode connects the source of described 5th NMOS tube
Pole, source ground；The grid of described 5th NMOS tube connects the first bias voltage input, and drain electrode connects
The source electrode of described 5th PMOS and the grid of described 6th PMOS, source electrode connects described auxiliary rice
Strangle and compensate electric capacity；
The miller-compensated capacitance series of described auxiliary is defeated at source electrode and the described voltage of described 5th NMOS tube
Go out between end；
Described first resistance and the second resistance are concatenated into resistance pressure-dividing network, one end of this resistance pressure-dividing network
Connect voltage output end, other end ground connection, in indirect described feedback voltage end.
Preferably, described first order error amplifier includes: the first PMOS, the second PMOS,
3rd PMOS, the first NMOS tube and the second NMOS tube；
Wherein, the grid of described first PMOS connects feedback voltage end, and drain electrode meets a described NMOS
The drain electrode of pipe and the grid of the second NMOS tube；The grid of described second PMOS connects reference voltage end,
Drain electrode connects the outfan of described first order error amplifier；It is inclined that the grid of described 3rd PMOS connects the 3rd
Putting voltage input end, drain electrode connects described first PMOS and the source electrode of described second PMOS, source
Pole connects input power；The grid of described second NMOS tube connects the grid of described first NMOS tube, leakage
Pole connects the outfan of described first order error amplifier, source ground；The source of described first NMOS tube
Pole ground connection.
Compared with prior art, the invention have the advantages that
The present invention uses the miller-compensated electric capacity of auxiliary and the 5th NMOS tube to constitute current buffering in LDO
Feedback, and, introduced by zero-regulator resistor Rz, zeroing electric capacity Cz and the 4th PMOS MP4
One active zero point；
On the one hand, when the voltage of voltage output end out reduces because of load transient change when, the
The source electrode of five NMOS tube can reduce suddenly, and this makes the electric current flowing through the 5th NMOS tube increase suddenly,
The grid voltage of the 6th PMOS is dragged down and needs not move through amplifier stage such that it is able to output auxiliary Miller
Compensate electric capacity, the fast path of the 5th NMOS tube to the 6th PMOS；And this quickly responds path
The transient state loop bandwidth of LDO can be increased, strengthen the output transient response of LDO, therefore, it is possible to reduce
The size of output spike voltage, namely can effectively reduce the punching excessively of LDO；
On the other hand, the absolute value of this active zero point by controlling Rz and Cz, can be made less than LDO
In the absolute value of the second limit, to realize offsetting this second limit by this active zero point；Furthermore it is possible to it is logical
Cross control and assist miller-compensated electric capacity and the mutual conductance of the 5th NMOS tube, to realize with above-mentioned auxiliary Miller
Compensate electric capacity Cm2The zero point introduced with the 5th NMOS tube MN5 offsets the higher order pole in LDO；
And after stating two counteractings in realization, second limit of LDO and higher order pole are cancelled, and can regard as
LDO only one of which the first limit, owing to the bandwidth of first order pole is certain to the bandwidth more than many limits, therefore
The loop bandwidth of LDO can be increased, the response speed of reinforcing feedback；
To sum up, the present invention can not increase power consumption and without big external capacitor in the case of, be greatly improved
The response speed of LDO.After tested, the LDO of the present embodiment maximum load electric capacity when stable is
200pF, therefore, is especially suitable for SOC systematic difference.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of a kind of LDO of prior art；
Fig. 2 is the structure chart of the present invention a kind of low pressure difference linear voltage regulator embodiment 1；
Fig. 3 is the structure chart of the present invention a kind of low pressure difference linear voltage regulator embodiment 2.
Detailed description of the invention
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The present invention is further detailed explanation with detailed description of the invention.
With reference to Fig. 2, it is shown that the structure chart of the present invention a kind of low pressure difference linear voltage regulator embodiment 1, tool
Body may include that first order error amplifier U1, second level error amplifier, main miller-compensated electric capacity
Cm1, assist miller-compensated electric capacity Cm2, the 6th PMOS MP6, zero-regulator resistor Rz, zeroing electric capacity
Cz, the first resistance R1 and the second resistance R2；
Wherein, described second level error amplifier specifically may include that the 4th PMOS MP4,
Five PMOS MP5, the 3rd NMOS tube MN3, the 4th NMOS tube MN4 and the 5th NMOS
Pipe MN5；
The reverse input end of described first order error amplifier U1 is connected with reference voltage end Vref, homophase
Input is connected with feedback voltage end V120；
Described master miller-compensated electric capacity Cm1One termination described first order error amplifier U1 outfan,
Another terminates voltage output end out；
The grid of described 3rd NMOS tube MN3 connects the outfan of described first order error amplifier U1,
Source ground；The grid of described 4th PMOS MP4 connects described zero-regulator resistor Rz and zeroing electric capacity
Cz, drain electrode connects described zero-regulator resistor Rz, the drain electrode and the described 5th of described 3rd NMOS tube MN3
The grid of PMOS MP5；The drain electrode of described 6th PMOS MP6 connects described voltage output end
Out, source electrode connects input power；Described zeroing electric capacity Cz and described 4th PMOS MP4, the 5th
The source electrode of PMOS MP5 and the 6th PMOS MP6 connects input power；Described 4th NMOS
The grid of pipe MN4 meets the second bias voltage input VB2, and drain electrode connects described 5th NMOS tube MN5
Source electrode, source ground；The grid of described 5th NMOS tube MN5 connects the first bias voltage input
VB1, drain electrode connects drain electrode and the grid of described 6th PMOS MP6 of described 5th PMOS MP5
Pole, source electrode meets described auxiliary miller-compensated electric capacity Cm2；
Described auxiliary miller-compensated electric capacity Cm2It is serially connected in source electrode and the institute of described 5th NMOS tube MP5
State between voltage output end out；
Described first resistance R1 and the second resistance R2 is concatenated into resistance pressure-dividing network, this electric resistance partial pressure net
Network one termination voltage output end out, other end ground connection, in indirect described feedback voltage end V120.
The low pressure difference linear voltage regulator of the embodiment of the present invention can apply to flash memory (flash memory) etc.
In SOC system, to play that its volume is little, outward element is little, low-power consumption, interference is little, output noise is low,
Easy to use, cheap advantage.
The present embodiment mainly can include that three grades of structure for amplifying, described three grades of structure for amplifying specifically can wrap
Include: corresponding for first order error amplifier U1 the first amplifier stage, second level error amplifier corresponding
Two amplifier stages and the 6th PMOS MP6, the first resistance R1 and the second resistance R2 constitute the 3rd
Amplifier stage.
In the present embodiment, assist miller-compensated electric capacity Cm2Constitute electric current with the 5th NMOS tube MN5 to delay
Punching feedback (current buffer feedback), when the voltage of voltage output end out is because load transient becomes
Changing and when reduce, the source electrode of the 5th NMOS tube MN5 also can reduce suddenly, this can make to flow through the
The electric current of five NMOS tube MN5 increases suddenly, and the grid voltage of the 6th PMOS MP6 is dragged down
And needing not move through amplifier stage such that it is able to output assists miller-compensated electric capacity Cm2, the 5th NMOS tube
The fast path of MN5 to the 6th PMOS MP6；And this quickly responds path and can increase LDO
Transient state loop bandwidth, strengthen LDO output transient response, therefore, it is possible to reduce output spike voltage
Size, namely can effectively reduce LDO cross punching.
It addition, in actual applications, owing to the size of usual 6th PMOS MP6 is very big, therefore
6th PMOS MP6 grid correspondence limit, very close to initial point, is easily caused LDO unstable, this
Time can only by increase power consumption the 6th PMOS MP6 grid correspondence limit shifted onto beyond bandwidth with
Stabilizing circuit, this power consumption resulting in circuit is the biggest.
For the problems referred to above, the present embodiment creatively introduces an active zero point to eliminate the 6th PMOS
The limit that pipe MP6 grid is corresponding, this active zero point specifically can include zero-regulator resistor Rz, zeroing electric capacity
Cz and the 4th PMOS MP4.
At this according to performances such as the response characteristic of zero-pole analysis LDO system of LDO, stability.
The limit of the present embodiment specifically may include that the first limit, the second limit and higher order pole；Wherein,
First limit is main miller-compensated electric capacity Cm1The Miller effect introduce, its value is the least, the most close
Initial point, it is assumed that use C∑Represent the second amplifier stage and the gain of the 3rd amplifier stage and Cm1Product, then
First limit is exactly C∑Inverse with the product of the first amplifier stage output resistance；Second limit is above-mentioned
Six PMOS MP6 grid correspondence limits, its numerical value can be approximated to be (Cm2/C2)*(gm3/CL), wherein,
gm3It is the mutual conductance of the 3rd amplifier stage, C2It is the output parasitic capacitance of the second error amplifier, CLRepresent total
Load output capacitance.
The zero point of the present embodiment specifically may include that above-mentioned active zero point and assists miller-compensated electric capacity
Cm2The zero point introduced with the 5th NMOS tube MN5；Wherein, the numerical value of above-mentioned active zero point equal to Rz,
The inverse of Cz product, assists miller-compensated electric capacity Cm2The zero point introduced with the 5th NMOS tube MN5
Numerical value is equal to gm5/Cm2, wherein, gm5It it is the mutual conductance of the 5th NMOS tube MN5.
In implementing, those skilled in the art can control Rz and Cz according to practical situation, make
The absolute value of above-mentioned active zero point is less than the absolute value of above-mentioned second limit, to realize supporting by this active zero point
Disappear this second limit；For example, it is possible to Rz is obtained the biggest.
It addition, those skilled in the art can also control g according to practical situationm5And Cm2, to realize
With above-mentioned auxiliary miller-compensated electric capacity Cm2The zero point introduced with the 5th NMOS tube MN5 offsets above-mentioned height
Rank limit.
After stating two counteractings in realization, second limit of the present embodiment and higher order pole are cancelled, permissible
Regard LDO only one of which the first limit as, owing to the bandwidth of first order pole is certain to the bandwidth more than many limits,
Therefore the loop bandwidth of LDO can be increased, the response speed of reinforcing feedback.
To sum up, the present embodiment can not increase power consumption and without big external capacitor in the case of, significantly carry
The response speed of high LDO.After tested, the LDO of the present embodiment maximum load electric capacity when stable is
200pF, therefore, is especially suitable for SOC systematic difference.
With reference to Fig. 3, it is shown that the optional structure chart of the present invention a kind of low pressure difference linear voltage regulator embodiment 2.
The low pressure difference linear voltage regulator of the present embodiment, on the basis of above-mentioned embodiment illustrated in fig. 2, the most also may be used
To include following optional technical scheme.
As it is shown on figure 3, first error amplifier of the present embodiment specifically may include that a PMOS
Pipe MP1, the second PMOS MP2, the 3rd PMOS MP3, the first NMOS tube MN1 and
Second NMOS tube MN2；
Wherein, the grid of described first PMOS MP1 meets feedback voltage end V120, and drain electrode connects described
The drain electrode of the first NMOS tube MN1 and the grid of the second NMOS tube MN2；Described 2nd PMOS
The grid of pipe MP2 connects reference voltage end Vref, and drain electrode connects the outfan of described first order error amplifier,
This outfan and main miller-compensated electric capacity Cm1It is connected with the grid of the 3rd NMOS tube；Described 3rd
The grid of PMOS MP3 meets the 3rd bias voltage input VB3, and drain electrode meets a described PMOS
Pipe MP1 and the source electrode of described second PMOS MP2, source electrode connects input power；Described 2nd NMOS
The grid of pipe MN2 connects the grid of described first NMOS tube MN1, and drain electrode connects described first order error
The outfan of amplifier, source ground；The source ground of described first NMOS tube MN1.
It is appreciated that shown in Fig. 3, the circuit structure of the first error amplifier is intended only as preferred embodiment,
The actually circuit structure of other the first error amplifier is also feasible, and the embodiment of the present invention is to concrete
The circuit structure of the first error amplifier is not any limitation as.
Each embodiment in this specification all uses the mode gone forward one by one to describe, and each embodiment stresses
Be all the difference with other embodiments, between each embodiment, identical similar part sees mutually
?.For system embodiment, due to itself and embodiment of the method basic simlarity, so the ratio described
Relatively simple, relevant part sees the part of embodiment of the method and illustrates.
Above to a kind of low pressure difference linear voltage regulator provided by the present invention, it is described in detail, herein
In apply specific case principle and the embodiment of the present invention be set forth, saying of above example
Bright method and the core concept thereof being only intended to help to understand the present invention；General simultaneously for this area
Technical staff, according to the thought of the present invention, the most all can change it
Place, in sum, this specification content should not be construed as limitation of the present invention.
Claims (2)
1. a low pressure difference linear voltage regulator, it is characterised in that including: first order error amplifier,
Second level error amplifier, main miller-compensated electric capacity, assist miller-compensated electric capacity, the 6th PMOS,
Zero-regulator resistor, zeroing electric capacity, the first resistance and the second resistance；
Wherein, described second level error amplifier includes: the 4th PMOS, the 5th PMOS,
3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube；
The reverse input end of described first order error amplifier is connected with reference voltage end, in-phase input end with
Feedback voltage end is connected；
The outfan of the one described first order error amplifier of termination of the miller-compensated electric capacity of described master, the other end
Connect voltage output end；
The grid of described 3rd NMOS tube connects the outfan of described first order error amplifier, and source electrode connects
Ground；The grid of described 4th PMOS connects described zero-regulator resistor and zeroing electric capacity, and drain electrode connects described zeroing
Resistance, the drain electrode of described 3rd NMOS tube and the grid of described 5th PMOS；Described 6th
The drain electrode of PMOS connects described voltage output end, and source electrode connects input power；Described zeroing electric capacity and described
The source electrode of the 4th PMOS, the 5th PMOS and the 6th PMOS connects input power；Described
The grid of four NMOS tube connects the second bias voltage input, and drain electrode connects the source of described 5th NMOS tube
Pole, source ground；The grid of described 5th NMOS tube connects the first bias voltage input, and drain electrode connects
The source electrode of described 5th PMOS and the grid of described 6th PMOS, source electrode connects described auxiliary rice
Strangle and compensate electric capacity；
The miller-compensated capacitance series of described auxiliary is defeated at source electrode and the described voltage of described 5th NMOS tube
Go out between end；
Described first resistance and the second resistance are concatenated into resistance pressure-dividing network, one end of this resistance pressure-dividing network
Connect voltage output end, other end ground connection, in indirect described feedback voltage end.
2. low pressure difference linear voltage regulator as claimed in claim 1, it is characterised in that the described first order
Error amplifier includes: the first PMOS, the second PMOS, the 3rd PMOS, a NMOS
Pipe and the second NMOS tube；
Wherein, the grid of described first PMOS connects feedback voltage end, and drain electrode meets a described NMOS
The drain electrode of pipe and the grid of the second NMOS tube；The grid of described second PMOS connects reference voltage end,
Drain electrode connects the outfan of described first order error amplifier；It is inclined that the grid of described 3rd PMOS connects the 3rd
Putting voltage input end, drain electrode connects described first PMOS and the source electrode of described second PMOS, source
Pole connects input power；The grid of described second NMOS tube connects the grid of described first NMOS tube, leakage
Pole connects the outfan of described first order error amplifier, source ground；The source of described first NMOS tube
Pole ground connection.
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| CN105159383A (en) * | 2015-08-24 | 2015-12-16 | 电子科技大学 | Low dropout regulator with high power supply rejection ratio |
| CN105511542B (en) * | 2016-02-01 | 2017-01-25 | 东南大学 | A Voltage Buffer Applied to SAR ADC |
| US9791874B1 (en) * | 2016-11-04 | 2017-10-17 | Nxp B.V. | NMOS-based voltage regulator |
| CN106774590A (en) * | 2017-01-11 | 2017-05-31 | 电子科技大学 | A kind of low-dropout linear voltage-regulating circuit of high stability high-power supply noise rejection ratio |
| CN109445503A (en) * | 2017-08-11 | 2019-03-08 | 李启同 | A kind of LDO circuit applied to integrated chip |
| CN107291138A (en) * | 2017-08-13 | 2017-10-24 | 刘博文 | One kind includes frequency compensated low-dropout regulator |
| CN109683648B (en) * | 2017-10-19 | 2023-08-01 | 辉芒微电子(深圳)股份有限公司 | LDO circuit |
| CN110174918B (en) * | 2019-05-10 | 2024-06-11 | 深圳市汇春科技股份有限公司 | Overshoot elimination circuit, undershoot elimination circuit and chip of low dropout linear voltage regulator |
| CN111273724B (en) * | 2020-02-04 | 2021-03-30 | 同济大学 | Stability-compensated linear voltage regulator and design method thereof |
| CN111338413B (en) * | 2020-03-02 | 2021-05-14 | 电子科技大学 | A Low Dropout Linear Regulator with High Power Supply Rejection Ratio |
| CN113238603B (en) * | 2021-05-28 | 2022-08-26 | 成都海光微电子技术有限公司 | Linear voltage stabilizer, SOC chip and electronic equipment |
| CN113672027B (en) * | 2021-08-20 | 2022-04-01 | 苏州云途半导体有限公司 | Push-pull quick response LDO (low dropout regulator) capable of receiving any capacitive load |
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