CN114172517B - Infrared reading circuit and analog-to-digital converter - Google Patents
Infrared reading circuit and analog-to-digital converter Download PDFInfo
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The invention provides an infrared reading circuit and an analog-to-digital converter, and relates to the technical field of infrared focal plane arrays. The circuit comprises: the device comprises a conversion unit, an integration unit, a comparator and a control logic unit; the conversion unit converts the voltage difference between the voltage of the diode detector and the voltage of the blind end detector into corresponding current and transmits the corresponding current to the integration unit; the control logic unit receives the overturning signal sent by the comparator and sends a control signal to the integration unit; the integrating unit includes: and the two integrating capacitors are controlled by the control signal, the current is alternately folded and integrated, and when any one integrating capacitor is folded and integrated, the upper polar plate voltage of the other integrating capacitor is reset. The invention avoids delay of the comparator and phase change, eliminates charge and discharge time of integral capacitor reset, greatly reduces nonlinearity, thereby improving accuracy and dynamic range of ADC, improving linearity without increasing power consumption, and having higher practical value.
Description
Technical Field
The invention relates to the technical field of infrared focal plane arrays, in particular to an infrared reading circuit and an analog-to-digital converter.
Background
Infrared imaging is a detector technology that obtains infrared imaging by detecting thermal radiation of a target object. The uncooled infrared focal plane array detector has obvious advantages in the aspects of cost, portability, power consumption and the like, so that the uncooled infrared focal plane array detector is widely applied to military and civil fields such as night vision, monitoring, thermal image temperature measurement and the like. The design of the reading circuit always has research difficulty and hot spot of the uncooled infrared focal plane array, and can be divided into analog reading and digital reading according to a reading mode, wherein the digital reading finishes analog-to-digital conversion through an on-chip integrated ADC, and the transmission path of an analog signal is shorter and has less loss, so that the reading circuit has higher performance compared with the analog reading. The sensitivity of the infrared focal plane detector to the substrate temperature and the portability of the application scene all put quite strict limits on the power consumption of the readout circuit, especially the power consumption of the ADC.
The folding integrating ADC is a common infrared reading circuit ADC scheme, and has the advantages of simple circuit structure, lower power consumption, larger charge processing capacity and the like by folding and integrating signals on an integrating capacitor.
However, in such an infrared readout circuit, the delay of the comparator and the charge-discharge time of the reset of the integrating capacitor may cause nonlinearity, and the nonlinearity may increase with the increase of the signal, thereby limiting the accuracy and dynamic range of the ADC. If the power consumption of the comparator is directly increased, although delay can be reduced and linearity can be improved, the power consumption budget of the uncooled infrared reading circuit is limited, and excessive power consumption can cause excessive substrate temperature to directly influence the performance of the thermosensitive detector. Therefore, how to improve linearity without increasing power consumption is a need for solving the problem.
Disclosure of Invention
The invention provides an infrared reading circuit and an analog-to-digital converter, which are capable of improving linearity without increasing power consumption.
A first aspect of an embodiment of the present invention provides an infrared readout circuit, the circuit including: the device comprises a conversion unit, an integration unit, a comparator and a control logic unit;
the conversion unit receives the voltage of the diode detector and the voltage of the blind end detector in the infrared focal plane array, converts the voltage difference between the voltage of the diode detector and the voltage of the blind end detector into corresponding current, and transmits the corresponding current to the integration unit;
The integrating unit is controlled by the control logic unit and performs folding integration on the current;
The control logic unit receives the overturning signal sent by the comparator and sends a control signal to the integration unit;
wherein the integrating unit includes: two integrating capacitances;
the two integrating capacitors are controlled by the control signal, the current is alternately folded and integrated, and when any one integrating capacitor is folded and integrated, the upper polar plate voltage of the other integrating capacitor is reset;
each column in the infrared focal plane array shares one of the infrared readout circuits.
Optionally, the integrating unit further includes: four control switches;
the four control switches and the two integrating capacitors form a ping-pong reset structure;
The four control switches receive control signals, control the two integrating capacitors to alternately perform folding integration on the current based on the ping-pong reset structure, and when any one integrating capacitor performs folding integration, the upper pole plate voltage of the other integrating capacitor is reset.
Optionally, the circuit further comprises: a reset switch; the conversion unit includes: a transconductance amplifier; the integrating unit further includes: an integrating transistor;
the four control switches are respectively: the first control switch, the second control switch, the third control switch and the fourth control switch; the two integrating capacitors are respectively: the first integrating capacitor and the second integrating capacitor;
the non-inverting terminal of the transconductance amplifier receives the diode detector voltage;
The inverting terminal of the transconductance amplifier receives the blind terminal detector voltage;
The output end of the transconductance amplifier is connected with the source electrode of the integrating transistor;
A gate of the integrating transistor receives an integrated signal;
The drain electrode of the integrating transistor is respectively connected with the first end of the first control switch, the first end of the fourth control switch, the second end of the reset switch and the in-phase end of the comparator;
The second end of the first control switch is respectively connected with the upper polar plate of the first integrating capacitor and the first end of the second control switch;
the second end of the second control switch is respectively connected with the lower polar plate of the first integrating capacitor and the first end of the third control switch, and the lower polar plate of the first integrating capacitor receives reset voltage;
The second end of the third control switch is respectively connected with the upper polar plate of the second integrating capacitor and the second end of the fourth control switch;
The lower polar plate of the second integrating capacitor receives the reset voltage;
A first end of the reset switch receives the reset voltage;
the inverting terminal of the comparator receives a reference voltage.
Optionally, an output end of the comparator is connected with the control logic unit;
The control logic unit generates the control signal according to the overturning signal, and the control signal is used for controlling the opening or closing of the four control switches.
Optionally, the control signal includes: a first control signal and a second control signal;
the first control switch and the third control switch are controlled by the first control signal;
the second control switch and the fourth control switch are controlled by the second control signal;
the first control switch and the third control switch are simultaneously opened or simultaneously closed;
the second control switch and the fourth control switch are simultaneously opened or simultaneously closed;
when the first control switch and the third control switch are opened, the second control switch and the fourth control switch are closed, and when the first control switch and the third control switch are closed, the second control switch and the fourth control switch are opened.
Optionally, the control logic unit alternately generates the first control signal and the second control signal according to the flipping signal, when one of the flipping signals is received last time, generates the first control signal, and when one of the flipping signals is received next time, generates the second control signal.
Optionally, when the first control switch and the third control switch are controlled by the first control signal to be closed, the second control switch and the fourth control switch are controlled to be opened, the first integrating capacitor performs folding integration on the current, and meanwhile, the upper polar plate voltage of the second integrating capacitor is reset to the reset voltage;
And when the second control switch and the fourth control switch are controlled by the second control signal to be closed, the first control switch and the third control switch are opened, the second integrating capacitor performs folding integration on the current, and meanwhile, the upper polar plate voltage of the first integrating capacitor is reset to the reset voltage.
Optionally, when the first integrating capacitor performs folding integration on the current, the voltage of an upper polar plate of the first integrating capacitor gradually rises from the reset voltage until rising to the reference voltage, and the comparator turns over and sends the turning signal to the control logic unit;
When the second integrating capacitor performs folding integration on the current, the voltage of the upper polar plate of the second integrating capacitor gradually rises from the reset voltage until the voltage rises to the reference voltage, and the comparator turns over and sends the turning signal to the control logic unit.
Optionally, the circuit further comprises: and the counter is connected with the output end of the comparator and is used for recording the turnover times of the comparator during the period that the first integration capacitor and the second integration capacitor alternately perform folding integration on the current.
A second aspect of an embodiment of the present invention provides an analog-to-digital converter, including: a circuit as claimed in any one of the first aspects.
The infrared reading circuit provided by the invention has the advantages that the conversion unit converts the voltage difference between the voltage of the diode detector and the voltage of the blind end detector into corresponding current, and the corresponding current is transmitted to the integration unit; the integrating unit includes: the two integrating capacitors are controlled by the control signals of the control logic unit and are used for alternately folding and integrating the current. That is, when any one of the integration capacitors performs folding integration, the upper plate voltage of the other integration capacitor is reset.
Compared with the traditional folding integrating ADC, the two integrating capacitors alternately perform folding integration and alternate reset. For example, when one capacitor is integrated, the capacitor is not directly reset, but the other capacitor which is reset in advance is switched to replace the capacitor for integration, so that delay of a comparator and charging and discharging time of phase change which eliminates the reset of the integrating capacitor are avoided, nonlinearity is greatly reduced, the precision and dynamic range of the ADC are improved, linearity is improved on the premise that power consumption is not increased, and the method has high practical value.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an infrared readout circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a preferred infrared readout circuit in accordance with an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating operation of the infrared sensing circuit in accordance with an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The inventor finds that, in the current traditional folding integral ADC, N times of folding are performed in one integral quantization process, and the charge Q int on the integral capacitor can be written as:
Qint＝IsigTint＝Qeff+Qrst+Qε
＝N×CVREF+N×Isigtrst+CVε#(1)
In the above formula, I sig represents the current converted by the conversion unit, T rst represents the total delay time (including delay of the comparator, charge-discharge time of the integration capacitor reset and time from the voltage of the same phase end of the comparator exceeding the reference voltage to the voltage of the same phase end of the comparator being recovered to the reference voltage), T int represents the total integration time, Q eff represents the effective charge actually processed by the circuit, Q rst represents the charge lost due to failure of the circuit due to delay, Q ε represents the residual charge on the integration capacitor after the completion of folding integration, N is the folding times, and V ε is the residual voltage.
Ideally, the total delay time t rst and the margin V ε are zero, the charge packet size for each fold reset is CV REF, and the number of folds is N ideal＝IsigTint/CVREF. However, since the actual delay is not zero, the non-linearity ΔN can be calculated as follows:
In the above formula, the approximation process is performed in the formula (2), because in practical application, the margin V ε can be processed by further refinement. As can be seen from equation (3), the non-linearity Δn increases as the current I sig and the total delay time t rst increase, thereby limiting the accuracy and dynamic range of the ADC.
Through a great deal of researches and actual measurement, the inventor creatively provides the infrared reading circuit and the analog-to-digital converter, which do not increase the power consumption, but also can improve the linearity. The infrared readout circuit and the analog-to-digital converter according to the embodiment of the present invention are explained and described in detail below.
Referring to FIG. 1, a modular schematic diagram of an infrared readout circuit is shown in accordance with an embodiment of the present invention. The infrared readout circuit includes: the device comprises a conversion unit, an integration unit, a comparator and a control logic unit.
The conversion unit receives the voltage of the diode detector and the voltage of the blind end detector in the infrared focal plane array, converts the voltage difference between the voltage of the diode detector and the voltage of the blind end detector into corresponding current, and transmits the corresponding current to the integration unit. Typically, the converted current is drawn from the integrating capacitor to the conversion unit, so that the voltage at the upper plate of the integrating capacitor drops during the folding integration process.
The control logic unit receives the overturning signal sent by the comparator and sends a control signal to the integration unit; and the integrating unit is controlled by the control logic unit and performs folding integration on the current. Specifically, the integrating unit includes: two integrating capacitances; the two integrating capacitors are controlled by control signals to alternately perform folding integration on the current, namely, when any one integrating capacitor performs folding integration, the upper polar plate voltage of the other integrating capacitor is reset, so that when the other integrating capacitor is switched to be ready for starting the folding integration, the folding integration can be directly performed, the resetting is not needed, and then the folding integration is started. Each column in the entire infrared focal plane array may share an infrared readout circuit of an embodiment of the present invention.
In the embodiment of the present invention, in order to implement the above functions, a preferred manner is to design the integration unit as a ping-pong reset structure. The integrating unit further includes: four control switches; the four control switches and the two integrating capacitors form a ping-pong reset structure; the four control switches receive control signals, control the two integrating capacitors to alternately perform folding integration on the current based on the ping-pong reset structure, and when any one integrating capacitor performs folding integration, the upper pole plate voltage of the other integrating capacitor is reset. Of course, the embodiments of the present invention are not limited in particular, and any circuit or component that can achieve the above functions may be used.
Referring to fig. 2, a schematic diagram of a preferred infrared readout circuit in an embodiment of the present invention is shown, where fig. 2 includes: the transconductance amplifier GM, the integrating transistor MP, the first integrating capacitor C 1, the second integrating capacitor C 2, the reset switch S R, the first control switch S 1, the second control switch S 2, the third control switch S 3, the fourth control switch S 4, the comparator CMP, the control logic unit ControlLogic (hereafter abbreviated CL is used instead for brevity) and the Counter.
In fig. 2, the conversion unit is represented by a transconductance amplifier GM, the non-inverting terminal of which receives the diode detector voltage (V in in fig. 2), and the inverting terminal of which receives the blind terminal detector voltage (V blind in fig. 2); the output terminal of the transconductance amplifier GM is connected to the source of the integrating transistor MP. Of course, other components or circuits that can implement the GM function of the transconductance amplifier may be used as the conversion unit.
The gate of the integrating transistor MP receives the integrating signal INT; the drain of the integrating transistor MP is connected to the first terminal of the first control switch S 1, the first terminal of the fourth control switch S 4, the second terminal of the reset switch S R, and the non-inverting terminal of the comparator CMP (the non-inverting terminal receives the integrating voltage V INT), respectively. During the period that the integration signal INT is low level, the integration transistor MP is conducted, and the infrared reading circuit is in a folding integration stage to generate a current I SIG; during the high period of the integration signal INT, the integration transistor MP is turned off, and the infrared readout circuit is not operated.
The second end of the first control switch S 1 is respectively connected with the upper polar plate of the first integrating capacitor C 1 and the first end of the second control switch S 2; the second end of the second control switch S 2 is connected to the lower plate of the first integrating capacitor C 1 and the first end of the third control switch S 3, respectively, and the lower plate of the first integrating capacitor C 1 receives the reset voltage V SS.
The second end of the third control switch S 3 is respectively connected with the upper polar plate of the second integrating capacitor C 2 and the second end of the fourth control switch S 4; the lower polar plate of the second integrating capacitor C 2 receives the reset voltage V SS; a first end of the reset switch S R receives the reset voltage V SS, and the reset switch S R is controlled by the reset signal Φ RST; the inverting terminal of the comparator CMP receives the reference voltage V REF.
In the embodiment of the invention, the output end of the comparator CMP is connected with the control logic unit CL; the control logic CL generates a control signal for controlling the opening or closing of the four control switches according to the flipping signal (CMP OUT in fig. 2).
Specifically, the control signal includes: a first control Signal (Signal 1 in fig. 2) and a second control Signal (Signal 2 in fig. 2); the first control switch S 1 and the third control switch S 3 are controlled by a first control signal; the second control switch S 2 and the fourth control switch S 4 are controlled by a second control signal; the first control switch S 2 and the third control switch S 3 are simultaneously opened or simultaneously closed; the second control switch S 2 and the fourth control switch S 4 are simultaneously opened or simultaneously closed. When the first control switch S 1 and the third control switch S 3 are opened, the second control switch S 2 and the fourth control switch S 4 are closed, and when the first control switch S 1 and the third control switch S 3 are closed, the second control switch S 2 and the fourth control switch S 4 are opened.
In the embodiment of the present invention, the control logic unit CL may alternately generate the first control signal and the second control signal according to the inversion signal sent by the comparator CMP. In general, when the first integrating capacitor C 1 performs folding integration on the current, the upper plate voltage of the first integrating capacitor C 1 gradually rises from the reset voltage V SS until rising to the reference voltage V REF, at this time, the comparator CMP turns over and sends a turning signal to the control logic unit CL; when the second integrating capacitor C 2 performs folding integration on the current, the upper plate voltage of the second integrating capacitor C 2 gradually rises from the reset voltage V SS until rising to the reference voltage V REF, and the comparator CMP turns over and sends a turning signal to the control logic unit CL.
If the control logic unit CL receives a flipping signal the previous time it generates a first control signal, then the next time the control logic unit CL receives a flipping signal it generates a second control signal, the third time the control logic unit CL receives a flipping signal it generates a first control signal again, and so on until the whole folding integration process is over.
When the first control switch S 1 and the third control switch S 3 are controlled to be closed by a first control signal, the second control switch S 2 and the fourth control switch S 4 are opened, at this time, the first integrating capacitor C 1 performs folding integration on the current, and meanwhile, the upper plate voltage of the second integrating capacitor C 2 is reset to the reset voltage V SS; when the second control switch S 2 and the fourth control switch S 4 are controlled to be closed by the second control signal S 2, the first control switch S 1 and the third control switch S 3 are opened, and at this time, the second integrating capacitor C 2 performs folding integration on the current, and at the same time, the upper plate voltage of the first integrating capacitor C 1 is reset to the reset voltage V SS.
For the Counter, the Counter is connected to an output end of the comparator CMP, and is used for recording the turnover number of the comparator CMP during the period that the first integrating capacitor C 1 and the second integrating capacitor C 2 alternately fold and integrate the current, where the turnover number is the n-bit quantization result b n...b1 of the ADC.
In summary, with reference to the operation timing diagrams of the infrared readout circuit shown in fig. 2 and 3, the operation principle of the infrared readout circuit according to the embodiment of the present invention is as follows:
When the analog-to-digital converter starts to work, if INT is high level, the integrating transistor MP is turned off, the infrared reading circuit does not perform folding integration, only INT is low level, the integrating transistor MP is turned on, the infrared reading circuit starts to perform folding integration, first, the reset signal Φ RET is high level, the reset switch S R is turned on, the whole infrared reading circuit is reset, then the reset signal Φ RET becomes low level, the two integrating capacitors start to perform folding integration, and in the whole folding integration process, the reset signal Φ RET is kept low level.
When folding integration starts, if the first control Signal1 is a high level Signal and the second control Signal2 is a low level Signal, the first control switch S 1 and the third control switch S 3 are closed, the second control switch S 2 and the fourth control switch S 4 are opened, the first integrating capacitor C 1 starts folding integration, the second integrating capacitor C 2 cannot perform folding integration naturally because of the open loop, and the upper plate voltage of the second integrating capacitor C 2 is the reset voltage V SS.
Since the transconductance amplifier GM is always converting the voltage difference of the two detectors into a current and integrating the current on the integrating capacitor, the upper plate voltage V INT of the first integrating capacitor C 1 starts rising from the reset voltage V SS, and when the upper plate voltage V INT rises to the reference voltage V REF, the comparator CMP outputs the flip signal CMP OUT (the flip signal is a pulse signal).
The comparator CMP outputs the flip Signal CMP OUT to the control logic unit CL, and the control logic unit CL generates the high-level second control Signal2 after receiving the flip Signal CMP OUT, and the first control Signal1 is at the low level. Therefore, the second control switch S 2 and the fourth control switch S 4 are closed, the first control switch S 1 and the third control switch S 3 are opened, and then the second integrating capacitor C 2 starts to perform folding integration, at the same time, the first integrating capacitor C 1 cannot perform folding integration naturally because the loop is opened, and the upper plate voltage of the first integrating capacitor C 1 is reset and becomes the reset voltage V SS.
The same process as the folding integration of the first integrating capacitor C, the upper plate voltage V INT of the second integrating capacitor C 2 starts rising from the reset voltage V SS, and when the upper plate voltage V INT rises to the reference voltage V REF, the comparator CMP outputs the flip signal CMP OUT to the control logic unit CL again.
After receiving the Signal, the control logic unit CL generates the first control Signal1 with a high level, and at this time, the second control Signal1 changes to a low level again. Therefore, the first control switch S 1 and the third control switch S 3 are closed, the second control switch S 2 and the fourth control switch S 4 are opened, and then the first integrating capacitor C 1 starts folding integration again, at the same time, the second integrating capacitor C 2 cannot perform folding integration again because of the loop opening, and the upper plate voltage of the second integrating capacitor C 2 is reset again and becomes the reset voltage V SS. The above process is repeated until the whole folding integration is finished, i.e., INT becomes high level, and the integrating transistor MP is turned off.
In the whole folding integration process, the Counter continuously records the turnover number of the comparator CMP, namely the n-bit quantization result b n...b1 of the ADC, during the period that the first integration capacitor C 1 and the second integration capacitor C 2 alternately perform folding integration on the current.
Compared with the infrared reading circuit with the traditional structure, the infrared reading circuit of the embodiment of the invention has shorter total delay time because: the total delay time trst of the infrared readout circuit of the conventional structure comprises: the delay time t d2 of the comparator CMP, the charge-discharge time t ch of the integrating capacitor reset, and the time t d1 of the comparator from the same-phase terminal voltage exceeding the reference voltage to the recovery to the reference voltage. In the readout circuit of the embodiment of the invention, a ping-pong reset structure is used, two integrating capacitors C 1 and C 2 are used for resetting alternately, and in the process of folding and integrating by one integrating capacitor, the other integrating capacitor finishes resetting, and the other integrating capacitor can directly start folding and integrating, so that the delay time t d2 of the comparator CMP and the charging and discharging time t ch of the resetting of the integrating capacitor are not existed, only the voltage of the same phase end of the comparator exceeds the reference voltage, and the time t d1 for recovering to the reference voltage exists, as the existence of t d1 is exemplarily shown in fig. 3, the total delay time of the infrared readout circuit of the embodiment of the invention is shorter than the total delay time of the infrared readout circuit of the traditional structure at present.
Based on the above-mentioned infrared readout circuit, the embodiment of the present invention further provides an analog-to-digital converter, where the analog-to-digital converter includes: an infrared readout circuit as claimed in any one of the above.
In summary, in the infrared readout circuit according to the embodiment of the present invention, the conversion unit converts the voltage difference between the diode detector voltage and the blind end detector voltage into the corresponding current, and transmits the corresponding current to the integration unit; when any one integrating capacitor performs folding integration, the integrating unit resets the upper polar plate voltage of the other integrating capacitor.
Compared with the traditional folding integrating ADC, the two integrating capacitors alternately perform folding integration and alternate reset. For example, when one capacitor is integrated, the capacitor is not directly reset, but the other capacitor which is reset in advance is switched to replace the capacitor for integration, so that delay of a comparator and charging and discharging time of phase change which eliminates the reset of the integrating capacitor are avoided, nonlinearity is greatly reduced, the precision and dynamic range of the ADC are improved, linearity is improved on the premise that power consumption is not increased, and the method has high practical value.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (7)
1. An infrared readout circuit, said circuit comprising: the device comprises a conversion unit, an integration unit, a comparator and a control logic unit;
the conversion unit receives the voltage of the diode detector and the voltage of the blind end detector in the infrared focal plane array, converts the voltage difference between the voltage of the diode detector and the voltage of the blind end detector into corresponding current, and transmits the corresponding current to the integration unit;
the integrating unit is controlled by the control logic unit and performs folding integration on the current; the control logic unit receives the overturning signal sent by the comparator and sends a control signal to the integration unit;
Wherein the integrating unit includes: the first integrating capacitor, the second integrating capacitor, the first control switch, the second control switch, the third control switch, the fourth control switch and the integrating transistor; the conversion unit includes: a transconductance amplifier;
The two integrating capacitors are controlled by the control signal, the current is alternately folded and integrated, and when any one integrating capacitor is folded and integrated, the upper polar plate voltage of the other integrating capacitor is reset;
each column in the infrared focal plane array shares one infrared readout circuit;
The input end of the transconductance amplifier is connected with the input end of the integrating transistor, and the output end of the transconductance amplifier is connected with the output end of the integrating transistor; the grid electrode of the integrating transistor receives an integrating signal, and the drain electrode of the integrating transistor is respectively connected with the first end of the first control switch, the first end of the fourth control switch, the second end of the reset switch and the in-phase end of the comparator;
The second end of the first control switch is respectively connected with the upper polar plate of the first integrating capacitor and the first end of the second control switch; the second end of the second control switch is respectively connected with the lower polar plate of the first integrating capacitor and the first end of the third control switch, and the lower polar plate of the first integrating capacitor receives reset voltage; the second end of the third control switch is respectively connected with the upper polar plate of the second integrating capacitor and the second end of the fourth control switch;
The lower polar plate of the second integrating capacitor receives the reset voltage; a first end of the reset switch receives the reset voltage; the inverting terminal of the comparator receives a reference voltage; the output end of the comparator is connected with the control logic unit; the control logic unit generates the control signals according to the overturning signals, and the control signals are used for controlling the opening or closing of the four control switches.
2. The circuit of claim 1, wherein the control signal comprises: a first control signal and a second control signal;
the first control switch and the third control switch are controlled by the first control signal;
the second control switch and the fourth control switch are controlled by the second control signal;
the first control switch and the third control switch are simultaneously opened or simultaneously closed;
the second control switch and the fourth control switch are simultaneously opened or simultaneously closed;
when the first control switch and the third control switch are opened, the second control switch and the fourth control switch are closed, and when the first control switch and the third control switch are closed, the second control switch and the fourth control switch are opened.
3. The circuit of claim 2, wherein the control logic unit alternately generates the first control signal and the second control signal based on the flip signals, the first control signal being generated when one of the flip signals is received the previous time, the second control signal being generated when one of the flip signals is received the next time.
4. The circuit of claim 2, wherein the first control switch and the third control switch are controlled by the first control signal to be closed, the second control switch and the fourth control switch to be opened, the first integrating capacitor performs folding integration on the current, and an upper plate voltage of the second integrating capacitor is reset to the reset voltage;
And when the second control switch and the fourth control switch are controlled by the second control signal to be closed, the first control switch and the third control switch are opened, the second integrating capacitor performs folding integration on the current, and meanwhile, the upper polar plate voltage of the first integrating capacitor is reset to the reset voltage.
5. The circuit of claim 4, wherein when the first integrating capacitor folds the current, an upper plate voltage of the first integrating capacitor gradually rises from the reset voltage until rising to the reference voltage, the comparator toggles, and the flipped signal is sent to the control logic unit;
When the second integrating capacitor performs folding integration on the current, the voltage of the upper polar plate of the second integrating capacitor gradually rises from the reset voltage until the voltage rises to the reference voltage, and the comparator turns over and sends the turning signal to the control logic unit.
6. The circuit of claim 5, wherein the circuit further comprises: and the counter is connected with the output end of the comparator and is used for recording the turnover times of the comparator during the period that the first integration capacitor and the second integration capacitor alternately perform folding integration on the current.
7. An analog-to-digital converter, the analog-to-digital converter comprising: a circuit as claimed in any one of claims 1 to 6.
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| CN114884492B (en) * | 2022-06-01 | 2024-07-19 | 北京大学 | Gm-CCO type-based comparator circuit applied to analog-to-digital converter |
| CN116470889B (en) * | 2023-04-10 | 2024-04-16 | 北京大学 | Comparator circuit, analog-digital converter and electronic equipment |
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