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CN114172517A - Infrared reading circuit and analog-to-digital converter - Google Patents

Infrared reading circuit and analog-to-digital converter Download PDF

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CN114172517A
CN114172517A CN202110948083.7A CN202110948083A CN114172517A CN 114172517 A CN114172517 A CN 114172517A CN 202110948083 A CN202110948083 A CN 202110948083A CN 114172517 A CN114172517 A CN 114172517A
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control switch
voltage
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integration
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CN114172517B (en
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周晔
鲁文高
于善哲
张雅聪
陈中建
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Peking University
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/50Analogue/digital converters with intermediate conversion to time interval
    • H03M1/52Input signal integrated with linear return to datum
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic

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Abstract

The invention provides an infrared reading circuit and an analog-to-digital converter, and relates to the technical field of infrared focal plane arrays. The circuit comprises: the device comprises a conversion unit, an integration unit, a comparator and a control logic unit; the conversion unit converts the voltage difference between the voltage of the diode detector and the voltage of the blind end detector into corresponding current and transmits the current to the integration unit; the control logic unit receives the turning signal sent by the comparator and sends a control signal to the integrating unit; the integration unit includes: and the two integrating capacitors are controlled by a control signal to alternately fold and integrate the current, and when any one of the integrating capacitors is folded and integrated, the voltage of the upper plate of the other integrating capacitor is reset. The invention avoids the delay of the comparator and the charging and discharging time of phase change for eliminating the reset of the integral capacitor, greatly reduces the nonlinearity, thereby improving the precision and the dynamic range of the ADC, improving the linearity on the premise of not increasing the power consumption and having higher practical value.

Description

Infrared reading circuit and analog-to-digital converter
Technical Field
The invention relates to the technical field of infrared focal plane arrays, in particular to an infrared reading circuit and an analog-to-digital converter.
Background
Infrared imaging is a detector technology that obtains infrared imaging by detecting thermal radiation of a target object. The uncooled infrared focal plane array detector has obvious advantages in the aspects of cost, portability, power consumption and the like, and is widely applied to the military and civil fields of night vision, monitoring, thermal imagery temperature measurement and the like. The design of the readout circuit is always a research difficulty and a hotspot of an uncooled infrared focal plane array, and can be divided into analog readout and digital readout according to a readout mode, wherein the digital readout completes analog-to-digital conversion through an on-chip integrated ADC (analog-to-digital converter), and the transmission path of an analog signal is shorter and the loss is less, so that the readout circuit has higher performance compared with the analog readout. The sensitivity of the infrared focal plane detector to the substrate temperature and the portability of the application scenario place rather severe limitations on the power consumption of the readout circuit, especially the power consumption of the ADC.
The folding integral ADC is a common ADC scheme of an infrared reading circuit, and has the advantages of simple circuit structure, low power consumption, high charge processing capacity and the like by folding and integrating signals on an integral capacitor.
However, in such an infrared readout circuit, nonlinearity is caused by the delay of the comparator and the charging and discharging time of the reset of the integrating capacitor, and the nonlinearity increases with the increase of the signal, thereby limiting the accuracy and dynamic range of the ADC. If the power consumption of the comparator is directly increased, although the delay can be reduced and the linearity can be improved, the power consumption budget of the uncooled infrared reading circuit is limited, and the overhigh power consumption can cause the overhigh temperature of the substrate and directly influence the performance of the thermosensitive detector. Therefore, how to improve the linearity without increasing the power consumption is an urgent problem to be solved.
Disclosure of Invention
The invention provides an infrared reading circuit and an analog-to-digital converter, and provides a circuit capable of improving linearity without increasing power consumption.
A first aspect of an embodiment of the present invention provides an infrared readout circuit, where the circuit includes: the device comprises a conversion unit, an integration unit, a comparator and a control logic unit;
the conversion unit receives the voltage of a diode detector and the voltage of a blind end detector in the infrared focal plane array, converts the voltage difference between the voltage of the diode detector and the voltage of the blind end detector into corresponding current and transmits the current to the integration unit;
the integration unit is controlled by the control logic unit and is used for folding and integrating the current;
the control logic unit receives the turning signal sent by the comparator and sends a control signal to the integrating unit;
wherein the integration unit includes: two integrating capacitors;
the two integrating capacitors are controlled by the control signal, the current is alternately folded and integrated, and when any one of the integrating capacitors is folded and integrated, the voltage of the upper plate of the other integrating capacitor is reset;
and each column in the infrared focal plane array shares one infrared readout circuit.
Optionally, the integration unit further comprises: four control switches;
the four control switches and the two integrating capacitors form a ping-pong reset structure;
the four control switches receive control signals, based on the ping-pong reset structure, the two integrating capacitors are controlled to alternately fold and integrate the current, and when any one integrating capacitor is folded and integrated, the voltage of the upper plate of the other integrating capacitor is reset.
Optionally, the circuit further comprises: a reset switch; the conversion unit includes: a transconductance amplifier; the integration unit further includes: an integrating transistor;
the four control switches are respectively: the first control switch, the second control switch, the third control switch and the fourth control switch; the two integrating capacitors are respectively: a first integrating capacitor and a second integrating capacitor;
the non-inverting terminal of the transconductance amplifier receives the voltage of the diode detector;
the inverting terminal of the transconductance amplifier receives the voltage of the blind end detector;
the output end of the transconductance amplifier is connected with the source electrode of the integrating transistor;
the grid electrode of the integration transistor receives an integration signal;
the drain electrode of the integration transistor is respectively connected with the first end of the first control switch, the first end of the fourth control switch, the second end of the reset switch and the in-phase end of the comparator;
the second end of the first control switch is respectively connected with the upper pole plate of the first integrating capacitor and the first end of the second control switch;
the second end of the second control switch is connected with the lower pole plate of the first integrating capacitor and the first end of the third control switch respectively, and the lower pole plate of the first integrating capacitor receives a reset voltage;
a second end of the third control switch is connected with an upper pole plate of the second integrating capacitor and a second end of the fourth control switch respectively;
the lower pole plate of the second integrating capacitor receives the reset voltage;
a first terminal of the reset switch receives the reset voltage;
the inverting terminal of the comparator receives a reference voltage.
Optionally, the output end of the comparator is connected with the control logic unit;
and the control logic unit generates the control signal according to the overturning signal, and the control signal is used for controlling the opening or closing of the four control switches.
Optionally, the control signal comprises: a first control signal and a second control signal;
the first control switch and the third control switch are controlled by the first control signal;
the second control switch and the fourth control switch are controlled by the second control signal;
the first control switch and the third control switch are opened or closed simultaneously;
the second control switch and the fourth control switch are opened or closed simultaneously;
when the first control switch and the third control switch are switched off, the second control switch and the fourth control switch are switched on, and when the first control switch and the third control switch are switched off, the second control switch and the fourth control switch are switched off.
Optionally, the control logic unit alternately generates the first control signal and the second control signal according to the flipping signal, generates the first control signal when receiving one of the flipping signals at the current time, and generates the second control signal when receiving one of the flipping signals at the next time.
Optionally, when the first control switch and the third control switch are controlled by the first control signal to be turned on, the second control switch and the fourth control switch are turned off, the first integration capacitor performs folding integration on the current, and simultaneously, the upper plate voltage of the second integration capacitor is reset to the reset voltage;
when the second control switch and the fourth control switch are controlled by the second control signal to be closed, the first control switch and the third control switch are switched off, the second integration capacitor performs folding integration on the current, and meanwhile, the upper plate voltage of the first integration capacitor is reset to the reset voltage.
Optionally, when the first integrating capacitor performs folding integration on the current, the voltage of the upper plate of the first integrating capacitor gradually rises from the reset voltage until the voltage rises to the reference voltage, the comparator turns over, and the turning signal is sent to the control logic unit;
when the second integrating capacitor performs folding integration on the current, the voltage of the upper electrode plate of the second integrating capacitor gradually rises from the reset voltage until the voltage rises to the reference voltage, and the comparator turns over and sends the turning signal to the control logic unit.
Optionally, the circuit further comprises: and the counter is connected with the output end of the comparator and is used for recording the turnover times of the comparator during the period that the first integrating capacitor and the second integrating capacitor alternately perform folding integration on the current.
A second aspect of an embodiment of the present invention provides an analog-to-digital converter, including: a circuit as claimed in any one of the first aspect.
According to the infrared reading circuit provided by the invention, the voltage difference between the voltage of the diode detector and the voltage of the blind end detector is converted into corresponding current by the conversion unit, and the corresponding current is transmitted to the integration unit; the integration unit includes: the two integrating capacitors are controlled by the control signal of the control logic unit to alternately fold and integrate the current. That is, when one of the integrating capacitors is folded and integrated, the upper plate voltage of the other integrating capacitor is reset.
Compared with the traditional folding integral ADC, the two integral capacitors alternately perform folding integral and alternately reset. For example, when one capacitor is integrated, the capacitor is not directly reset, but another capacitor which is reset in advance is switched to replace the capacitor for integration, so that the delay of a comparator and the phase change of the charge-discharge time for eliminating the reset of the integrated capacitor are avoided, the nonlinearity is greatly reduced, the precision and the dynamic range of the ADC are improved, the linearity is improved on the premise of not increasing the power consumption, and the high practical value is achieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a modular schematic of an infrared readout circuit according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a preferred infrared readout circuit in an embodiment of the present invention;
fig. 3 is a timing diagram illustrating operation of the infrared readout circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The inventor finds that the traditional folding integral ADC carries out N times of folding in the process of one-time integral quantization, and the charge Q on an integral capacitorintCan be written as:
Qint=IsigTint=Qeff+Qrst+Qε
=N×CVREF+N×Isigtrst+CVε#(1)
in the above formula, IsigRepresenting the current converted by the conversion unit, trstRepresents the total delay time (including the delay of the comparator, the charging and discharging time of the reset of the integrating capacitor and the time from the voltage at the same-phase end of the comparator to exceed the reference voltage and recover to the reference voltage), TintRepresenting the total integration time, QeffEffective charge, Q, representing the actual processing of the circuitrstRepresenting the charge lost to failure of the circuit to handle due to delay, QεRepresenting the residual charge on the integrating capacitor after the folding integration is completed, N being the number of folds, VεIs the margin voltage.
Ideally, the total delay time trstAnd the remainder VεZero, the size of the charge packet reset by each folding is CVREFThe number of folding times is Nideal=IsigTint/CVREF. But since the actual situation delay is not zero, the non-linearity Δ N can be calculated as follows:
Figure RE-GDA0003473445190000051
Figure RE-GDA0003473445190000052
in the above formula, the formula (2) is approximated because the margin V is actually usedεIt is possible to further refine the quantization process. As shown in the formula (3), the non-linearity Δ N depends on the current IsigAnd total delay time trstIncreases and thus limits the accuracy and dynamic range of the ADC.
Through a great deal of research and actual measurement, the inventor creatively provides the infrared reading circuit and the analog-to-digital converter of the embodiment of the invention, which can not only increase the power consumption, but also improve the linearity. The infrared readout circuit and the analog-to-digital converter according to the embodiment of the present invention are explained and explained in detail below.
Referring to fig. 1, a modular schematic diagram of an infrared readout circuit according to an embodiment of the present invention is shown. The infrared readout circuit includes: conversion unit, integral unit, comparator, control logic unit.
The conversion unit receives the voltage of the diode detector and the voltage of the blind end detector in the infrared focal plane array, converts the voltage difference between the voltage of the diode detector and the voltage of the blind end detector into corresponding current and transmits the current to the integration unit. In general, the converted current is extracted from the integrating capacitor to the converting unit, so that the voltage of the upper plate of the integrating capacitor is reduced in the process of folding integration.
The control logic unit receives the turning signal sent by the comparator and sends a control signal to the integrating unit; and the integration unit is controlled by the control logic unit to fold and integrate the current. Specifically, the integration unit includes: two integrating capacitors; the two integrating capacitors are controlled by a control signal to alternately fold and integrate the current, namely, when any one integrating capacitor is folded and integrated, the voltage of the upper plate of the other integrating capacitor is reset, so that when the other integrating capacitor is switched to be ready for starting to fold and integrate, the folding and integrating can be directly carried out without resetting before starting to fold and integrate like the traditional structure. Each column in the entire infrared focal plane array may share an infrared readout circuit of an embodiment of the present invention.
In the embodiment of the present invention, in order to implement the above functions, a preferable mode is to design the integration unit as a ping-pong reset structure. The integration unit further includes: four control switches; the four control switches and the two integrating capacitors form a ping-pong reset structure; the four control switches receive control signals, based on a ping-pong reset structure, the two integrating capacitors are controlled to alternately fold and integrate the current, and when any one of the integrating capacitors is folded and integrated, the voltage of the upper plate of the other integrating capacitor is reset. Of course, the embodiment of the present invention is not limited to this, and all circuits or components that can implement the above functions are all possible.
Referring to fig. 2, a schematic diagram of a preferred infrared readout circuit in an embodiment of the present invention is shown, where fig. 2 includes: transconductance amplifier GM, integrating transistor MP and first integrating capacitor C1A second integrating capacitor C2Reset switch SRA first control switch S1A second control switch S2A third control switch S3And a fourth control switch S4Comparator CMP, control logic unit control logic (hereinafter abbreviated CL for brevity) and Counter.
In fig. 2 the conversion unit is indicated by a transconductance amplifier GM, the non-inverting terminal of which receives the diode probe voltage (V in fig. 2)in) The inverting terminal of the transconductance amplifier GM receives the blind detector voltage (V in fig. 2)blind) (ii) a The output terminal of the transconductance amplifier GM is connected to the source of the integrating transistor MP. Of course, other components or circuits that can implement the function of the transconductance amplifier GM may be used as the conversion unit.
The gate of the integrating transistor MP receives the integrating signal INT; the drain of the integrating transistor MP and the first control switch S1First terminal, fourth control switch S4First end ofReset switch SRThe non-inverting terminal of the comparator CMP (the non-inverting terminal receives the integration voltage V)INT) Are respectively connected. During the period when the integration signal INT is at low level, the integration transistor MP is turned on, and the infrared readout circuit is in the folding integration stage to generate current ISIG(ii) a While the integration signal INT is at the high level, the integration transistor MP is turned off, and the infrared readout circuit does not operate.
First control switch S1Second terminal and first integrating capacitor C1Upper pole plate and second control switch S2Are respectively connected; second control switch S2Second terminal and first integrating capacitor C1Lower plate of (2), third control switch S3Are respectively connected with a first integrating capacitor C1The lower plate receives a reset voltage VSS
Third control switch S3Second terminal and second integrating capacitor C2Upper pole plate and fourth control switch S4The second ends of the first and second connecting rods are respectively connected; second integrating capacitor C2The lower plate receives a reset voltage VSS(ii) a Reset switch SRFirst terminal of (1) receives a reset voltage VSSReset switch SRControlled by a reset signal phiRST(ii) a The inverting terminal of the comparator CMP receives the reference voltage VREF
In the embodiment of the invention, the output end of the comparator CMP is connected with the control logic unit CL; the control logic unit CL is based on the flip signal (CMP in FIG. 2)OUT) And generating a control signal which is used for controlling the opening or closing of the four control switches.
Specifically, the control signal includes: a first control Signal (Signal 1 in fig. 2) and a second control Signal (Signal 2 in fig. 2); first control switch S1A third control switch S3Controlled by a first control signal; second control switch S2And a fourth control switch S4Controlled by a second control signal; first control switch S2And a third control switch S3Simultaneously open or simultaneously closed; second control switch S2And a fourth control switch S4Either simultaneously open or simultaneously closed. First, theA control switch S1And a third control switch S3When disconnected, the second control switch S2And a fourth control switch S4Closed, first control switch S1And a third control switch S3When closed, the second control switch S2And a fourth control switch S4And (5) disconnecting.
In the embodiment of the present invention, the control logic unit CL may alternately generate the first control signal and the second control signal according to the flip signal sent by the comparator CMP. In general, the first integrating capacitor C1When the current is folded and integrated, the first integrating capacitor C1From the reset voltage VSSGradually rises until the voltage rises to a reference voltage VREFAt this time, the comparator CMP inverts and sends an inversion signal to the control logic unit CL; second integrating capacitor C2When the current is folded and integrated, the second integrating capacitor C2From the reset voltage VSSGradually rises until the voltage rises to a reference voltage VREFThe comparator CMP inverts and sends an inversion signal to the control logic unit CL.
If the control logic unit CL generates the first control signal when receiving the first inversion signal, the control logic unit CL generates the second control signal when receiving the first inversion signal, and the control logic unit CL generates the first control signal when receiving the first inversion signal for the third time, and so on until the whole folding integration process is finished.
First control switch S1And a third control switch S3When the first control signal is closed, the second control switch S2And a fourth control switch S4Is turned off, at this time, the first integrating capacitor C1Folding integration is performed on the current, and simultaneously a second integrating capacitor C2Is reset to a reset voltage VSS(ii) a Second control switch S2And a fourth control switch S4Controlled by a second control signal S2When closed, the first control switch S1And a third control switch S3Is turned off, at this time, the second integrating capacitor C2Folding integration is carried out on the current, and meanwhile, a first integration capacitor C1Is reset to a reset voltage VSS
For the Counter, the Counter is connected to the output of the comparator CMP for recording the first integrating capacitor C1And a second integrating capacitor C2During the period of folding and integrating the current alternately, the flip times of the comparator CMP, which is the n-bit quantization result b of the ADCn...b1
In summary, with reference to the operation timing diagrams of the infrared readout circuit shown in fig. 2 and fig. 3, the operation principle of the infrared readout circuit according to the embodiment of the present invention is as follows:
when the analog-to-digital converter starts to work, if INT is at high level, the integrating transistor MP is switched off, the infrared reading circuit does not perform folding integration, only INT is at low level, the integrating transistor MP is switched on, the infrared reading circuit starts to perform folding integration, and firstly, the reset signal phiRETIs high, so that the switch S is resetRClosing, resetting the whole infrared reading circuit, and then resetting the signal phiRETWhen the voltage level is changed to low level, the two integrating capacitors start to perform folding integration, and the reset signal phi is reset in the whole folding integration processRETAre all held low.
When the folding integration is started, if the first control Signal1 is a high level Signal and the second control Signal2 is a low level Signal, the first control switch S is turned on1And a third control switch S3Closed, second control switch S2And a fourth control switch S4Off, then the first integrating capacitor C1Start folding integration, second integrating capacitor C2Because the loop is open, folding integration is naturally not possible, and the second integrating capacitor C2The upper plate voltage is reset voltage VSS
The first integrating capacitor C is due to the fact that the transconductance amplifier GM always converts the voltage difference of the two detectors into a current which is integrated over the integrating capacitor1Upper plate voltage V ofINTFrom the reset voltage VSSBegins to rise when the voltage of the upper plate VINTUp to a reference voltage VREFThe comparator CMP outputs an inverted signal CMPOUT(the flip signal is a pulse signal).
Comparator CMP outputs an inverted signal CMPOUTIn the control logic unit CL, the control logic unit CL receives the first control Signal1 and generates the second control Signal2 with a high level, at this time, the first control Signal1 is at a low level. Thus, the second control switch S2And a fourth control switch S4Closed, first control switch S1And a third control switch S3Off, then the second integrating capacitor C2The folding integration is started and, at the same time, the first integrating capacitor C1Because the loop is open, folding integration is naturally not possible, and the first integrating capacitor C1Is reset to a reset voltage VSS
The same folding integration process as that performed by the first integrating capacitor C, and the second integrating capacitor C2Upper plate voltage V ofINTFrom the reset voltage VSSBegins to rise when the voltage of the upper plate VINTUp to a reference voltage VREFWhile the comparator CMP outputs the flip signal CMP againOUTTo the control logic unit CL.
The control logic unit CL receives the first control Signal1, which is high, and the second control Signal1 is low. Thus, the first control switch S1And a third control switch S3Closed, second control switch S2And a fourth control switch S4Off, then the first integrating capacitor C1The folding integration is started again, and simultaneously the second integration capacitor C2Again because the loop is open, fold integration is not possible and the second integrating capacitor C2Is reset again to the reset voltage VSS. The above process is repeated until the entire folding integration is finished, i.e., INT becomes high level and the integrating transistor MP is turned off.
During the whole folding integration process, the Counter continuously records the first integration capacitor C1And a second integrating capacitor C2To current is connectedDuring the folding integration period, the number of flip times of the comparator CMP, which is the n-bit quantization result b of the ADCn...b1
Compared with the infrared reading circuit with the conventional structure, the infrared reading circuit provided by the embodiment of the invention has shorter total delay time because: in the conventional infrared readout circuit, the total delay time trst includes: delay time t of comparator CMPd2And the charging and discharging time t of resetting the integral capacitorchAnd the time t from the end voltage of the same phase of the comparator exceeding the reference voltage to the recovery to the reference voltaged1. The readout circuit of the embodiment of the invention uses a ping-pong reset structure and two integrating capacitors C1And C2The reset is carried out alternately, while one integration capacitor carries out the folding integration, the other integration capacitor is reset, and the other integration capacitor can directly start the folding integration, so that the delay time t of the comparator CMP is not neededd2And the charging and discharging time t of the reset of the integral capacitorchOnly the comparator non-inverting terminal voltage exceeds the reference voltage until the time t of recovering to the reference voltaged1E.g. as exemplarily shown in fig. 3, td1The total delay time of the infrared readout circuit according to the embodiment of the present invention is shorter than that of the conventional infrared readout circuit.
Based on the infrared readout circuit, an embodiment of the present invention further provides an analog-to-digital converter, where the analog-to-digital converter includes: an infrared readout circuit as described in any of the above.
In summary, in the infrared readout circuit according to the embodiment of the present invention, the conversion unit converts the voltage difference between the voltage of the diode detector and the voltage of the blind end detector into the corresponding current, and transmits the current to the integration unit; when any one of the integration capacitors is folded and integrated, the voltage of the upper plate of the other integration capacitor is reset.
Compared with the traditional folding integral ADC, the two integral capacitors alternately perform folding integral and alternately reset. For example, when one capacitor is integrated, the capacitor is not directly reset, but another capacitor which is reset in advance is switched to replace the capacitor for integration, so that the delay of a comparator and the phase change of the charge-discharge time for eliminating the reset of the integrated capacitor are avoided, the nonlinearity is greatly reduced, the precision and the dynamic range of the ADC are improved, the linearity is improved on the premise of not increasing the power consumption, and the high-voltage integrated circuit has high practical value.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. An infrared readout circuit, comprising: the device comprises a conversion unit, an integration unit, a comparator and a control logic unit;
the conversion unit receives the voltage of a diode detector and the voltage of a blind end detector in the infrared focal plane array, converts the voltage difference between the voltage of the diode detector and the voltage of the blind end detector into corresponding current and transmits the current to the integration unit;
the integration unit is controlled by the control logic unit and is used for folding and integrating the current;
the control logic unit receives the turning signal sent by the comparator and sends a control signal to the integrating unit;
wherein the integration unit includes: two integrating capacitors;
the two integrating capacitors are controlled by the control signal, the current is alternately folded and integrated, and when any one of the integrating capacitors is folded and integrated, the voltage of the upper plate of the other integrating capacitor is reset;
and each column in the infrared focal plane array shares one infrared readout circuit.
2. The circuit of claim 1, wherein the integration unit further comprises: four control switches;
the four control switches and the two integrating capacitors form a ping-pong reset structure;
the four control switches receive control signals, based on the ping-pong reset structure, the two integrating capacitors are controlled to alternately fold and integrate the current, and when any one integrating capacitor is folded and integrated, the voltage of the upper plate of the other integrating capacitor is reset.
3. The circuit of claim 2, further comprising: a reset switch; the conversion unit includes: a transconductance amplifier; the integration unit further includes: an integrating transistor;
the four control switches are respectively: the first control switch, the second control switch, the third control switch and the fourth control switch; the two integrating capacitors are respectively: a first integrating capacitor and a second integrating capacitor;
the non-inverting terminal of the transconductance amplifier receives the voltage of the diode detector;
the inverting terminal of the transconductance amplifier receives the voltage of the blind end detector;
the output end of the transconductance amplifier is connected with the source electrode of the integrating transistor;
the grid electrode of the integration transistor receives an integration signal;
the drain electrode of the integration transistor is respectively connected with the first end of the first control switch, the first end of the fourth control switch, the second end of the reset switch and the in-phase end of the comparator;
the second end of the first control switch is respectively connected with the upper pole plate of the first integrating capacitor and the first end of the second control switch;
the second end of the second control switch is connected with the lower pole plate of the first integrating capacitor and the first end of the third control switch respectively, and the lower pole plate of the first integrating capacitor receives a reset voltage;
a second end of the third control switch is connected with an upper pole plate of the second integrating capacitor and a second end of the fourth control switch respectively;
the lower pole plate of the second integrating capacitor receives the reset voltage;
a first terminal of the reset switch receives the reset voltage;
the inverting terminal of the comparator receives a reference voltage.
4. The circuit of claim 3, wherein the output of the comparator is connected to the control logic unit;
and the control logic unit generates the control signal according to the overturning signal, and the control signal is used for controlling the opening or closing of the four control switches.
5. The circuit of claim 4, wherein the control signal comprises: a first control signal and a second control signal;
the first control switch and the third control switch are controlled by the first control signal;
the second control switch and the fourth control switch are controlled by the second control signal;
the first control switch and the third control switch are opened or closed simultaneously;
the second control switch and the fourth control switch are opened or closed simultaneously;
when the first control switch and the third control switch are switched off, the second control switch and the fourth control switch are switched on, and when the first control switch and the third control switch are switched off, the second control switch and the fourth control switch are switched off.
6. The circuit of claim 5, wherein the control logic unit alternately generates the first control signal and the second control signal according to the flip signals, wherein the first control signal is generated when one of the flip signals is received at a previous time, and the second control signal is generated when one of the flip signals is received at a next time.
7. The circuit of claim 5, wherein the first control switch and the third control switch are controlled by the first control signal to be closed, the second control switch and the fourth control switch are opened, the first integration capacitor performs folding integration on the current, and simultaneously, the upper plate voltage of the second integration capacitor is reset to the reset voltage;
when the second control switch and the fourth control switch are controlled by the second control signal to be closed, the first control switch and the third control switch are switched off, the second integration capacitor performs folding integration on the current, and meanwhile, the upper plate voltage of the first integration capacitor is reset to the reset voltage.
8. The circuit of claim 7, wherein when the first integrating capacitor performs the folding integration on the current, the voltage of the upper plate of the first integrating capacitor gradually rises from the reset voltage until the voltage rises to the reference voltage, the comparator turns over, and the turning signal is sent to the control logic unit;
when the second integrating capacitor performs folding integration on the current, the voltage of the upper electrode plate of the second integrating capacitor gradually rises from the reset voltage until the voltage rises to the reference voltage, and the comparator turns over and sends the turning signal to the control logic unit.
9. The circuit of claim 8, further comprising: and the counter is connected with the output end of the comparator and is used for recording the turnover times of the comparator during the period that the first integrating capacitor and the second integrating capacitor alternately perform folding integration on the current.
10. An analog-to-digital converter, comprising: a circuit as claimed in any one of claims 1 to 9.
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