CN114171457B - Display panel and preparation method thereof - Google Patents

Abstract

The application discloses a display panel and a preparation method thereof, wherein the preparation method comprises the steps of providing a substrate; preparing a common electrode layer, a gate electrode layer and a gate insulating layer on the substrate; preparing a metal oxide layer and a data transmission layer on the gate insulating layer; wherein the step of preparing the metal oxide layer and the data transmission layer on the gate insulating layer comprises the following steps: a semitransparent photomask is adopted to carry out a yellow light process, and a photoresistive pattern of the data transmission layer, a required channel region and a pixel region is defined; etching to remove the film without the photoresist protection; ashing removes the photoresistance above the channel region and the pixel region, etching removes the data transmission layer of the channel region and the pixel region, and only retains the metal oxide layer above the data transmission layer. The technical effect of the application is that the fringe field switching liquid crystal panel is prepared by only adopting four photomasks, so that the cost is saved, the manufacturing efficiency is improved, and the aperture opening ratio of the display panel is improved.

Description

Display panel and manufacturing method thereof

technical field

The present application relates to the display field, in particular to a display panel and a preparation method thereof.

Background technique

Fringe Field Switching (FFS for short) technology is currently a technology applied in the field of liquid crystal display, which has the advantages of fast response speed, wide viewing angle and high light transmittance, and is widely used in notebook monitors, desktop monitors and TVs, etc. Terminal devices are also display technologies that have developed rapidly in recent years.

The core of FFS technology is thin film transistor (Thin Film Transistor, TFT for short) technology, but the TFT of FFS LCD panel is usually made of two layers of indium tin oxide ITO, which makes the production process of FFS LCD panel more complicated, and it will be more complex than ordinary LCD panel. Use 1-2 more masks. In order to reduce costs and improve manufacturing efficiency, reducing the number of FFS technology masks is one of the current research directions.

Contents of the invention

The purpose of the present application is to provide a display panel and its preparation method, which can solve the technical problems of the existing fringe field switch liquid crystal display panel, such as complex preparation process and large amount of photomask usage.

In order to achieve the above object, the present application provides a method for manufacturing a display panel, comprising the following steps: providing a substrate; preparing a common electrode layer, a gate layer and a gate insulating layer on the substrate; A metal oxide layer and a data transmission layer are prepared on the insulating layer; wherein, the step of preparing the metal oxide layer and the data transmission layer on the gate insulating layer includes: using a translucent mask to perform a yellow light process, Defining the photoresist pattern of the data transmission layer and the required channel region and pixel region; etching treatment to remove the film layer without the protection of the photoresist pattern; ashing treatment to remove the channel region and the pixel region The upper photoresist is etched to remove the data transmission layer of the channel region and the pixel region, and only the metal oxide layer above it remains.

Further, the step of preparing the common electrode layer and the gate layer on the substrate includes the following steps: sequentially coating the common electrode layer and the gate layer on the upper surface of the substrate; The mask is subjected to a yellow light process to define the photoresist pattern of the gate layer and the common electrode layer; the first semi-transparent mask includes a first complete shielding area, a first semi-transparent shielding area and a first opening area ; etching treatment to remove the film layer without the protection of the photoresist pattern; ashing treatment to remove a layer of photoresist, exposing the gate layer corresponding to the first semi-transparent shielding area, and etching treatment to remove the exposed gate layer The pole layer is ashed again to remove the remaining photoresist.

Further, the step of preparing a gate insulating layer on the substrate includes: depositing a gate insulating layer material on the upper surface of the gate layer, the common electrode layer and the substrate, and the gate The material of the insulating layer includes silicon oxide or a mixture of silicon nitride and silicon oxide. The deposition thickness is 3000-4500 angstroms. It is patterned with a photomask to expose part of the gate layer pattern to form a gate insulating layer. .

Further, the step of preparing a metal oxide layer and a data transmission layer on the gate insulating layer includes: sequentially depositing a metal oxide layer and a data transmission layer on the gate insulating layer; The second translucent mask includes a second complete shielding area, a second semitransparent shielding area, and a second opening area; the second semitransparent shielding area is set opposite to the channel area and the pixel area; ashing process Removing the photoresist above the channel region and the pixel region corresponding to the second semi-transparent shielding region, etching to remove the data transmission layer of the channel region and the pixel region, leaving only the metal oxide layer above it Object layer, ashing treatment to remove the remaining photoresist.

Further, the deposition thickness of the metal oxide layer is 500-1500 angstroms, and the material of the metal oxide layer is at least one of indium gallium zinc oxide, indium gallium tin oxide, and indium gallium zinc tin oxide. The deposition thickness of the data transmission layer is 2500-5000 angstroms, and the data transmission layer is a laminated structure composed of at least two layers of metal materials, wherein one layer of material is copper, and the remaining at least one layer of material is At least one of molybdenum, titanium, and niobium.

Further, the preparation method of the display panel further includes the following steps: depositing a passivation layer material on the data transmission layer, the metal oxide layer and the gate insulating layer, and the passivation layer The material includes silicon oxide or silicon oxynitride, and the deposition thickness is 2000-4000 angstroms. It is patterned with a photomask to expose part of the data transmission layer and part of the metal oxide layer to form a passivation layer.

Further, the preparation method of the display panel further includes: performing laser treatment on the substrate, conducting the exposed metal oxide layer to form a pixel electrode, and the metal oxide layer covered by the passivation layer has semiconductor properties , as a channel, and the conductive metal oxide layers on both sides of the channel serve as source and drain, forming a thin film transistor structure.

Further, adjusting the size of the patterned opening of the passivation layer and adjusting the intensity of the laser during the laser treatment to control the diffusion depth of conductorization, so that the length of the channel is less than 3 microns.

Further, the material of the common electrode layer is a transparent material, including indium tin oxide or indium zinc oxide, and the thickness of the film layer is 500-1000 angstroms; the material of the gate layer is a laminate composed of at least two layers of metal materials structure, wherein one layer is made of copper, and the remaining at least one layer is made of at least one of molybdenum, titanium and niobium; the thickness of the film layer is 2500-5000 angstroms.

In order to achieve the above purpose, the present application also provides a display panel, which is prepared by the method for preparing a display panel as described above.

The technical effect of the present application is that only four photomasks are used to prepare a fringe field switch liquid crystal panel, which reduces the number of photomasks, reduces the preparation process, saves process costs, improves manufacturing efficiency, and simultaneously increases the aperture ratio of the display panel.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a flowchart of a method for preparing a display panel provided in an embodiment of the present application;

FIG. 2 is a schematic structural view of the coating common electrode layer and gate layer provided by the embodiment of the present application;

Fig. 3 is a schematic diagram of the yellow light process using the first translucent mask provided by the embodiment of the present application;

Fig. 4 is a schematic view of the structure provided by the embodiment of the present application after removing the film layer without the protection of the first photoresist layer;

FIG. 5 is a schematic structural view of the patterned gate layer provided by the embodiment of the present application;

FIG. 6 is a schematic structural view of a prepared gate insulating layer provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of depositing a metal oxide layer and a data transmission layer provided in an embodiment of the present application;

Fig. 8 is a schematic diagram of the yellow light process using the second translucent mask provided by the embodiment of the present application;

Fig. 9 is a schematic structural view provided by the embodiment of the present application after removing the film layer without the protection of the second photoresist layer;

FIG. 10 is a schematic structural diagram of the patterned data transmission layer provided by the embodiment of the present application;

Fig. 11 is a schematic structural diagram after depositing a passivation layer provided in the embodiment of the present application;

FIG. 12 is a schematic structural diagram of a display panel provided by an embodiment of the present application.

Explanation of reference signs:

1. Substrate; 2. Common electrode layer; 3. Gate layer; 4. Gate insulating layer; 5. Metal oxide layer; 6. Data transmission layer; 7. Passivation layer;

10. The first photoresist layer; 20. The second photoresist layer;

100. The first translucent mask; 200. The second translucent mask;

110. The first fully shielded area; 120. The first translucent shaded area; 130. The first open area;

210, the second complete shielding area; 220, the second translucent shielding area; 230, the second open area.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application. In addition, it should be understood that the specific implementations described here are only used to illustrate and explain the present application, and are not intended to limit the present application. In this application, unless stated to the contrary, the used orientation words such as "up" and "down" usually refer to up and down in the actual use or working state of the device, specifically the direction of the drawing in the drawings ; while "inside" and "outside" refer to the outline of the device.

Embodiments of the present application provide a display panel and a manufacturing method thereof. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.

As shown in FIG. 1 to FIG. 12 , the manufacturing method of the display panel provided by the embodiment of the present application includes steps S1-S.

S1 provides a substrate 1, which is generally a glass substrate and functions as a substrate.

S2 prepares the common electrode layer 2 , the gate layer 3 and the gate insulating layer 4 on the upper surface of the substrate 1 . Specifically, a common electrode layer 2 and a gate layer 3 are sequentially coated on the upper surface of the substrate 1 (see FIG. 2 ), and the material of the common electrode layer 2 is a transparent material, including indium tin oxide or indium zinc oxide. , the film thickness is 500-1000 angstroms. The film thickness of the gate layer 3 is 2500-5000 angstroms, and the material of the gate layer 3 is a laminated structure composed of at least two layers of metal materials, wherein one layer of material is copper (Cu), and the rest The material of at least one layer is at least one of molybdenum (Mo), titanium (Ti), and niobium (Nb). In this embodiment, the gate layer 3 can be copper/molybdenum, copper/titanium, copper/titanium Molybdenum-titanium, copper/molybdenum-niobium and other structures.

As shown in FIG. 3 , the first translucent photomask 100 is used to carry out the yellow light process to define the photoresist pattern of the gate layer 3, the common electrode layer 2, the pixel area and the terminal area, which is the first photoresist Layer 10. Specifically, the first translucent mask 100 includes a first complete shielding area 110 , a first translucent shielding area 120 and a first opening area 130 . Wherein, the first complete shielding region 110 is arranged opposite to the terminal region and part of the pixel region, the first semi-transparent shielding region 120 is arranged opposite to the partial pixel region, and the first opening region 130 is opposite to the remaining part Relatively arranged, the required patterns of the gate layer 3, the common electrode layer 2 and the terminal area are defined. The thickness of the photoresist layer defined by the first translucent shielding area 120 is smaller than the thickness of the photoresist layer defined by the first complete shielding area 110 . Adjusting the transparency of the first translucent shielding region 120 in the first translucent mask 100 can change the thickness of the photoresist layer defined therein.

As shown in FIG. 4 , through the first etching process, the film layers not protected by the first photoresist layer 10 (the gate layer and the common electrode layer not covered by the photoresist) are removed.

As shown in FIG. 5 , oxygen gas is used for ashing treatment to remove one layer of photoresist layer, exposing the gate layer corresponding to the first semi-transparent shielding region 120, ensuring that the gate layer corresponding to the first semi-transparent shielding region 120 can be The defined photoresist layer can be removed. The gate layer above the common electrode layer in the pixel area is removed by second etching to make it transparent, and all remaining photoresist is removed by ashing treatment again to form a patterned gate layer 3 and common electrode layer 2 .

As shown in FIG. 6, a gate insulating layer material is deposited on the upper surfaces of the gate layer 3, the common electrode layer 2, and the substrate 1, and the gate insulating layer material includes silicon oxide or silicon nitride and A mixture of silicon oxide, deposited in a thickness of 3000-4500 angstroms. And use a photomask to pattern it, expose part of the gate layer pattern in the terminal area, and form the gate insulating layer 4 . The gate insulating layer 4 plays an insulating role to prevent problems such as short circuit between the gate layer 3 and other metal layers.

S3 preparing a metal oxide layer 5 and a data transmission layer 6 on the gate insulating layer 4 . Specifically, a metal oxide layer 5 and a data transmission layer 6 are sequentially deposited on the upper surface of the gate insulating layer 4 (see FIG. 7 ). The deposition thickness of the metal oxide layer 5 is 500-1500 angstroms, and the material of the metal oxide layer 5 is indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide At least one of the substances (IGZTO). The deposition thickness of the data transmission layer 6 is 2500-5000 angstroms, and the data transmission layer 6 is a laminated structure composed of at least two layers of metal materials, wherein one layer of material is copper (Cu), and the remaining at least one layer The material is at least one of molybdenum (Mo), titanium (Ti), and niobium (Nb). In this embodiment, the data transmission layer 6 can be copper/molybdenum, copper/titanium, copper/molybdenum-titanium, Copper/molybdenum niobium and other structures.

As shown in FIG. 8 , the second translucent photomask 200 is used to perform a yellow light process to define the photoresist pattern of the data transmission layer 6 and the required channel region and pixel region to form the second photoresist layer 20 . Wherein, the second translucent mask 200 includes a second complete shielding area 210 , a second translucent shielding area 220 and a second opening area 230 . The second translucent shielding region 220 is disposed opposite to the channel region and the pixel region, and the thickness of the photoresist layer defined by the second semitransparent shielding region 220 is smaller than that defined by the second complete shielding region 210 defines the thickness of the photoresist layer. Adjusting the transparency of the second translucent shielding region 220 in the second translucent mask 200 can change the thickness of the photoresist layer defined therein.

As shown in FIG. 9 , the etching process removes the film layer not protected by the second photoresist layer 20 (the data transmission layer and the metal oxide layer not covered by the second photoresist layer 20 ).

As shown in FIG. 10, oxygen is used for ashing treatment to remove a photoresist layer, and the ashing treatment removes the channel region corresponding to the second translucent shielding region 220 and the photoresist above the pixel region, exposing The metal oxide layer corresponding to the second translucent shielding region 220 only needs to ensure that the photoresist layer defined by the second translucent shielding region 220 can be removed. The etching process removes the data transmission layer of the channel area and the pixel area, leaving only the metal oxide layer above it, and the ashing process removes the remaining photoresist to form a patterned data transmission layer 6 and metal oxide Layer 5.

S4 deposits a layer of passivation layer material on the data transmission layer 6, the metal oxide layer 5 and the gate insulating layer 4, the passivation layer material includes silicon oxide or silicon oxynitride, and the deposition thickness is The thickness is 2000-4000 angstroms, and a photomask is used to pattern it to expose part of the data transmission layer and part of the metal oxide layer to form a passivation layer 7 (see FIG. 11 ).

S5 performs laser processing on the substrate 1 to conduct the exposed metal oxide layer 5 to form a pixel electrode, and the metal oxide layer 5 covered by the passivation layer 7 is not conducted and still has semiconductor properties, as channel, and the conductive metal oxide layers on both sides of the channel are used as source and drain to form a thin film transistor structure TFT (see FIG. 12 ). Adjusting the size of the patterned opening of the passivation layer 7 and adjusting the intensity of the laser during the laser treatment to control the diffusion depth of conductorization, so that the length of the channel is less than 3 microns, which effectively reduces the size of the TFT and can improve Opening rate.

The technical effect of the preparation method of the display panel described in the embodiment of the present application is that only four photomasks are used to prepare the fringe field switch liquid crystal panel, the number of photomasks is reduced, the preparation process is reduced, the process cost is saved, and the manufacturing efficiency is improved. Improve the aperture ratio of the display panel.

As shown in FIG. 12 , the embodiment of the present application also provides a display panel, which is prepared by the method for preparing a display panel described above. The display panel includes a substrate 1, a common electrode layer 2, a grid layer 3, a grid The polar insulating layer 4 , the metal oxide layer 5 , the data transmission layer 6 and the passivation layer 7 also include functional film layers such as a light emitting layer, which are not described in detail in this embodiment.

The technical effect of the display panel described in the embodiment of the present application is that in the preparation process of the display panel, only four photomasks are used to prepare a fringe field switch liquid crystal panel, which reduces the number of photomasks, reduces the preparation process, saves process costs, and improves The manufacturing efficiency can be improved, and the aperture ratio of the display panel can be improved at the same time.

The above is a detailed introduction to a display panel and its preparation method provided by the embodiment of the present application. In this paper, specific examples are used to illustrate the principle and implementation of the present application. The description of the above embodiment is only used to help understand the present application. The method of application and its core idea; at the same time, for those skilled in the art, according to the idea of this application, there will be changes in the specific implementation and scope of application. In summary, the content of this specification should not be understood as Limitations on this Application.

Claims (6)

1. A method for manufacturing a display panel, comprising the steps of:

providing a substrate;

preparing a common electrode layer, a gate electrode layer and a gate insulating layer on the substrate;

preparing a metal oxide layer and a data transmission layer on the gate insulating layer;

depositing a passivation layer material above the data transmission layer, the metal oxide layer and the gate insulating layer, and patterning the passivation layer material by using a photomask to expose part of the data transmission layer and part of the metal oxide layer to form a passivation layer; and

performing laser processing on the substrate, conducting the exposed metal oxide layer to form a pixel electrode, wherein the metal oxide layer covered by the passivation layer has semiconductor performance and serves as a channel, and the conducted metal oxide layers at two sides of the channel serve as a source electrode and a drain electrode to form a thin film transistor structure;

adjusting the size of a patterned opening of the passivation layer and adjusting the laser intensity during laser treatment to control the diffusion depth of the conductor so that the length of the channel is less than 3 microns;

wherein the step of preparing the metal oxide layer and the data transmission layer on the gate insulating layer comprises the following steps:

sequentially depositing a metal oxide layer and a data transmission layer on the gate insulating layer;

performing a yellow light process by using a second semitransparent mask to define the data transmission layer and the photoresist patterns of the required channel region and the pixel region; the second semitransparent light cover comprises a second complete shielding region, a second semitransparent shielding region and a second opening region, and the second semitransparent shielding region is arranged opposite to the channel region and the pixel region;

etching to remove the metal oxide layer without the protection of the photoresist pattern and the data transmission layer;

and ashing to remove the photoresist above the channel region and the pixel region corresponding to the second semitransparent shielding region, etching to remove the data transmission layer of the channel region and the pixel region, and only retaining the metal oxide layer above the data transmission layer, wherein the ashing to remove the residual photoresist.

2. The method of manufacturing a display panel according to claim 1, wherein the step of manufacturing the common electrode layer and the gate electrode layer on the substrate comprises the steps of:

a film plating common electrode layer and a grid layer are sequentially formed on the upper surface of the substrate;

performing a yellow light process by using a first semi-transparent photomask to define photoresist patterns of the grid electrode layer and the public electrode layer; the first half-transparent photomask comprises a first complete shielding region, a first half-transparent shielding region and a first opening region;

etching to remove the film without the protection of the photoresist pattern;

and ashing to remove one layer of photoresist, exposing the grid layer corresponding to the first semi-transparent shielding region, etching to remove the exposed grid layer, and ashing again to remove the residual photoresist.

3. The method of manufacturing a display panel according to claim 2, wherein the step of manufacturing a gate insulating layer on the substrate comprises:

and depositing a gate insulating layer material on the upper surfaces of the gate layer, the common electrode layer and the substrate, wherein the gate insulating layer material comprises silicon oxide or a mixture of silicon nitride and silicon oxide, the deposition thickness is 3000-4500 meter, and patterning is performed on the gate insulating layer material by using a photomask to expose part of the gate layer pattern, so as to form the gate insulating layer.

4. The method for manufacturing a display panel according to claim 1, wherein,

the deposition thickness of the metal oxide layer is 500-1500 Emi, and the material of the metal oxide layer is at least one of indium gallium zinc oxide, indium gallium tin oxide and indium gallium zinc tin oxide;

the deposition thickness of the data transmission layer is 2500-5000 angstroms, the data transmission layer is a laminated structure formed by at least two layers of metal materials, one layer of the material is copper, and the rest at least one layer of the material is at least one of molybdenum, titanium and niobium.

5. The method for manufacturing a display panel according to claim 2, wherein,

the public electrode layer is made of transparent material and comprises indium tin oxide or indium zinc oxide, and the thickness of the film layer is 500-1000 m;

the material of the grid electrode layer is a laminated structure formed by at least two layers of metal materials, wherein one layer of material is copper, and the rest at least one layer of material is at least one of molybdenum, titanium and niobium; the thickness of the film layer is 2500-5000 Emi.

6. A display panel prepared by the method of preparing a display panel according to any one of claims 1 to 5.

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