CN102157562B - Method for manufacturing bottom gate metal oxide thin film transistor - Google Patents

Abstract

A method for preparing a bottom-gate metal oxide thin film transistor in the field of semiconductor manufacturing technology, by sequentially preparing a gate electrode and a metal oxide material; then coating a photoresist on the surface of the metal oxide material and applying chemical mechanical to the photoresist layer Polishing for planarization; then annealing or plasma treatment of the metal oxide not masked by the photoresist; finally stripping the photoresist and magnetron sputtering to deposit source and drain electrode materials and forming them by photolithography and wet etching source and drain electrodes. The invention utilizes the characteristic that the metal oxide material can be converted from an insulator to a semiconductor after special treatment to manufacture a metal oxide thin film transistor with a special structure in the active layer, which can effectively prevent the source and drain film from breaking.

Description

Fabrication method of bottom gate metal oxide thin film transistor

technical field

The invention relates to a method for preparing a transistor in the field of semiconductor technology, in particular to a method for preparing a bottom-gate metal oxide thin film transistor.

Background technique

At present, semiconductor materials such as amorphous silicon (a-Si) and polycrystalline silicon (p-Si) are mostly used in the active layer of the thin film transistor (TFT) technology. Among them, a-Si TFT is the most widely used and can cover almost all sizes of flat panel display (FPD) products. Limited by the uniformity of film quality, p-Si TFT is currently only suitable for small and medium-sized products. In terms of device characteristics, a-Si TFT has the advantages of simple structure and good mass production uniformity, but at the same time has disadvantages such as low mobility (about 0.5cm ² /V s) and poor light stability; p-Si TFT Although it has much higher mobility (>10cm ² /V·s) than a-Si TFT, it also has disadvantages such as complex structure, large leakage current and poor mass production uniformity. With the rapid development of FPD technology, higher and higher requirements are put forward for the performance of TFT. Judging from the characteristics of a-Si TFT and p-Si TFT, the above requirements cannot be fully met, so more advanced TFT technology needs to be developed. From the current point of view, metal oxide TFT is one of the most promising alternatives.

Metal oxide as the active layer material of TFT has the following two advantages: (1) bandgap (>3.0eV), which brings very good light stability, so different from a-Si TFT, metal oxide TFT It can be made into a fully transparent device, thereby significantly increasing the aperture ratio of the panel, thereby reducing the power consumption of the display; (2) high mobility (about 10cm ² /V·s). Generally speaking, metal oxide TFT has both the technical advantages of a-Si TFT and p-Si TFT, and is feasible in mass production, so it is very likely to replace a-Si TFT as a flat panel display in the near future. The mainstream of active electronic drive devices.

At present, metal oxide thin film transistors are still in the research and development stage before mass production. From the published literature, the device structure and manufacturing process of the metal oxide TFT adopted by the research institute mostly adopts the technology similar to that of a-Si TFT. The most common one is the bottom gate staggered (Inverted-Staggered) structure and related manufacturing process that have been widely used in the actual production of a-Si TFT. 1 is a schematic cross-sectional view of a common structure of a metal oxide thin film transistor, including a glass substrate 110, a gate electrode layer 120 disposed on the substrate, a gate insulating layer 130 disposed on the substrate and the gate electrode layer, and a gate insulating layer disposed on the gate insulating layer. metal oxide semiconductor layer 140 , drain electrode layer 151 and source electrode layer 152 . The device protection layer, pixel electrode layer, etc. are omitted here because they are irrelevant to the present invention. FIG. 2 is a generally used process flow for manufacturing the device structure shown in FIG. 1, including forming a gate electrode pattern T10, forming a gate insulating layer T20, forming a metal oxide semiconductor layer pattern T30, and forming a source-drain electrode layer pattern T40.

Research experience shows that when the device structure shown in Figure 1 is used, the rupture of the source and drain films is likely to occur at the positions of the dashed boxes A and B, because there is a step at the boundary of the active layer that causes the source and drain films to due to stress concentration. When the device is used for driving a flat panel display, the above-mentioned breakage can lead to the occurrence of point defects.

Contents of the invention

The present invention aims at the above-mentioned deficiencies in the prior art, and provides a method for preparing a bottom-gate metal oxide thin film transistor, which utilizes the characteristics that the metal oxide material can be converted from an insulator to a semiconductor after special treatment, and the active layer has a special structure The metal oxide thin film transistor can effectively prevent the source-drain film from breaking.

The present invention is achieved through the following technical solutions, and the present invention comprises the following steps:

The first step is to sputter a layer of gate electrode film on the substrate by magnetron sputtering and form the gate electrode by photolithography and wet etching;

The wet etching refers to etching the etching material by immersing it in an etching solution composed of 55wt% H ₃ PO ₄ , 15% HNO ₃ and 5wt% CH ₃ COOH.

The second step is to sequentially use plasma-enhanced chemical vapor deposition gate insulating layer material on the gate electrode, and use AC magnetron sputtering metal oxide material;

The plasma-enhanced chemical vapor deposition refers to: with the assistance of the plasma discharge process, the reaction substances undergo a chemical reaction under gaseous conditions to generate solid substances that are deposited on the surface of the heated substrate, thereby producing a solid film, wherein the gate insulation Layer material means: silicon dioxide or silicon nitride.

The metal oxide material refers to zinc oxide, indium gallium zinc oxide, indium zinc oxide or indium gallium oxide, the carrier concentration of which is below 10 ¹⁰ /cm ³ .

The third step is to apply photoresist on the surface of the metal oxide material and planarize the photoresist layer by chemical mechanical polishing;

The thickness of the photoresist layer is 1.2-2.0 microns; the use of chemical mechanical polishing refers to polishing the photoresist layer flat with a pressure of 100-150 gm/cm ² at a speed of 60-200 rpm.

The fourth step is to convert the metal oxide not masked by the photoresist into a semiconductor with a carrier concentration increased to 10 ¹³ -10 ¹⁵ cm ^-3 by annealing or plasma treatment;

The annealing refers to the process of heat treatment at 200-400° C. under vacuum or reducing atmosphere; the plasma treatment refers to the process of using argon plasma to treat the surface of the device for 1-3 minutes.

In the fifth step, the photoresist is stripped off, the source and drain electrode materials are deposited by magnetron sputtering, and the source and drain electrodes are formed by photolithography and wet etching.

The stripping refers to removing the photoresist by using a stripping solution mixed with dimethyl sulfoxide and monoethanolamine in a weight ratio of 7:3.

The magnetron sputtering described in the first step, the second step and the fifth step refers to the use of argon plasma under the action of an electric field and a magnetic field to bombard the surface of the target with accelerated high-energy ions. After energy exchange, the target The atoms on the surface of the material escape from the original lattice and transfer to the surface of the substrate to form a film. The sputtering power is 100W, the gas pressure is 1Pa, and the ratio of oxygen to argon in the sputtering gas ranges from 1:20 to 1: 100 and the argon gas flow rate is 30 sccm, and the gate electrode film is made of aluminum, molybdenum or chromium metal or alloys thereof.

The structure of the metal oxide thin film transistor involved in the present invention is: a metal oxide thin film transistor formed on a glass substrate, comprising a gate electrode layer, a gate insulating layer, a metal oxide layer and a source-drain electrode layer. The gate electrode layer is located on the glass substrate, the gate insulating layer is located on the gate electrode and the glass substrate and covers the gate electrode layer, and the metal oxide layer is located on the gate insulating layer and completely covers the gate insulating layer, The source-drain electrode layer is located on the metal oxide layer and overlaps the metal oxide layer near the channel region. It is characterized in that: the metal oxide layer is divided into two regions according to the different conductivity characteristics, that is, the semiconductor region and the insulator region. The metal oxide thin film near the channel region exhibits semiconductor properties; the metal oxide in other regions exhibits insulator properties.

The difference between the structure of the metal oxide thin film transistor prepared by the present invention and the common device structure is that the boundary of the island of the active layer is eliminated. Compared with the prior art, the present invention makes full use of the characteristics that metal oxide materials can be divided into semiconductors and insulators under different process conditions, and converts the active layer islands in the common structure of metal oxide thin film transistors to be embedded in equal-thickness In this way, the step caused by the existence of the island boundary of the active layer is removed, thereby greatly reducing the stress concentration in the upper source and drain film materials, and thus solving the problem that the source and drain films are easy to break, Effectively improved the production pass rate.

Description of drawings

FIG. 1 is a schematic diagram of a common structure of a bottom-gate metal oxide thin film transistor.

FIG. 2 is a schematic diagram of a common process flow of a bottom-gate metal oxide thin film transistor.

FIG. 3 is a schematic diagram of the structure of the metal oxide thin film transistor of the present invention.

Fig. 4 is the process flow chart of embodiment 1.

Fig. 5 is the process flow chart of embodiment 2.

Fig. 6 is the process flow chart of embodiment 3.

Detailed ways

The following is a detailed description of the embodiments of the present invention. This embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operating procedures are provided, but the protection scope of the present invention is not limited to the following implementation example.

Example 1

As shown in Figure 4, the manufacturing process of the bottom gate metal oxide thin film transistor of the present invention comprises the following steps:

a) Deposit a layer of gate electrode film on the glass substrate and form the desired pattern by photolithography and etching (as shown in Figure 4(a)).

b) Depositing a layer of gate insulating layer material (as shown in FIG. 4( b )).

c) Depositing a layer of metal oxide material to make it exhibit insulator properties by controlling the process conditions (as shown in Figure 4(c)).

d) Apply photoresist 710 and use chemical mechanical polishing (CMP) technology to planarize the photoresist, so that other areas except the vicinity of the channel area are covered by photoresist (as shown in 4(d)) .

e) Treating the exposed oxide film to transform it into a semiconductor characteristic by adopting vacuum annealing method 810 (as shown in 4(e)).

f) Removing the photoresist (as shown in 4(f)).

g) Depositing a layer of source-drain electrode thin film and forming the required pattern through photolithography and etching processes, and finally completing the device preparation (as shown in Figure 3).

In the process step a), the film forming process usually adopts magnetron sputtering technology, and the target material adopts AlNd and MoNb alloy; the etching process adopts traditional wet etching technology, and the etching solution adopts a mixed solution of phosphoric acid, sulfuric acid and acetic acid .

The process step b) generally adopts plasma enhanced chemical vapor deposition technology. Taking silicon dioxide deposition as an example, silane and oxygen are used as reaction gases, the discharge power is 200W, and the substrate heating temperature is 300°C.

In the process step c), the AC magnetron sputtering technology is usually used to form a film, and the target material is a sintered body of oxide ceramics such as ZnO, InGaZnO, InZnO, and InGaO. The sputtering pressure is 1Pa, and the carrier concentration in the metal oxide film is kept below 10 ¹⁰ /cm ³ by adjusting the ratio of oxygen and argon in the sputtering gas, so as to exhibit insulator properties. The etching process usually adopts traditional wet etching technology. The etching solution is a mixture of phosphoric acid and hydrogen peroxide.

In the process step d), the photoresist thickness is usually 1.2-2.0 microns, the chemical mechanical polishing pressure range is 100-150 gm/cm ² , and the rotation speed is 60-200 rpm.

In the process step e), the sample is heated to 300° C. under vacuum, kept for 60 minutes, and then cooled in air. The carrier concentration of the treated oxide film is increased to within the range of 10 ¹³ to 10 ¹⁵ cm ^-3 , so as to exhibit semiconductor characteristics.

In the process step f), the stripping solution usually adopts DMSO:MEA=7:3 (weight ratio).

In the process step g), the film forming process usually adopts magnetron sputtering technology, and the target material adopts AlNd and MoNb alloy; the etching process adopts traditional wet etching technology, and the etching solution adopts a mixed solution of phosphoric acid, sulfuric acid and acetic acid .

Example 2

As shown in FIG. 5 , the process flow of this embodiment is similar to that of Embodiment 1. The difference is that in FIG. 5( e ), the annealing method ( 820 ) in a reducing atmosphere is used to realize the transformation of the metal oxide from an insulator to a semiconductor.

In the process step 820, the sample is heated to 300° C. under a reducing atmosphere such as hydrogen or nitrogen, kept for 30 minutes, and then cooled in air. The carrier concentration of the processed metal oxide thin film is increased to the range of 10 ¹³ to 10 ¹⁵ cm ^-3 , so as to exhibit semiconductor characteristics.

Example 3

As shown in FIG. 6 , the process flow of this embodiment is similar to that of Embodiment 1. The difference is that in FIG. 6( e ), the plasma treatment method ( 830 ) is used to realize the transformation of the metal oxide from an insulator to a semiconductor.

In the process step 830, the sample is placed in a vacuum chamber, and the surface of the sample is treated with argon plasma for 3-5 minutes, and the discharge power is 150W. The carrier concentration of the processed metal oxide thin film is increased to the range of 10 ¹³ to 10 ¹⁵ cm ^-3 , so as to exhibit semiconductor characteristics.

Using the process flow in the above-mentioned embodiments 1-3, the process steps of photolithography and etching of the active layer are saved, and chemical mechanical polishing and annealing (or plasma treatment) processes are used instead, compared with the traditional process shown in Figure 2 The process is simple.

3 is a schematic structural diagram of a bottom-gate metal oxide thin film transistor prepared by the method of the present invention. Its basic structure is as follows: formed on a glass substrate substrate 310, including a gate electrode layer 320, a gate insulating layer 330, a metal oxide layer 340 , a drain electrode layer 351 and a source electrode layer 352 .

The gate electrode layer 310 is located on the glass substrate and is usually made of metal aluminum, molybdenum, chromium and other materials. In large-size flat-panel display backplane technology, the gate electrode layer is generally composed of aluminum neodymium/molybdenum-niobium alloy, which can not only obtain good electrical conductivity, but also prevent defects such as "hills" on the surface of the film. The thickness of the gate electrode layer is usually about 300 nanometers.

The gate insulating layer is located on the gate electrode and the glass substrate and covers the gate electrode layer, and is usually made of silicon dioxide or silicon nitride, with a film thickness of about 300 nanometers.

The metal oxide layer is located on the gate insulating layer, and may be a polycrystalline metal oxide material represented by zinc oxide (ZnO), or an amorphous metal oxide material represented by indium gallium zinc oxide (IGZO). It is characterized in that: the metal oxide layer is divided into two regions according to the different conductivity characteristics, that is, a semiconductor region and an insulator region; the metal oxide film near the channel region exhibits semiconductor characteristics; the metal oxide films in other regions exhibit insulator characteristics. The thickness of the metal oxide layer may be in the range of 100-300 nanometers.

The source-drain electrode layer is located on the gate insulating layer and overlaps the metal oxide layer near the channel, and is usually made of metal aluminum, molybdenum, chromium and other materials. In large-size flat panel display backplane technology, the gate electrode layer is generally composed of Composed of molybdenum-niobium/aluminum-neodymium/molybdenum-niobium alloy, it can not only obtain good electrical conductivity, but also prevent defects such as "hills" on the upper and lower surfaces of the film. The thickness of the source-drain electrode layer is usually about 300 nanometers.

Compared with the prior art, the structural feature of the metal oxide thin film transistor prepared by the present invention is that the boundary of the island of the active layer is eliminated. The present invention makes full use of the characteristics that metal oxide materials can be divided into semiconductors and insulators under different process conditions, and converts the active layer islands in the common structure of metal oxide thin film transistors to be embedded in insulating layer materials of equal thickness, so that The step caused by the existence of the island boundary of the active layer is removed, thereby greatly reducing the stress concentration in the upper source and drain thin film materials, thereby solving the problem that the source and drain thin films are easy to break, and effectively improving the production pass rate.

Claims (8)

1. the preparation method of a bottom gate metal oxide thin-film transistor is characterized in that, may further comprise the steps:

The first step, adopt magnetron sputtering one deck gate electrode film and form gate electrode by photoetching and wet etching at substrate;

Second step, using plasma strengthens chemical vapour deposition (CVD) gate insulation layer material successively on gate electrode, and adopts AC magnetic controlled sputtered metal oxide material;

The 3rd step, adopt chemico-mechanical polishing to carry out planarization at metal oxide materials surface applied photoresist and to photoresist layer;

The 4th step, by annealing in process or plasma treatment not by the metal oxide of photoresist masking, make it to be converted into carrier concentration and increase to 10 ¹³-10 ¹⁵Cm ^-3Semiconductor;

The 5th step, stripping photoresist and magnetron sputtering deposition source-drain electrode material also form source-drain electrode by photoetching and wet etching.

2. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1, it is characterized in that, the first step, magnetron sputtering described in second step and the 5th step refers to: utilize argon plasma under the effect in electric field and magnetic field, the high-energy ion bombardment target material surface that is accelerated, after the energy exchange, the atom of target material surface breaks away from former lattice and overflows, transfer to substrate surface and film forming, sputtering power is 100W, gas pressure is 1Pa, the proportion of oxygen and argon gas is in the sputter gas: 1: 20～1: 100 and argon flow amount are 30sccm, and the material of gate electrode film wherein is: aluminium, molybdenum or chromium metal or its alloy.

3. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1 is characterized in that, described wet etching refers to: it is 55wt%H that the etching material is immersed in composition ₃PO ₄, 15wt%HNO ₃, 5wt%CH ₃COOH and 25wt%H ₂Corrode in the etching liquid of O.

4. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1, it is characterized in that, described plasma enhanced chemical vapor deposition refers to: the auxiliary reactive material down in the plasma discharge process issues biochemical reaction in the gaseous state condition, generate the substrate surface that solid matter is deposited on heating, and then making solid film, gate insulation layer material wherein refers to: silicon dioxide or silicon nitride.

5. according to the preparation method of the described bottom gate metal oxide thin-film transistor of above-mentioned arbitrary claim, it is characterized in that described metal oxide materials refers to: zinc oxide, indium oxide gallium zinc, indium zinc oxide or indium oxide gallium, its carrier concentration is 10 ¹⁰/ cm ³Below.

6. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1 is characterized in that, the thickness of the photoresist layer described in the 3rd step is the 1.2-2.0 micron; Described employing chemico-mechanical polishing refers to: adopt 100-150gm/cm ²Pressure, photoresist layer is polished smooth with the rotating speed of 60-200rpm.

7. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1 is characterized in that, the annealing described in the 4th step refers to: under vacuum or reducing atmosphere in the process of 200～400 ℃ of heat treated; Described plasma treatment refers to: adopt argon plasma that device is carried out 1～3 minute surface-treated process.

8. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1 is characterized in that, peeling off described in the 5th step refers to: adopt dimethyl sulfoxide (DMSO) and monoethanolamine by weight for the mixing stripper of 7:3 photoresist being removed.

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