CN102157564B - Preparation method of top gate metal oxide thin film transistor (TFT) - Google Patents

Abstract

A method for preparing a top-gate metal oxide thin film transistor in the field of semiconductor technology, by sequentially preparing source-drain electrodes and metal oxide materials; then coating photoresist on the surface of the metal oxide material and using the photoresist layer chemical mechanical polishing; and annealing or plasma treatment of the metal oxide not masked by the photoresist, and finally stripping off the photoresist and magnetron sputtering to deposit the gate insulating layer material and forming the gate by wet etching. The invention utilizes the characteristic that the metal oxide material can be converted from a semiconductor to a conductor after special treatment, and can form a reliable ohmic contact between the metal oxide film and the source and drain electrodes.

Description

Fabrication method of top gate metal oxide thin film transistor

technical field

The invention relates to a method for preparing a transistor in the field of semiconductor technology, in particular to a method for preparing a top-gate metal oxide thin film transistor.

Background technique

Thin film transistors (TFTs) have been widely used in the field of flat panel display (FPD) technologies such as liquid crystal and organic light emitting (OLED). At present, semiconductor materials such as amorphous silicon (a-Si) and polycrystalline silicon (p-Si) are mostly used in the active layer of the TFT technology. Among them, a-Si TFT is the most widely used and can cover flat panel display products of almost all sizes. Limited by the uniformity of film quality, p-Si TFT is currently only suitable for small and medium-sized products. In terms of device characteristics, a-Si TFT has the advantages of simple structure and good mass production uniformity, but at the same time has disadvantages such as low mobility (about 0.5cm ² /V·s) and poor light stability; although p-Si TFT It has a much higher mobility (>10cm ² /V·s) than a-Si TFT, but it also has disadvantages such as complex structure, large leakage current and poor mass production uniformity. With the rapid development of FPD technology, higher and higher requirements are put forward for the performance of TFT. Judging from the characteristics of a-SiTFT and p-Si TFT, the above requirements cannot be fully met, so new TFT technologies need to be developed. From the current point of view, metal oxide TFT is one of the most promising substitutes.

Metal oxide as the active layer material of TFT has the following two advantages: (1) bandgap (>3.0eV), which brings very good light stability, so different from a-Si TFT, metal oxide TFT It can be made into a fully transparent device, thereby significantly increasing the aperture ratio of the panel, thereby reducing the power consumption of the display; (2) high mobility (~10cm ² /V·s). Generally speaking, metal oxide TFT has the technical advantages of a-Si TFT and p-Si TFT at the same time, and is feasible in mass production, so it is very likely to become an active electronic drive device for flat panel display in the near future mainstream.

According to the published research results, the device structure of the metal oxide TFT currently used is the bottom gate staggered (Inverted-Staggered) structure, which has been widely used in the actual production of a-Si TFT. In addition, top-gate staggered structures have also been reported in the literature. Accompanying drawing 1 is a schematic cross-sectional view of a common top-gate staggered metal oxide thin film transistor, including a glass substrate 110, a source electrode 121 arranged on the substrate and a drain electrode layer 122 arranged on the substrate and the source-drain electrode layer The metal oxide semiconductor layer 130, the gate insulating layer 140 disposed on the metal oxide semiconductor layer, and finally the gate electrode layer disposed on the gate insulating layer. Accompanying drawing 2 is the process flow commonly used in manufacturing the device structure shown in Fig. 1, including forming the source-drain electrode pattern T10, forming the metal oxide semiconductor layer pattern T20, forming the gate insulating layer T30, and forming the gate electrode layer pattern T40.

Research experience shows that it is often difficult to form a real ohmic contact between the metal oxide semiconductor layer and the source and drain electrodes when the device structure shown in Figure 1 is adopted, which will significantly reduce the on-state current of the thin film transistor; when the device is used When used as a flat-panel display driver, sometimes it will lead to insufficient charging of pixels.

Contents of the invention

Aiming at the above-mentioned deficiencies in the prior art, the present invention provides a method for preparing a top-gate metal oxide thin film transistor, which utilizes the characteristic that the metal oxide material can be converted from a semiconductor to a conductor after special treatment, and can make the metal oxide thin film and A reliable ohmic contact is formed between the source and drain electrodes.

The present invention is achieved through the following technical solutions, and the present invention comprises the following steps:

The first step is to use magnetron sputtering source and drain electrode materials on the substrate and form source and drain electrodes by photolithography and wet etching;

The wet etching refers to etching the etching material by immersing it in an etching solution whose composition is 55wt% H ₃ PO ₄ , 15% HNO ₃ and 5% CH ₃ COOH.

The second step is to use plasma-enhanced chemical vapor deposition of metal oxide materials on the source and drain electrodes;

The plasma-enhanced chemical vapor deposition refers to: with the assistance of the plasma discharge process, the reaction substances undergo a chemical reaction under gaseous conditions, and the solid substances are deposited on the surface of the heated substrate to form a solid film.

The metal oxide refers to zinc oxide, indium gallium zinc oxide, indium zinc oxide or indium gallium oxide, the carrier concentration of which is below 10 ¹⁰ /cm ³ .

The third step is to apply photoresist on the surface of the metal oxide material and perform chemical mechanical polishing on the photoresist layer;

The thickness of the photoresist layer is 1.2-2.0 microns; the chemical mechanical polishing refers to polishing the photoresist layer flat with a pressure of 100-150 gm/cm ² at a speed of 60-200 rpm.

The fourth step is to convert the metal oxide not masked by the photoresist into a semiconductor with a carrier concentration increased to 10 ¹³ -10 ¹⁵ cm ^-3 by annealing or plasma treatment;

The annealing refers to the process of heat treatment at 200-400° C. under vacuum or reducing atmosphere; the plasma treatment refers to the process of using argon plasma to treat the surface of the device for 1-3 minutes.

In the fifth step, the photoresist is stripped off, the gate insulating layer material is deposited by magnetron sputtering, and the gate is formed by wet etching.

The stripping refers to removing the photoresist by using a mixed stripping liquid with a weight ratio of dimethyl sulfoxide and monoethanolamine at a weight ratio of 7:3.

The magnetron sputtering described in the first and fifth steps refers to the use of argon plasma under the action of an electric field and a magnetic field to bombard the surface of the target with accelerated high-energy ions. After energy exchange, the atoms on the surface of the target Escape from the original crystal lattice, transfer to the surface of the substrate to form a film, the sputtering power is 100W, the gas pressure is 1Pa, the ratio of oxygen to argon in the sputtering gas ranges from 1:20 to 1:100 and argon The flow rate is 30 sccm, and the material of the gate insulating layer is: aluminum, molybdenum or chromium metal or their alloys.

The structure of the top-gate metal oxide thin film transistor involved in the present invention is as follows: a top-gate metal oxide thin film transistor is formed on a glass substrate and includes a source-drain electrode layer, a metal oxide layer, a gate insulating layer and a gate electrode layer. The source-drain electrode layer is located on the glass substrate, the metal oxide layer is located on the source-drain electrode layer and overlaps the source-drain electrode layer near the channel region, and the gate insulating layer is located between the source-drain electrode layer and the metal oxide layer. The oxide layer is above and completely covers the above two layers, and the gate electrode layer is above the gate insulating layer and completely covers the channel region. It is characterized in that: the metal oxide layer is divided into two regions according to different conductivity characteristics, that is, a semiconductor region and a conductor region. The region directly above the source and drain is conductive; the metal oxide in other regions is semiconductive.

The source and drain electrodes of the metal oxide thin film transistor prepared according to the present invention are in direct contact with the metal oxide film (ie conductor) with high carrier concentration, instead of the structure in which the source and drain electrodes are in contact with the oxide semiconductor in the conventional technology. In this way, because of the tunnel effect, reliable ohmic contact can be formed between the source and drain electrodes and the active layer. Compared with the prior art, the present invention makes full use of the characteristics that metal oxide materials can be divided into semiconductors and conductors under different process conditions, and converts the metal oxides above the source and drain electrodes into conductors. Reliable ohmic contact is formed between objects, thereby increasing the on-state current and solving the technical problem of insufficient charging in display driving.

Description of drawings

Figure 1 is a schematic diagram of a common structure of a top-gate metal oxide thin film crystal.

FIG. 2 is a schematic diagram of a common process flow of a top-gate metal oxide thin film transistor.

FIG. 3 is a schematic structural diagram of a top-gate metal oxide thin film transistor of the present invention.

Fig. 4 is the process flow chart of embodiment 1.

Fig. 5 is the process flow chart of embodiment 2.

Fig. 6 is the process flow chart of embodiment 3.

Detailed ways

The embodiments of the present invention are described in detail below. This embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operating procedures are provided, but the protection scope of the present invention is not limited to the following implementation example.

Example 1

As shown in Figure 4, the present embodiment comprises the following process steps:

a) Deposit a layer of source-drain electrode thin film on the glass substrate and form the desired pattern by photolithography and etching (as shown in Figure 4(a)).

b) Depositing a layer of metal oxide material to make it exhibit semiconductor characteristics by controlling the process conditions (as shown in Figure 4(b)).

c) Coating photoresist 610 on the surface of the device and using chemical mechanical polishing (CMP) technology to planarize, so that other areas except A and B areas are covered by photoresist (as shown in Figure 4 (c) shown).

d) Treat the oxide film not masked by the photoresist to convert it into a conductor by vacuum annealing treatment 710 (as shown in FIG. 4( d )).

e) stripping off the photoresist (as shown in Figure 4(e)).

f) Depositing a gate insulating layer (as shown in FIG. 4(f)).

g) Depositing a layer of gate electrode film and forming the required pattern by photolithography and etching to complete the device preparation (as shown in Figure 3).

In the process step a), the film forming process usually adopts magnetron sputtering technology, and the target material adopts AlNd and MoNb alloy; the etching process adopts traditional wet etching technology, and the etching solution adopts a mixed solution of phosphoric acid, sulfuric acid and acetic acid .

The process step b) usually adopts AC magnetron sputtering sputtering technology to form a film, and the target material is a sintered body of oxide ceramics such as ZnO, InGaZnO, InZnO, and InGaO. The sputtering pressure is 1Pa, and the carrier concentration in the metal oxide film is kept below 10 ¹⁰ /cm ³ by adjusting the ratio of oxygen and argon in the sputtering gas, so as to exhibit insulator properties. The etching process usually adopts traditional wet etching technology. The etching solution is a mixture of phosphoric acid and hydrogen peroxide.

In the process step c), the photoresist thickness is usually 1.2-2.0 microns, the chemical mechanical polishing pressure range is 100-150 gm/cm ² , and the rotation speed is 60-200 rpm.

In said process step d), the sample is heated to 300° C. in vacuum, kept for 60 minutes, and then cooled in air. The carrier concentration of the treated oxide film is increased to within the range of 10 ¹³ to 10 ¹⁵ cm ^-3 , so as to exhibit semiconductor characteristics.

In the process step e), the stripping solution usually adopts DMSO:MEA=7:3 (weight ratio).

The process step f) usually adopts plasma enhanced chemical vapor deposition technology. Taking silicon dioxide deposition as an example, silane and oxygen are used as reaction gases, the discharge power is 200W, and the substrate heating temperature is 300°C.

In the process step g), the film forming process usually adopts magnetron sputtering technology, and the target material adopts AlNd and MoNb alloy; the etching process adopts traditional wet etching technology, and the etching solution adopts a mixed solution of phosphoric acid, sulfuric acid and acetic acid .

Example 2

As shown in FIG. 5 , the process flow of this embodiment is similar to that of Embodiment 1. The difference is that in FIG. 5( d ), the annealing method ( 720 ) in a reducing atmosphere is used to realize the transformation of the metal oxide from an insulator to a semiconductor.

In the process step 720, the sample is heated to 300° C. under a reducing atmosphere such as hydrogen or nitrogen, kept for 30 minutes, and then cooled in air. The carrier concentration of the processed metal oxide thin film is increased to the range of 10 ¹³ to 10 ¹⁵ cm ^-3 , so as to exhibit semiconductor characteristics.

Example 3

As shown in FIG. 6 , the process flow of this embodiment is similar to that of Embodiment 1. The difference is that in FIG. 6( d ), the plasma treatment method ( 730 ) is used to realize the transformation of the metal oxide from an insulator to a semiconductor.

In the process step 730, the sample is placed in a vacuum chamber, and the surface of the sample is treated with argon plasma for 3-5 minutes, and the discharge power is 150W. The carrier concentration of the processed metal oxide thin film is increased to the range of 10 ¹³ to 10 ¹⁵ cm ^-3 , so as to exhibit semiconductor characteristics.

Accompanying drawing 3 is the structure diagram of the top gate metal oxide thin film transistor manufactured according to the method proposed by the present invention, and its basic structure is as follows: formed on the glass substrate 310, comprise a drain electrode layer 321 and source electrode layer 322, a metal An oxide layer 330 , a gate insulating layer 340 , and a gate electrode layer 350 .

The source-drain electrode layer is located on a glass substrate and is usually made of metal aluminum, molybdenum, chromium and other materials. In large-size flat panel display backplane technology, the source-drain electrode layer is generally made of aluminum neodymium/molybdenum-niobium alloy, which can obtain Good electrical conductivity can prevent defects such as "hills" on the surface of the film. The thickness of the source-drain electrode layer is usually about 300 nanometers.

The metal oxide layer is located on the source-drain electrode layer and overlaps the source-drain electrode near the channel region, and may be a polycrystalline metal oxide material represented by zinc oxide (ZnO), or an indium gallium zinc oxide (IGZO) is the representative amorphous metal oxide material. It is characterized in that: the metal oxide layer is divided into two regions according to different conductivity characteristics, that is, a conductor region and a semiconductor region. The metal oxide thin film in the area directly above the source and drain exhibits conductor properties; the metal oxide in other areas exhibits semiconductor properties. The thickness of the metal oxide layer may be in the range of 100-300 nanometers.

The gate insulating layer is located on the metal oxide layer and the source-drain electrode layer and covers the above two thin films, usually made of silicon dioxide or silicon nitride, with a film thickness of about 300 nanometers.

The gate electrode layer is located on the gate insulating layer and is usually made of metal aluminum, molybdenum, chromium and other materials. In large-size flat panel display backplane technology, the gate electrode layer is generally composed of molybdenum-niobium/aluminum-neodymium/molybdenum-niobium alloy, which can not only obtain good electrical conductivity but also prevent defects such as "hills" on the surface of the film. The thickness of the gate electrode layer is usually about 300 nanometers.

Compared with the prior art, the source and drain electrodes of the metal oxide thin film transistor prepared by the present invention are in direct contact with the metal oxide film (i.e. conductor) with high carrier concentration, instead of the source and drain electrodes in the common technology and the oxide semiconductor contact structure. In this way, a reliable ohmic contact will be formed between the source and drain electrodes and the active layer due to the tunnel effect. The invention makes full use of the characteristics that metal oxide materials can be divided into semiconductors and conductors under different process conditions, converts the metal oxide above the source and drain electrodes into conductors, and forms a reliable ohmic contact between the source and drain electrodes and the metal oxide , thereby increasing the on-state current and solving the technical problem of insufficient charging in display driving.

Claims (6)

1. A method for preparing a top gate metal oxide thin film transistor, comprising the following steps: The first step is to use magnetron sputtering source and drain electrode materials on the substrate and form source and drain electrodes by photolithography and wet etching; The second step is to use plasma-enhanced chemical vapor deposition of metal oxide materials on the source and drain electrodes; The third step is to apply photoresist on the surface of the metal oxide material and perform chemical mechanical polishing on the photoresist layer; The fourth step is to convert the metal oxide not masked by the photoresist into a semiconductor with a carrier concentration increased to 10 ¹³ -10 ¹⁵ cm ^-3 by annealing or plasma treatment; The annealing refers to the process of heat treatment at 200-400°C under vacuum or reducing atmosphere; the plasma treatment refers to the use of argon plasma to treat the metal oxide not masked by the photoresist. 1 to 3 minutes surface treatment process; In the fifth step, the photoresist is stripped off, the gate insulating layer material is deposited by magnetron sputtering, and the gate is formed by wet etching. 2. the preparation method of top gate metal oxide thin film transistor according to claim 1 is characterized in that, the magnetron sputtering described in the first step and the fifth step refers to: utilize argon plasma in electric field and Under the action of a magnetic field, the accelerated high-energy ions bombard the surface of the target. After the energy exchange, the atoms on the surface of the target escape from the original lattice and transfer to the surface of the substrate to form a film. The sputtering power is 100W and the gas pressure is 1Pa. , the ratio of oxygen to argon in the sputtering gas ranges from 1:20 to 1:100 and the argon flow rate is 30 sccm, and the material of the gate insulating layer is silicon dioxide or silicon nitride. 3. The method for preparing a top-gate metal oxide thin film transistor according to claim 1, wherein said plasma-enhanced chemical vapor deposition refers to: under the assistance of a plasma discharge process, the reaction substance is deposited under gaseous conditions. A chemical reaction occurs, and a solid substance is deposited on the surface of the heated substrate to form a solid film. 4. The method for preparing a top-gate metal oxide thin film transistor according to any one of claims 1-3, wherein said metal oxide refers to: zinc oxide, indium gallium zinc oxide, indium zinc oxide or Indium gallium oxide has a carrier concentration below 10 ¹⁰ /cm ³ . 5. the preparation method of top gate metal oxide thin film transistor according to claim 1 is characterized in that, the thickness of the photoresist layer described in the 3rd step is 1.2-2.0 micron; Described chemical mechanical polishing is Refers to: using a pressure of 100-150gm/cm ² and a rotation speed of 60-200rpm to polish the photoresist layer flat. 6. The method for preparing a top-gate metal oxide thin film transistor according to claim 1, wherein said stripping refers to: using a mixture of dimethyl sulfoxide and monoethanolamine at a weight ratio of 7:3 solution to remove photoresist.

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