CN113851397A - A kind of unsealing method of stacked package chip - Google Patents
A kind of unsealing method of stacked package chip Download PDFInfo
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- CN113851397A CN113851397A CN202111042727.2A CN202111042727A CN113851397A CN 113851397 A CN113851397 A CN 113851397A CN 202111042727 A CN202111042727 A CN 202111042727A CN 113851397 A CN113851397 A CN 113851397A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
公开了一种堆叠封装芯片的开封方法，所述堆叠封装芯片包括引线框、堆叠于所述引线框上的多个管芯、以及覆盖所述引线框和所述多个管芯的封装料，所述多个管芯堆叠成台阶状，在所述多个管芯的边缘形成与金属线连接的台阶面，所述开封方法包括：根据所述多个管芯的位置，获取倾斜角；按照所述倾斜角，调整研磨方向与所述堆叠封装芯片之间的相对角度，去除所述封装料的至少部分以及切断所述金属线。本发明提供的堆叠封装芯片开封方法，通过根据所述多个管芯的位置，计算出倾斜角；并按照所述倾斜角，相对于水平面倾斜放置所述堆叠封装管芯；使得被遮挡的金属线能够顺利完成开封。
Disclosed is a method for unsealing a stacked package chip, wherein the stacked package chip includes a lead frame, a plurality of dies stacked on the lead frame, and a packaging compound covering the lead frame and the plurality of dies, The plurality of dies are stacked in a stepped shape, and a step surface connected to the metal wire is formed on the edges of the plurality of dies, and the unsealing method includes: obtaining an inclination angle according to the positions of the plurality of dies; The inclination angle adjusts the relative angle between the grinding direction and the stacked package chips, removes at least part of the encapsulant and cuts the metal lines. The method for unsealing a stacked package chip provided by the present invention calculates a tilt angle according to the positions of the plurality of dies; and according to the tilt angle, the stacked package dies are tilted relative to the horizontal plane; The line can be unsealed smoothly.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an unsealing method of stacked packaged chips.
Background
The surface of the stacked packaged chip is wrapped with a layer of thicker package, so that the purposes of protecting, supporting, radiating, providing electric connection and reducing the volume of a packaged product are achieved. In failure analysis of a chip, it is necessary to open a package.
The current unsealing methods can be divided into chemical unsealing and mechanical unsealing: the chemical unsealing adopts a chemical corrosion method to remove the packaging material, and the corrosivity of the packaging material on the substrate and the component is uncontrollable to a certain extent, so that the component and the substrate cannot be completely separated; mechanical unsealing employs a grinding method such as grinding (Polish)/automatic grinding (Autopolish) integral and partial unsealing; the mechanical partial decapping can selectively separate the components.
However, as the requirements of electronic products for miniaturization, function integration and large storage space are increased, the miniaturization and high-density packaging forms of chips are more and more mainstream, and the more complex packaged chips also provide new challenges for the decapsulation and failure analysis of the packaged chips while improving the logic operation function and the storage space: in the prior art, only the metal wire connection at the outer side of the tube core can be broken by grinding through mechanical unsealing, and the metal wire connection of a complex stacking structure which is directly above and shielded by the tube core cannot be separated.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a package on package chip unsealing method to realize the unsealing of the metal lines of the shielded die.
A method for unsealing a stacked package chip including a lead frame, a plurality of dies stacked on the lead frame, and an encapsulant covering the lead frame and the plurality of dies, the plurality of dies being stacked in a step shape, a step surface connected with a metal wire being formed at an edge of the plurality of dies,
the unsealing method includes:
acquiring a tilt angle according to the positions of the plurality of dies;
and adjusting a relative angle between the grinding direction and the stacked packaging chips according to the inclination angle, removing at least part of the packaging material and cutting the metal wire.
Preferably, the tilt angle is measured.
Preferably, the tilt angle is calculated.
Preferably, the spacing between adjacent dies of the stacked packaged chips is the same, and the width of the step surface is the same.
Preferably, the tilt angle is calculated from the spacing between adjacent dies and the width of the step face.
Preferably, the calculation method of the inclination angle is:
where, α is an inclination angle, h is a distance between adjacent dies, and l is a width of the step surface.
Preferably, in the steps of removing at least part of the encapsulant and cutting the metal lines, the stacked package chips are placed obliquely with respect to a horizontal plane according to the inclination angle.
Preferably, the stacked packaged chips are placed obliquely with respect to a horizontal plane by controlling a height difference between both sides of the lead frame.
Preferably, the height difference between the two sides of the lead frame is H:
H＝A*Sinα
where α is the tilt angle and a is the width of the lead frame.
Preferably, multiple dies are stacked together at the same tilt angle.
Preferably, multiple dies are stacked together at different tilt angles.
According to the unsealing method of the stacked packaged chip, the inclination angle is calculated according to the positions of the plurality of tube cores; and placing the stacked package die obliquely relative to the horizontal plane according to the inclination angle; therefore, the shielded metal wire can be smoothly unsealed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic structural diagram of a stacked package chip according to a first embodiment of the present invention;
fig. 2 illustrates a conventional decap process of a stacked package chip;
fig. 3 is a flowchart illustrating an unsealing method of stacked packaged chips according to a first embodiment of the present invention;
fig. 4 is a schematic view showing a first inclination angle of stacked package chips according to a first embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a structure of stacking packaged chips obliquely arranged with respect to a horizontal plane at a first inclination angle;
FIG. 6 is a schematic diagram showing a structure of stacking packaged chips obliquely arranged with respect to a horizontal plane at a second inclination angle;
FIG. 7 shows a scanned image of individual stacked package chips;
fig. 8 shows an unsealing diagram of a stacked package chip according to a second embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another area, the expression "directly above … …" or "above and adjacent to … …" will be used herein.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1 shows a schematic structural diagram of a stacked package chip according to a first embodiment of the present invention, and as shown in fig. 1, the stacked package chip 100 includes a lead frame 110, a plurality of dies 120 stacked on the lead frame 110, and an encapsulant 130 covering the lead frame 110 and the plurality of dies 120. Wherein the plurality of dies 120 are stacked in a step shape and have step surfaces 150 formed at edges thereof, and metal wires 140 are connected between the step surfaces 150 of the adjacent dies and between the step surfaces 150 of the lower dies and the lead frame 110.
During the unsealing process, a portion of the encapsulant 130 needs to be broken to cut the wire 140, and the wire 130 is typically ground off using a grinding tool.
Fig. 2 illustrates a conventional package on package chip decapping process, as shown in fig. 2, the plurality of dies 120 are dies 1201, 1202, 1203, 1204, 1205, 1206, 1207, and 1208, and in the conventional decapping method, the package on package chip 100 is horizontally placed, and the grinding tool 160 grinds the metal wire 140 on each step surface 150 of the encapsulant 130 and the plurality of dies 120 along a vertical horizontal plane. During the grinding process, the height of the grinding tool 160 and the relative position of the metal wire 140 need to be adjusted several times to grind the metal wire 140 connected to each step surface 150. The metal wires connected to the step surfaces of the die 1201, the die 1202, the die 1203 and the die 1204 can be cut off smoothly, but the metal wires connected to the step surfaces of the die 1205 and the die 1206 cannot be cut due to the shielding of the die 1201, the die 1202, the die 1203 and the die 1204.
Fig. 3 is a flowchart illustrating an unsealing method of a stacked package chip according to a first embodiment of the present invention, and as shown in fig. 3, the unsealing method of a stacked package chip according to the present embodiment includes the following steps.
S10: the tilt angle is obtained based on the positions of the plurality of dies of the stacked packaged chips.
The tilt angle of the stacked packaged chips can be obtained by calculation, measurement, or specific parameters marked on the product. In this step, the tilt angle of the stacked packaged chips is calculated, and the calculation process of the tilt angle will be described in detail below.
FIG. 4 is a schematic view showing a process of obtaining a tilt angle of stacked packaged chips according to the first embodiment; as shown in fig. 4, die 1201, die 1202, die 1203, and die 1204 are stacked together at a first tilt angle with their edges forming a step plane; die 1205, die 1206, die 1207, and die 1208 are stacked together at a second tilt angle, with the edges forming a step plane. Wherein the first and second tilt angles have different tilt directions.
The first tilt angle a is calculated from a distance h between adjacent dies and a step width l.
The spacing between adjacent dies of the stacked packaged chip 100 is the same, and is h, where the spacing between adjacent dies is the distance from the top surface of the lower die to the top surface of the adjacent upper die, for example, the spacing from the top surface of the die 1201 to the top surface of the die 1202; further, the step widths of the step surfaces 150 are the same and are all l; in this embodiment, each step width is the distance between the edge of the lower die to the edge of the adjacent upper die, e.g., the distance between the edge of die 1201 and the edge of die 1202. The first tilt angle is calculated from the spacing h between adjacent dies and the step width l of the step face as:
where, α is the first tilt angle, h is a distance between adjacent dies of the stacked package chip 100, and l is a step width of the step plane 150.
Similarly, the second inclination angle θ is calculated in the same manner.
S20: and adjusting a relative angle between the grinding direction and the stacked packaging chips according to the inclination angle, removing at least part of the packaging material and cutting the metal wire.
In this step, the stacked package chip 100 is placed to be inclined with respect to a horizontal plane in accordance with the inclination angle. In this embodiment, the placement angle of the stacked package chips is adjusted to adapt to the polishing direction of the polishing tool, and in other embodiments, the polishing angle of the polishing tool may also be adjusted to adapt to different tilt angles of the stacked package chips.
In this embodiment, the plurality of dies 120 are stacked together in different tilted directions, and it is necessary to adjust the placement position of the stacked packaged chip 100 and to grind the metal wires 140 in different tilted states.
Fig. 5 is a schematic diagram illustrating a structure of placing stacked package chips inclined with respect to a horizontal plane at a first inclination angle, and as shown in fig. 5, in this embodiment, the stacked package chips 100 are placed inclined with respect to the horizontal plane at the first inclination angle by controlling a height difference between two sides of the lead frame 110. When the stacked package chip 100 is tilted at a first tilt angle, the lead frame 110 is also tilted at a first tilt angle, and a height difference between a first side and a second side of the lead frame 110 is H1Wherein the second side is higher than the first side.
Specifically, in the present embodiment, the width of the lead frame 110 is a, and the first height difference between the two sides of the lead frame 110 is H1Comprises the following steps:
H1＝A*Sinα
as shown in fig. 5, the height difference between the first side and the second side of the lead frame 110 is H1And the second side is higher than the first side, the stacked package chip 100 is tilted at a first tilt angle with respect to the horizontal plane, in this state, the polishing tool 160 polishes along a direction perpendicular to the horizontal plane, and the polishing of the die 1201, the die 1202, the die 1203, and the die 1204 can be achieved by moving the polishing tool 160 in the horizontal direction.
FIG. 6 is a schematic view showing a structure in which the stacked package chips are placed at a second inclination angle with respect to the horizontal plane, the second inclination angle being different from the first inclination angle in the inclination direction, and the height difference between the first side and the second side of the lead frame 100 is H when the stacked package chips 100 are placed at the second inclination angle, as shown in FIG. 62Wherein the first side is higher than the second side.
Wherein a second height difference between both sides of the lead frame 110 is H2Comprises the following steps:
H2＝A*Sinθ
as shown in fig. 6, the height difference between the first side and the second side of the lead frame 110 is H2And when the first side is higher than the second side, the stacked package chip 100 is placed at a second inclination angle with respect to the horizontal plane, in this state, the shielding of the upper die 1201, the die 1202, the die 1203, and the die 1204 is released, the grinding tool 160 grinds along a direction perpendicular to the horizontal plane, and the grinding of the die 1205, the die 1206, the die 1207, and the die 1208 can be realized only by moving the grinding tool 160 in the horizontal direction.
In this embodiment, the dies 120 are stacked together at different tilt angles, and the first direction tilt angle a and the second direction tilt angle θ need to be calculated respectively. In other embodiments, multiple dies 120 are stacked together with a tilt angle in the same direction, only one tilt angle in the same direction needs to be calculated.
In more complex embodiments, the dies of the stacked packaged chips are also stacked together in more than two different tilted orientations.
In the embodiments described above, the size parameters of the stacked package chips are obtained by using an acoustic scanning microscope SAM and X-rays, but may be implemented by any other means capable of obtaining the size parameters of the stacked package chips, and the embodiments are only examples.
The dimensional parameters of the stacked packaged chips include, for example, the pitch h between adjacent dies, the step width l, and the width a of the lead frame 110.
Fig. 7(a) and 7(b) show front and back side scan images of one stacked package chip obtained by an acoustic scanning microscope SAM and X-rays, respectively, and as shown in fig. 7(a) and 7(b), the specific structure of the stacked package chip can be clearly observed by the image of the stacked package chip obtained by the acoustic scanning microscope SAM, and the specific size of each component in the stacked package chip can be obtained by X-rays.
Fig. 8 shows an unsealing diagram of a stacked package chip according to a second embodiment of the present invention. As shown in fig. 8, the stacked packaged chip 200 is more complex and includes a lead frame 210, a plurality of dies 220 stacked on the lead frame 210, and an encapsulant 230 covering the lead frame 210 and the plurality of dies 220. Wherein, the plurality of dies 120 are stacked in a step shape in two or more different inclined directions, a step surface 250 is formed at the edge, and the metal wire 240 is connected to the step surface 250.
In this embodiment, the shielding phenomenon of the die 220 is more serious, and the stacked package chip 200 is unpacked by the method of the first embodiment and is placed in a tilted manner for multiple times to realize the cutting of the complex metal wires 240. A schematic diagram of the relative tilting of the polishing tool 260 is shown in fig. 7, which may be implemented for the stacked packaged chips 200.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (11)
1. A method for unsealing a stacked packaged chip, the stacked packaged chip comprising a lead frame, a plurality of dies stacked on the lead frame, and an encapsulant covering the lead frame and the plurality of dies, the plurality of dies being stacked in a step shape, a step surface connected to a metal wire being formed at an edge of the plurality of dies,
the unsealing method includes:
acquiring a tilt angle according to the positions of the plurality of dies;
and adjusting a relative angle between the grinding direction and the stacked packaging chips according to the inclination angle, removing at least part of the packaging material and cutting the metal wire.
2. The method of unsealing a stacked package chip according to claim 1, wherein the inclination angle is obtained by measurement.
3. The method of unsealing a stacked package chip according to claim 1, wherein the inclination angle is calculated.
4. The method of unsealing stacked packaged chips according to claim 3, wherein the pitches between adjacent dies of the stacked packaged chips are the same, and the widths of the step faces are the same.
5. The method of unsealing a stacked package chip according to claim 4, wherein the inclination angle is calculated from a pitch between adjacent dies and a width of the step face.
6. The method of unsealing a stacked package chip according to claim 5, wherein the inclination angle is calculated by:
where, α is an inclination angle, h is a distance between adjacent dies, and l is a width of the step surface.
7. The method of unsealing a stack package chip according to claim 1, wherein the stack package chip is placed obliquely with respect to a horizontal plane at the inclination angle.
8. The method of unsealing a stacked packaged chip according to claim 7, wherein the stacked packaged chip is placed obliquely with respect to a horizontal plane by controlling a height difference of both sides of the lead frame.
9. The method of unsealing a stacked packaged chip according to claim 8, wherein the difference in height between both sides of the lead frame is H:
H＝A*Sinα
where α is the tilt angle and a is the width of the lead frame.
10. The method of unsealing a stacked packaged chip according to claim 1, wherein a plurality of dies are stacked together at the same inclination angle.
11. The method of unsealing a stacked packaged chip according to claim 1, wherein a plurality of dies are stacked together at different inclination angles.
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| CN202111042727.2A CN113851397A (en) | 2021-09-07 | 2021-09-07 | A kind of unsealing method of stacked package chip |
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| CN202111042727.2A CN113851397A (en) | 2021-09-07 | 2021-09-07 | A kind of unsealing method of stacked package chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI854377B (en) * | 2022-11-24 | 2024-09-01 | 新唐科技股份有限公司 | Separating method and failure analysis method of multi-chip package |
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| CN111745531A (en) * | 2020-07-01 | 2020-10-09 | 长江存储科技有限责任公司 | Curved surface grinding device and chip extraction method |
| CN113097086A (en) * | 2021-03-25 | 2021-07-09 | 长江存储科技有限责任公司 | Preparation method of to-be-failed analysis sample and to-be-failed analysis sample |
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| US20100133677A1 (en) * | 2008-11-28 | 2010-06-03 | Shinko Electric Industries Co., Ltd. | Semiconductor chip stacked body and method of manufacturing the same |
| CN108933109A (en) * | 2017-05-27 | 2018-12-04 | 晟碟信息科技（上海）有限公司 | The semiconductor devices of angled naked core |
| CN111745531A (en) * | 2020-07-01 | 2020-10-09 | 长江存储科技有限责任公司 | Curved surface grinding device and chip extraction method |
| CN113097086A (en) * | 2021-03-25 | 2021-07-09 | 长江存储科技有限责任公司 | Preparation method of to-be-failed analysis sample and to-be-failed analysis sample |
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| TWI854377B (en) * | 2022-11-24 | 2024-09-01 | 新唐科技股份有限公司 | Separating method and failure analysis method of multi-chip package |
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