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CN117276099B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN117276099B
CN117276099B CN202311288419.7A CN202311288419A CN117276099B CN 117276099 B CN117276099 B CN 117276099B CN 202311288419 A CN202311288419 A CN 202311288419A CN 117276099 B CN117276099 B CN 117276099B
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wafer
groove
dielectric layer
insulating dielectric
semiconductor device
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CN117276099A (en
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王森
田秀芳
奉伟
徐振
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Wuhan Xinxin Integrated Circuit Co ltd
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Wuhan Xinxin Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02016—Backside treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device and a method for manufacturing the same, wherein the method for manufacturing the semiconductor device comprises providing an upper wafer and a lower wafer; forming a groove in the edge area of the upper wafer, forming a first insulating medium layer to cover the upper wafer, sealing the groove by the first insulating medium layer to enable the groove to form a hollow structure, bonding one surface of the first insulating medium layer away from the upper wafer with the lower wafer, and thinning one surface of the upper wafer away from the lower wafer. The technical scheme of the invention can avoid the problem of edge breakage in the thinning process from affecting the devices in the wafer.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device and a method of fabricating the same.
Background
In order to meet the requirements of advanced packaging of ICs, the thickness of each layer of chips in the stack inevitably needs to be thinned in the trend of not changing or even decreasing the overall thickness of the package. In the traditional wafer thinning process, a diamond grinding wheel is used for quickly and coarsely grinding a wafer to a certain thickness, and then fine grinding is carried out in a mode of chemical mechanical grinding or wet etching.
However, in the wafer thinning process, edge chipping often occurs at the edge of the bonding interface, which leads to exposure of devices in the edge chipping region of the thinned wafer, and further results in problems such as bubbles in the photoresist, arc discharge during dry etching, and contamination of exposed devices by particles generated by wet etching.
Therefore, how to avoid the problem of edge breakage during the thinning process from affecting the internal devices of the wafer is a need to be solved.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which can avoid the problem of edge breakage in the thinning process from affecting the devices in a wafer.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing an upper wafer and a lower wafer;
forming a groove in the edge area of the upper wafer;
forming a first insulating medium layer to cover the upper wafer, wherein the first insulating medium layer seals the groove so that the groove forms a hollow structure;
bonding one surface of the first insulating medium layer far away from the upper wafer with the lower wafer;
and thinning one surface of the upper layer wafer far away from the lower layer wafer.
Optionally, the first insulating medium layer is formed inside the groove and does not fill the groove, so that the groove forms the hollow structure.
Optionally, before forming the first insulating dielectric layer to cover the upper wafer, the method for manufacturing the semiconductor device further includes:
And performing a first trimming process to remove a part of edge area of the upper wafer located at the periphery of the groove and/or a part of edge area of the lower wafer bonded with the upper wafer located at the periphery of the corresponding position of the groove.
Optionally, a laser process or an etching process is used to form the grooves in the edge region of the upper wafer.
Optionally, before bonding the side of the first insulating medium layer away from the upper wafer with the lower wafer, the method for manufacturing the semiconductor device further includes:
flattening one surface of the first insulating medium layer far away from the upper wafer;
Or forming a metal layer in the first insulating medium layer;
and flattening one surface of the first insulating medium layer and the metal layer, which is far away from the upper wafer.
Optionally, the upper wafer includes a substrate and a second insulating dielectric layer formed on the substrate, the groove is recessed from the second insulating dielectric layer and penetrates through the second insulating dielectric layer to further extend into the substrate, the first insulating dielectric layer covers the second insulating dielectric layer, and the step of thinning the side of the upper wafer away from the lower wafer includes:
and thinning one surface of the substrate far away from the second insulating medium layer.
Optionally, the depth to which the groove extends into the substrate is greater than or equal to the thickness of the substrate remaining after thinning a side of the substrate away from the second insulating dielectric layer.
Optionally, after thinning the side of the upper layer wafer away from the lower layer wafer, the method for manufacturing the semiconductor device further includes:
and performing a second trimming process to remove edge regions of the upper wafer and the lower wafer, which are positioned at the periphery of the groove, which is close to the center of the upper wafer.
Optionally, the groove is a closed or intermittent annular groove.
The invention also provides a semiconductor device manufactured by the manufacturing method of the semiconductor device.
The present invention also provides a semiconductor device characterized by comprising:
an upper wafer;
the groove is formed in the edge area of the upper layer wafer;
And the first insulating medium layer covers the upper wafer, and seals the groove so that the groove forms a hollow structure.
Optionally, the first insulating medium layer is formed inside the groove and does not fill the groove, so that the groove forms the hollow structure.
Optionally, the upper wafer includes a substrate and a second insulating dielectric layer formed on the substrate, the groove is recessed from the second insulating dielectric layer and penetrates through the second insulating dielectric layer to further extend into the substrate, and the first insulating dielectric layer covers the second insulating dielectric layer.
Optionally, the groove is a closed or intermittent annular groove.
Optionally, the semiconductor device further includes:
And the lower layer wafer is bonded with one surface of the first insulating medium layer, which is far away from the upper layer wafer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. The manufacturing method of the semiconductor device comprises the steps of providing an upper layer wafer and a lower layer wafer, forming a groove in the edge area of the upper layer wafer, forming a first insulating medium layer to cover the upper layer wafer, sealing the groove by the first insulating medium layer to enable the groove to form a hollow structure, bonding one surface of the first insulating medium layer, which is far away from the upper layer wafer, with the lower layer wafer, thinning one surface of the upper layer wafer, which is far away from the lower layer wafer, and enabling the groove arranged in the hollow structure to avoid the problem of edge breakage in the thinning process from affecting the device inside the wafer.
2. The semiconductor device is manufactured by adopting the manufacturing method of the semiconductor device, so that the problem of edge breakage in the thinning process can be avoided from affecting the devices in the wafer.
3. The semiconductor device comprises an upper layer wafer, a groove formed in the edge area of the upper layer wafer, and a first insulating medium layer covering the upper layer wafer and sealing the groove so that the groove forms a hollow structure, and the groove arranged in the hollow structure enables the problem of edge breakage in the thinning process to be prevented from affecting the internal device of the wafer.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 2a to 2i are schematic views of a device in the method of manufacturing a semiconductor device shown in fig. 1;
fig. 3 is a schematic top view of the semiconductor device shown in fig. 2 d.
The reference numerals of fig. 1 to 3 are as follows:
11-first substrate, 12-second insulating dielectric layer, 121-first metal interconnection structure, 13-groove, 14-first insulating dielectric layer, 15-first metal layer, 21-second substrate, 22-third insulating dielectric layer, 221-second metal interconnection structure, 231-fourth insulating dielectric layer and 232-second metal layer.
Detailed Description
In order to make the objects, advantages and features of the present invention more apparent, the following more particular description of the semiconductor device and method of fabricating the same is provided. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, referring to fig. 1, as can be seen from fig. 1, the method for manufacturing a semiconductor device includes:
step S1, providing an upper layer wafer and a lower layer wafer;
S2, forming a groove in the edge area of the upper wafer;
s3, forming a first insulating medium layer to cover the upper wafer, and sealing the groove by the first insulating medium layer so that the groove forms a hollow structure;
Step S4, bonding one surface of the first insulating medium layer far away from the upper layer wafer with the lower layer wafer;
And S5, thinning one surface of the upper layer wafer far away from the lower layer wafer.
The method for manufacturing the semiconductor device according to the present embodiment will be described in detail with reference to fig. 2a to 2i and fig. 3, and fig. 2a to 2i are schematic longitudinal sectional views.
According to step S1, an upper wafer and a lower wafer are provided.
The upper layer wafer may be a device wafer or a carrier wafer, and the lower layer wafer may be a device wafer or a carrier wafer.
The device wafer may be a pixel wafer containing a pixel array of an image sensor, or a MEMS wafer containing a MEMS microstructure of a MEMS device, or may be a MOSFET wafer containing a power device, or an IGBT wafer, or a passive device wafer, etc., where the type of the device wafer depends on the function of the device to be finally fabricated.
The carrier wafer may contain no functional structures, or the carrier wafer may contain functional structures that are located inside the carrier wafer rather than on the surface of the carrier wafer.
As shown in fig. 2a, the upper wafer includes a substrate (for distinguishing from a substrate in a lower wafer, the substrate in the upper wafer is defined as a first substrate 11, the substrate in the lower wafer is defined as a second substrate 21) and a second insulating dielectric layer 12 formed on the first substrate 11, a first metal interconnection structure 121 and the like may be formed in the second insulating dielectric layer 12, and as shown in fig. 2b, the lower wafer includes a second substrate 21 and a third insulating dielectric layer 22 formed on the second substrate 21, and a second metal interconnection structure 221 and the like may be formed in the third insulating dielectric layer 22.
According to step S2, as shown in fig. 2d, a groove 13 is formed in the edge region of the upper wafer.
The groove 13 may be formed in the edge area of the upper wafer by a laser process or an etching process, and the depth and width of the groove 13 may be adjusted by adjusting parameters of the laser process or the etching process.
The groove 13 is recessed from the second insulating dielectric layer 12 and penetrates through the second insulating dielectric layer 12 to further extend into the first substrate 11, and preferably, the depth of the groove 13 extending into the first substrate 11 is greater than or equal to the thickness of the first substrate 11 remaining after the subsequent thinning of the first substrate 11 away from the second insulating dielectric layer 12.
For example, when the thickness of the first substrate 11 remaining after the subsequent thinning of the first substrate 11 away from the side of the second insulating medium layer 12 is 14 micrometers, the depth to which the groove 13 extends into the first substrate 11 may be greater than or equal to 14 micrometers.
Preferably, as shown in fig. 3, the groove 13 is a closed annular groove, so that the groove 13 can completely block cracks and broken edges at the periphery of the groove 13. In other embodiments, the groove 13 may be a discontinuous annular groove. Note that fig. 3 is a schematic top view of the semiconductor device shown in fig. 2d, and for more clarity, the position of the recess 13 is shown, and the first substrate 11 at the bottom of the recess 13 is not shown in fig. 3.
Preferably, before the first insulating dielectric layer 14 is subsequently formed to cover the upper wafer, the method for manufacturing a semiconductor device may further include performing a first trimming process to remove a portion of the upper wafer located at the periphery of the recess 13 and/or a portion of the lower wafer located at the periphery of the position corresponding to the recess 13 after being subsequently bonded to the upper wafer.
Because the edges of the surfaces to be bonded of the upper layer wafer and the lower layer wafer are uneven when the upper layer wafer and the lower layer wafer are manufactured, the uneven edges of the surfaces to be bonded of the upper layer wafer and/or the lower layer wafer can be removed by executing the first trimming process before the upper layer wafer and the lower layer wafer are bonded, so that the surfaces to be bonded of the upper layer wafer and/or the lower layer wafer after the first trimming process are even, and the bonding force between the upper layer wafer and the lower layer wafer after the subsequent bonding is enhanced.
Wherein, when the first trimming process is performed, the trimming may be performed from a partial edge region of the second insulating dielectric layer 12 at the periphery of the recess 13 to a partial edge region of the first substrate 11 having a partial thickness or a full thickness, and/or from a partial edge region of the third insulating dielectric layer 22 at the periphery of the corresponding position of the recess 13 to a partial edge region of the second substrate 21 having a partial thickness or a full thickness. The embodiment shown in fig. 2c is that the partial edge area of the first substrate 11, which is trimmed from the partial edge area of the second insulating dielectric layer 12 at the periphery of the recess 13 to a partial thickness, is left unremoved.
In addition, in an embodiment, after the first trimming process is performed, an insulating medium layer may be formed on the bonding surface of the upper wafer and/or the lower wafer, so that the bonding surface of the upper wafer and/or the lower wafer is smoother.
In addition, the edge areas of the upper layer wafer and the lower layer wafer are non-chip areas respectively positioned at the edges of the upper layer wafer and the lower layer wafer.
According to step S3, as shown in fig. 2e, a first insulating dielectric layer 14 is formed to cover the upper wafer, and the first insulating dielectric layer 14 seals the recess 13, so that the recess 13 forms a hollow structure. Wherein the first insulating dielectric layer 14 is covered on the second insulating dielectric layer 12.
The first insulating dielectric layer 14 may be formed using a chemical vapor deposition process.
Since the width of the groove 13 is small, the groove 13 can be sealed in advance, the first insulating dielectric layer 14 is formed only on the inner wall of the groove 13 in a small amount, or the first insulating dielectric layer 14 is not formed in the groove 13 at all, i.e. the first insulating dielectric layer 14 does not fill the groove 13, so that the groove 13 forms a hollow structure.
In addition, the method for manufacturing the semiconductor device can further comprise flattening the side of the first insulating dielectric layer 14 away from the upper wafer before bonding the side of the first insulating dielectric layer 14 away from the upper wafer with the lower wafer. Or the method for manufacturing a semiconductor device may further include forming a first metal layer 15 in the first insulating dielectric layer 14, as shown in fig. 2f, where the first metal layer 15 may be electrically connected to the first metal interconnection structure 121, and planarizing a surface of the first insulating dielectric layer 14 and the first metal layer 15 away from the upper wafer.
And, before bonding the surface of the first insulating dielectric layer 14 away from the upper wafer with the lower wafer, the method for manufacturing the semiconductor device may further include forming a fourth insulating dielectric layer 231 on the lower wafer, and planarizing the surface of the fourth insulating dielectric layer 231 away from the lower wafer. Or the method for manufacturing a semiconductor device may further include forming a fourth insulating dielectric layer 231 on the lower wafer, forming a second metal layer 232 in the fourth insulating dielectric layer 231, wherein the second metal layer 232 may be electrically connected to the second metal interconnection structure 221, and planarizing a surface of the fourth insulating dielectric layer 231 and the second metal layer 232 away from the lower wafer, as shown in fig. 2 b.
According to step S4, as shown in fig. 2g, a surface of the first insulating dielectric layer 14 away from the upper wafer is bonded to the lower wafer.
If the first metal layer 15 is not formed in the first insulating dielectric layer 14 and the second metal layer 232 is not formed in the fourth insulating dielectric layer 231, the bonding between the upper wafer and the lower wafer is achieved by fusion bonding between the surface of the first insulating dielectric layer 14 away from the upper wafer and the surface of the fourth insulating dielectric layer 231 away from the lower wafer, and if the first metal layer 15 is formed in the first insulating dielectric layer 14 and the second metal layer 232 is formed in the fourth insulating dielectric layer 231, the bonding between the upper wafer and the lower wafer is achieved by fusion bonding between the surface of the first insulating dielectric layer 14 away from the upper wafer and the surface of the fourth insulating dielectric layer 231 away from the lower wafer, as shown in fig. 2 g.
According to step S5, as shown in fig. 2h, a surface of the upper wafer away from the lower wafer is thinned.
The method comprises the step of thinning the side of the first substrate 11 away from the second insulating medium layer 12. The first substrate 11 may be first quickly rough-ground to a certain thickness by using a diamond-impregnated wheel, and then the first substrate 11 may be finely ground by using a chemical mechanical grinding or wet etching method.
Since the edge of the upper wafer is easy to generate cracks and broken edges from the bonding interface in the process of thinning the surface of the upper wafer away from the lower wafer, the hollow part in the groove 13 can prevent the cracks and broken edges from expanding into the area surrounded by the groove 13 by forming the groove 13 with a hollow structure in the edge area of the upper wafer, so that the cracks and broken edges only occur in the peripheral edge area of the groove 13 (such as the crack A1 in FIG. 2 h), and the device exposure in the area surrounded by the groove 13 can be avoided to influence the internal devices of the wafer. And, when the depth of the groove 13 extending into the first substrate 11 is greater than or equal to the thickness of the first substrate 11 remaining after thinning one surface of the first substrate 11 away from the second insulating dielectric layer 12, the thinned one surface of the first substrate 11 away from the second insulating dielectric layer 12 can expose the groove 13, that is, the first substrate 11 in the thickness range where the groove 13 is not formed is thinned and removed, so that it can be further ensured that no crack and edge breakage occur in the area surrounded by the thinned groove 13.
In addition, after thinning the side of the upper wafer away from the lower wafer, the method for manufacturing a semiconductor device may further include performing a second trimming process to remove the peripheral edge regions of the upper and lower wafers located at the periphery of the recess 13 near the center of the upper wafer, as shown in fig. 2i, so as to remove the edge regions of the upper and lower wafers having more defects.
In the second trimming process, the edge region of the upper wafer near the periphery of the center side of the upper wafer may be trimmed from the edge region of the recess 13 to the edge region of the lower wafer with a partial thickness or a full thickness. The embodiment shown in fig. 2i is that the edge area of the second substrate 21 with a partial thickness is trimmed from the edge area of the upper wafer near the periphery of the center side of the upper wafer to the edge area of the lower wafer, i.e. the edge area of the second substrate 21 with a partial thickness is left unremoved.
In summary, the present invention provides a method for manufacturing a semiconductor device, which includes providing an upper wafer and a lower wafer, forming a groove in an edge region of the upper wafer, forming a first insulating dielectric layer covering the upper wafer, sealing the groove by the first insulating dielectric layer to form a hollow structure, bonding a surface of the first insulating dielectric layer away from the upper wafer with the lower wafer, and thinning a surface of the upper wafer away from the lower wafer. In the manufacturing method of the semiconductor device, the arrangement of the grooves with the hollow structure can avoid the problem of edge breakage in the thinning process from affecting the devices in the wafer.
An embodiment of the invention provides a semiconductor device manufactured by the manufacturing method of the semiconductor device.
As shown in fig. 2i, the semiconductor device includes an upper wafer and a lower wafer, the upper wafer is covered with a first insulating dielectric layer 14, and a surface of the first insulating dielectric layer 14 away from the upper wafer is bonded to the lower wafer.
The upper wafer comprises a first substrate 11 and a second insulating dielectric layer 12 formed on the first substrate 11, a first metal interconnection structure 121 and the like can be formed in the second insulating dielectric layer 12, the first insulating dielectric layer 14 covers the second insulating dielectric layer 12, the lower wafer comprises a second substrate 21 and a third insulating dielectric layer 22 formed on the second substrate 21, and a second metal interconnection structure 221 and the like can be formed in the third insulating dielectric layer 22.
As shown in fig. 2i, a first metal layer 15 may be further formed in the first insulating dielectric layer 14, and the first metal layer 15 may be electrically connected to the first metal interconnection structure 121. In other embodiments, the first metal layer 15 may not be formed in the first insulating dielectric layer 14.
As shown in fig. 2i, the semiconductor device may further include a fourth insulating dielectric layer 231 and a second metal layer 232, the fourth insulating dielectric layer 231 is formed on the lower wafer, the fourth insulating dielectric layer 231 covers the third insulating dielectric layer 22, the second metal layer 232 is formed in the fourth insulating dielectric layer 231, and the second metal layer 232 may be electrically connected to the second metal interconnection structure 221. In other embodiments, the second metal layer 232 may not be formed in the fourth insulating medium layer 231.
If the first metal layer 15 is not formed in the first insulating dielectric layer 14 and the second metal layer 232 is not formed in the fourth insulating dielectric layer 231, the bonding between the upper wafer and the lower wafer is achieved by fusion bonding between the surface of the first insulating dielectric layer 14 away from the upper wafer and the surface of the fourth insulating dielectric layer 231 away from the lower wafer, and if the first metal layer 15 is formed in the first insulating dielectric layer 14 and the second metal layer 232 is formed in the fourth insulating dielectric layer 231, the bonding between the upper wafer and the lower wafer is achieved by fusion bonding between the surface of the first insulating dielectric layer 14 away from the upper wafer and the surface of the fourth insulating dielectric layer 231 away from the lower wafer, as shown in fig. 2 i.
The upper layer wafer may be a device wafer or a carrier wafer, and the lower layer wafer may be a device wafer or a carrier wafer.
The device wafer may be a pixel wafer containing a pixel array of an image sensor, or a MEMS wafer containing a MEMS microstructure of a MEMS device, or may be a MOSFET wafer containing a power device, or an IGBT wafer, or a passive device wafer, etc., where the type of the device wafer depends on the function of the device to be finally fabricated.
The carrier wafer may contain no functional structures, or the carrier wafer may contain functional structures that are located inside the carrier wafer rather than on the surface of the carrier wafer.
The semiconductor device is manufactured by adopting the manufacturing method of the semiconductor device, so that the problem of edge breakage in the thinning process can be avoided from affecting the devices in the wafer.
The embodiment of the invention provides a semiconductor device, which comprises an upper layer wafer, a groove formed in the edge area of the upper layer wafer, and a first insulating medium layer covering the upper layer wafer, wherein the first insulating medium layer seals the groove so that the groove forms a hollow structure.
The semiconductor device provided in this embodiment will be described in detail with reference to fig. 2e to 2 g.
The upper wafer includes a substrate (for distinguishing from a substrate in a lower wafer, the substrate in the upper wafer is defined as a first substrate 11, and the substrate in the lower wafer is defined as a second substrate 21) and a second insulating dielectric layer 12 formed on the first substrate 11, where the second insulating dielectric layer 12 may have a first metal interconnection structure 121 formed therein.
The groove 13 is formed in an edge region of the upper wafer.
The recess 13 is recessed from the second insulating dielectric layer 12 and extends through the second insulating dielectric layer 12 to extend further into the first substrate 11. Preferably, the depth to which the recess 13 extends into the first substrate 11 is greater than or equal to the thickness of the first substrate 11 remaining after a subsequent process of thinning a side of the first substrate 11 away from the second insulating dielectric layer 12 is performed.
For example, when the thickness of the first substrate 11 remaining after the subsequent thinning of the first substrate 11 away from the side of the second insulating medium layer 12 is 14 micrometers, the depth to which the groove 13 extends into the first substrate 11 may be greater than or equal to 14 micrometers.
Preferably, the groove 13 is a closed annular groove, so that the groove 13 can completely block cracks and broken edges generated in a subsequent process of thinning the first substrate 11 from the periphery of the groove 13. In other embodiments, the groove 13 may be a discontinuous annular groove.
The first insulating medium layer 14 covers the upper wafer, and the first insulating medium layer 14 seals the groove 13, so that the groove 13 forms a hollow structure. Wherein the first dielectric layer 14 covers the second dielectric layer 12.
The first insulating dielectric layer 14 is formed only on the inner wall of the recess 13 in a small amount, or the first insulating dielectric layer 14 is not formed in the recess 13 at all, i.e., the first insulating dielectric layer 14 does not fill the recess 13, so that the recess 13 forms a hollow structure.
As shown in fig. 2f, the semiconductor device may further include a first metal layer 15 formed in the first insulating dielectric layer 14, and the first metal layer 15 may be electrically connected to the first metal interconnection structure 121. In the embodiment shown in fig. 2e, the first metal layer 15 may not be formed in the first insulating dielectric layer 14.
As shown in fig. 2g, the semiconductor device may further include a lower wafer bonded to a side of the first insulating dielectric layer 14 remote from the upper wafer.
The upper layer wafer may be a device wafer or a carrier wafer, and the lower layer wafer may be a device wafer or a carrier wafer.
The device wafer may be a pixel wafer containing a pixel array of an image sensor, or a MEMS wafer containing a MEMS microstructure of a MEMS device, or may be a MOSFET wafer containing a power device, or an IGBT wafer, or a passive device wafer, etc., where the type of the device wafer depends on the function of the device to be finally fabricated.
The carrier wafer may contain no functional structures, or the carrier wafer may contain functional structures that are located inside the carrier wafer rather than on the surface of the carrier wafer.
The lower wafer includes a second substrate 21 and a third insulating dielectric layer 22 formed on the second substrate 21, and a second metal interconnection structure 221 and the like may be formed in the third insulating dielectric layer 22.
As shown in fig. 2g, the semiconductor device may further include a fourth insulating dielectric layer 231 and a second metal layer 232, the fourth insulating dielectric layer 231 is formed on the lower wafer, the fourth insulating dielectric layer 231 covers the third insulating dielectric layer 22, the second metal layer 232 is formed in the fourth insulating dielectric layer 231, and the second metal layer 232 may be electrically connected to the second metal interconnection structure 221. In other embodiments, the second metal layer 232 may not be formed in the fourth insulating medium layer 231.
If the first metal layer 15 is not formed in the first insulating dielectric layer 14 and the second metal layer 232 is not formed in the fourth insulating dielectric layer 231, the bonding between the upper wafer and the lower wafer is achieved by fusion bonding between the surface of the first insulating dielectric layer 14 away from the upper wafer and the surface of the fourth insulating dielectric layer 231 away from the lower wafer, and if the first metal layer 15 is formed in the first insulating dielectric layer 14 and the second metal layer 232 is formed in the fourth insulating dielectric layer 231, the bonding between the upper wafer and the lower wafer is achieved by fusion bonding between the surface of the first insulating dielectric layer 14 away from the upper wafer and the surface of the fourth insulating dielectric layer 231 away from the lower wafer, as shown in fig. 2 g.
Preferably, a part of the edge area of the upper wafer located at the periphery of the groove 13 and/or a part of the edge area of the lower wafer located at the periphery of the corresponding position of the groove 13 may be trimmed away, so that the edge area of the upper wafer located at the periphery of the groove 13 and/or the edge area of the lower wafer located at the periphery of the corresponding position of the groove 13 is shrunk. In the embodiment shown in fig. 2e to 2g, the second insulating dielectric layer 12 and the edge region of the first substrate 11 near the second insulating dielectric layer 12, which is located at the periphery of the recess 13, are retracted relative to the first substrate 11 far from the second insulating dielectric layer 12.
Because the edges of the surfaces to be bonded of the upper layer wafer and the lower layer wafer are uneven when the upper layer wafer and the lower layer wafer are manufactured, the areas of the uneven edges of the surfaces to be bonded of the upper layer wafer and/or the lower layer wafer are removed before the upper layer wafer and the lower layer wafer are bonded, so that the surfaces to be bonded of the upper layer wafer and/or the lower layer wafer are level, and the bonding force between the upper layer wafer and the lower layer wafer after bonding is enhanced.
The edge areas of the upper layer wafer and the lower layer wafer are non-chip areas respectively positioned at the edges of the upper layer wafer and the lower layer wafer.
Since the edge of the upper wafer is easy to generate cracks and broken edges from the bonding interface in the process of thinning the surface of the upper wafer away from the lower wafer, in the invention, the cracks and broken edges generated in the thinning process only occur in the edge area of the periphery of the groove 13 due to the groove 13 of the hollow structure formed in the edge area of the upper wafer, and the hollow part in the groove 13 can prevent the cracks and broken edges from expanding into the area surrounded by the groove 13, thereby avoiding the exposure of devices in the area surrounded by the groove 13 to affect the internal devices of the wafer. And, when the depth of the groove 13 extending into the first substrate 11 is greater than or equal to the thickness of the first substrate 11 remaining after thinning one surface of the first substrate 11 away from the second insulating dielectric layer 12, the thinned one surface of the first substrate 11 away from the second insulating dielectric layer 12 can expose the groove 13, that is, the first substrate 11 in the thickness range where the groove 13 is not formed is thinned and removed, so that it can be further ensured that no crack and edge breakage occur in the area surrounded by the thinned groove 13.
In summary, the present invention provides a semiconductor device, which includes an upper wafer, a recess formed in an edge region of the upper wafer, and a first insulating dielectric layer covering the upper wafer, wherein the first insulating dielectric layer seals the recess to form a hollow structure. In the semiconductor device, the arrangement of the grooves of the hollow structure can prevent the edge breakage problem in the thinning process from affecting the internal devices of the wafer.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (14)

1.一种半导体器件的制造方法，其特征在于，包括：1. A method for manufacturing a semiconductor device, comprising: 提供上层晶圆和下层晶圆；Providing an upper wafer and a lower wafer; 形成凹槽于所述上层晶圆的边缘区域，执行第一次修剪工艺，以去除所述上层晶圆的位于所述凹槽外围的部分边缘区域；Forming a groove in the edge area of the upper wafer, and performing a first trimming process to remove a portion of the edge area of the upper wafer located outside the groove; 形成第一绝缘介质层覆盖于所述上层晶圆上，且所述第一绝缘介质层将所述凹槽封口，以使所述凹槽形成中空结构；Forming a first insulating medium layer to cover the upper wafer, and the first insulating medium layer seals the groove so that the groove forms a hollow structure; 将所述第一绝缘介质层远离所述上层晶圆的一面与所述下层晶圆熔融键合或混合键合；Melt-bonding or hybrid-bonding a side of the first insulating dielectric layer away from the upper wafer to the lower wafer; 减薄所述上层晶圆远离所述下层晶圆的一面，所述凹槽用于阻挡减薄过程中从所述第一绝缘介质层与所述下层晶圆的键合界面处产生的裂纹和崩边扩展到所述凹槽所环绕的区域内。The side of the upper wafer away from the lower wafer is thinned, and the groove is used to prevent cracks and chipping generated from the bonding interface between the first insulating medium layer and the lower wafer during the thinning process from extending into the area surrounded by the groove. 2.如权利要求1所述的半导体器件的制造方法，其特征在于，所述第一绝缘介质层形成于所述凹槽的内部且未填满所述凹槽，以使所述凹槽形成所述中空结构。2 . The method for manufacturing a semiconductor device according to claim 1 , wherein the first insulating dielectric layer is formed inside the groove and does not fill up the groove, so that the groove forms the hollow structure. 3.如权利要求1所述的半导体器件的制造方法，其特征在于，在形成所述第一绝缘介质层覆盖于所述上层晶圆上之前，所述半导体器件的制造方法还包括：3. The method for manufacturing a semiconductor device according to claim 1, characterized in that before forming the first insulating dielectric layer to cover the upper wafer, the method for manufacturing a semiconductor device further comprises: 执行第一次修剪工艺，以去除与所述上层晶圆键合后的所述下层晶圆的位于所述凹槽对应位置外围的部分边缘区域。A first trimming process is performed to remove a portion of the edge region of the lower wafer bonded to the upper wafer, which is located at the periphery of the position corresponding to the groove. 4.如权利要求1所述的半导体器件的制造方法，其特征在于，采用激光工艺或刻蚀工艺形成所述凹槽于所述上层晶圆的边缘区域。4 . The method for manufacturing a semiconductor device according to claim 1 , wherein the groove is formed in an edge region of the upper wafer by using a laser process or an etching process. 5.如权利要求1所述的半导体器件的制造方法，其特征在于，在将所述第一绝缘介质层远离所述上层晶圆的一面与所述下层晶圆键合之前，所述半导体器件的制造方法还包括：5. The method for manufacturing a semiconductor device according to claim 1, characterized in that before bonding the side of the first insulating dielectric layer away from the upper wafer to the lower wafer, the method for manufacturing a semiconductor device further comprises: 平坦化处理所述第一绝缘介质层远离所述上层晶圆的一面；Planarizing a side of the first insulating dielectric layer away from the upper wafer; 或者，形成金属层于所述第一绝缘介质层中；Alternatively, forming a metal layer in the first insulating dielectric layer; 平坦化处理所述第一绝缘介质层和所述金属层远离所述上层晶圆的一面。The first insulating dielectric layer and the metal layer are planarized on a side away from the upper wafer. 6.如权利要求1所述的半导体器件的制造方法，其特征在于，所述上层晶圆包括衬底和形成于所述衬底上的第二绝缘介质层，所述凹槽自所述第二绝缘介质层凹设并贯穿所述第二绝缘介质层以进一步延伸进入所述衬底中，所述第一绝缘介质层覆盖所述第二绝缘介质层；减薄所述上层晶圆远离所述下层晶圆的一面的步骤包括：6. The method for manufacturing a semiconductor device according to claim 1, wherein the upper wafer comprises a substrate and a second insulating dielectric layer formed on the substrate, the groove is recessed from the second insulating dielectric layer and penetrates the second insulating dielectric layer to further extend into the substrate, and the first insulating dielectric layer covers the second insulating dielectric layer; the step of thinning a side of the upper wafer away from the lower wafer comprises: 减薄所述衬底远离所述第二绝缘介质层的一面。The side of the substrate away from the second insulating dielectric layer is thinned. 7.如权利要求6所述的半导体器件的制造方法，其特征在于，所述凹槽延伸进入所述衬底中的深度大于或等于减薄所述衬底远离所述第二绝缘介质层的一面后剩余的所述衬底的厚度。7. The method for manufacturing a semiconductor device according to claim 6, wherein the depth to which the groove extends into the substrate is greater than or equal to the thickness of the substrate remaining after thinning a side of the substrate away from the second insulating dielectric layer. 8.如权利要求1所述的半导体器件的制造方法，其特征在于，在减薄所述上层晶圆远离所述下层晶圆的一面之后，所述半导体器件的制造方法还包括：8. The method for manufacturing a semiconductor device according to claim 1, characterized in that after thinning a side of the upper wafer away from the lower wafer, the method for manufacturing a semiconductor device further comprises: 执行第二次修剪工艺，以去除所述上层晶圆和所述下层晶圆的位于所述凹槽的靠近所述上层晶圆中心一侧的外围的边缘区域。A second trimming process is performed to remove edge regions of the upper wafer and the lower wafer located at the periphery of the groove on one side close to the center of the upper wafer. 9.如权利要求1所述的半导体器件的制造方法，其特征在于，所述凹槽为闭合或间断的环形凹槽。9 . The method for manufacturing a semiconductor device according to claim 1 , wherein the groove is a closed or discontinuous annular groove. 10.一种半导体器件，其特征在于，采用如权利要求1～9中任一项所述的半导体器件的制造方法制造。10. A semiconductor device, characterized in that it is manufactured using the method for manufacturing a semiconductor device according to any one of claims 1 to 9. 11.一种半导体器件，其特征在于，包括：11. A semiconductor device, comprising: 上层晶圆；upper wafer; 凹槽，形成于所述上层晶圆的边缘区域；A groove is formed in an edge region of the upper wafer; 第一绝缘介质层，覆盖于所述上层晶圆上，且所述第一绝缘介质层将所述凹槽封口，以使所述凹槽形成中空结构；A first insulating medium layer covers the upper wafer, and the first insulating medium layer seals the groove so that the groove forms a hollow structure; 下层晶圆，所述下层晶圆与所述第一绝缘介质层远离所述上层晶圆的一面熔融键合或混合键合，所述上层晶圆的位于所述凹槽外围的部分边缘区域相对于另一部分边缘区域内缩，所述凹槽用于阻挡减薄所述上层晶圆远离所述下层晶圆的一面的过程中从所述第一绝缘介质层与所述下层晶圆的键合界面处产生的裂纹和崩边扩展到所述凹槽所环绕的区域内。A lower wafer, wherein the lower wafer is melt-bonded or hybrid-bonded to a side of the first insulating dielectric layer away from the upper wafer, and a partial edge region of the upper wafer located at the periphery of the groove is retracted relative to another partial edge region, and the groove is used to prevent cracks and chipping generated at the bonding interface between the first insulating dielectric layer and the lower wafer during thinning of a side of the upper wafer away from the lower wafer from extending into the area surrounded by the groove. 12.如权利要求11所述的半导体器件，其特征在于，所述第一绝缘介质层形成于所述凹槽的内部且未填满所述凹槽，以使所述凹槽形成所述中空结构。12 . The semiconductor device according to claim 11 , wherein the first insulating dielectric layer is formed inside the groove and does not fill up the groove, so that the groove forms the hollow structure. 13.如权利要求11所述的半导体器件，其特征在于，所述上层晶圆包括衬底和形成于所述衬底上的第二绝缘介质层，所述凹槽自所述第二绝缘介质层凹设并贯穿所述第二绝缘介质层以进一步延伸进入所述衬底中，所述第一绝缘介质层覆盖所述第二绝缘介质层。13. The semiconductor device as described in claim 11 is characterized in that the upper wafer includes a substrate and a second insulating dielectric layer formed on the substrate, the groove is recessed from the second insulating dielectric layer and penetrates the second insulating dielectric layer to further extend into the substrate, and the first insulating dielectric layer covers the second insulating dielectric layer. 14.如权利要求11所述的半导体器件，其特征在于，所述凹槽为闭合或间断的环形凹槽。14 . The semiconductor device according to claim 11 , wherein the groove is a closed or discontinuous annular groove.
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