TWI854377B - Separating method and failure analysis method of multi-chip package - Google Patents

Abstract

A separating method of a multi-chip package includes the following steps. The multi-chip package is provided. The multi-chip package includes a bottom chip, a top chip, an insulating glue, a lead frame, a first wire, a second wire, a third wire and an encapsulant. The bottom chip comprises a pad. The lead frame comprises a plurality pins around the bottom chip and the top chip. The first wire connects the bottom chip and the pins. The second wire connects the top chip and the pins. The third wire connects the top chip and the bottom chip. The encapsulant covers the bottom chip, the top chip, the first wire, the second wire and the third wire. A portion of the encapsulant is removed to expose the top chip, the second wire, and the third wire. The second wire and third wire are cut to separate the second wire and the pins and to separate the third wire and the bottom chip. The top chip is removed to expose the insulating glue. A portion of the insulating glue is removed to expose the pad of the bottom chip.

Description

Disassembly method and failure analysis method of multi-chip package

The present invention relates to a method for disassembling a semiconductor package and a method for analyzing a failure, and in particular to a method for disassembling a multi-chip package and a method for analyzing a failure.

Multi-Chip Package (MCP) usually stacks two chips produced by different companies through wire bonding and packages them in the same package. However, this design increases the difficulty and complexity of subsequent failure analysis (FA).

For example, when a multi-chip package is undergoing a fault analysis, if the electrical inference indicates that the possible fault point is at the bottom chip of the multi-chip package (i.e., the chip at the bottom of the stacked chips), the top chip in the multi-chip package (i.e., the chip at the top of the stacked chips) needs to be removed before the bottom chip can be analyzed. However, the current method of removing the top chip mostly uses a grinding method, which makes it easy to grind off the original wire bonding of the bottom chip itself (including the wires and the pads/leads on both sides of the wires, etc.) when removing the top chip, thereby causing electrical damage to the bottom chip.

The present invention provides a multi-chip package disassembly method and a failure analysis method, which can maintain the integrity of the bottom chip itself and the original wire bonding of the bottom chip to improve the reliability of subsequent electrical verification results.

The disassembly method of the multi-chip package of the present invention comprises the following steps. First, a multi-chip package is provided. The multi-chip package comprises a bottom chip, a top chip, an insulating glue, a lead frame, a first lead, a second lead, a third lead and a sealing body. The bottom chip comprises a pad. The lead frame comprises a plurality of leads surrounding the bottom chip and the top chip. The first lead connects the bottom chip and the plurality of leads. The second lead connects the top chip and the plurality of leads. The third lead connects the top chip and the bottom chip. The sealing body covers the bottom chip, the top chip, the first lead, the second lead and the third lead. Then, a portion of the sealing body is removed to expose the top chip, the second lead and the third lead. Next, the second wire and the third wire are cut to separate the second wire from the plurality of pins and the third wire from the bottom chip. Next, the top chip is removed to expose the insulating glue. Next, a portion of the insulating glue is removed to expose the pads of the bottom chip.

In one embodiment of the present invention, the back surface of the top chip is bonded to the active surface of the bottom chip via an insulating adhesive.

In one embodiment of the present invention, after the second wire and the third wire are cut, the top chip is removed, and part of the insulating glue is removed, the connection between the bottom chip and the first wire remains intact.

In one embodiment of the present invention, the method of removing a portion of the sealing body comprises a dry etching process or a wet etching process.

In one embodiment of the present invention, the method of cutting the second wire and the third wire includes: using an ion beam of an ion focusing system to cut the second wire and the third wire.

In one embodiment of the present invention, the step of removing the top chip includes: after cutting the second wire and the third wire, heating is performed to separate the top chip from the insulating glue.

In one embodiment of the present invention, the heating condition is: maintaining at 200°C for 1 minute to 2 minutes.

In one embodiment of the present invention, the method of removing part of the insulating glue includes: performing an etching process using a chemical agent.

In one embodiment of the present invention, the step of using chemical reagents to perform an etching process includes the following steps: immersing the multi-chip package after removing the top chip in ethylenediamine and performing a first heat treatment for 2 hours; then, taking out the multi-chip package after ethylenediamine and the first heat treatment, and then performing a second heat treatment for 1 hour; then, immersing the multi-chip package after the second heat treatment in acetone and shaking it for 1 hour.

The multi-chip package failure analysis method of the present invention comprises: providing a socket board; and placing the chip package processed by the above-mentioned decomposition method in the socket board to perform circuit analysis.

Based on the above, in the disassembly method and fault analysis method of a multi-chip package of an embodiment of the present invention, by cutting the second wire and the third wire, removing the top chip and removing part of the insulating glue, the bottom chip itself and/or the original wire bonding of the bottom chip (including the connection between the bottom chip and the first wire and/or the connection between the first wire and the lead of the lead frame, etc.) will not be damaged and remain intact. In this way, there is no need to re-wire the bottom chip, and subsequent electrical verification (such as electrical analysis and physical property analysis, etc.) can be directly performed on the bottom chip, thereby not affecting the reliability of the electrical verification result.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

FIG. 1 is a flow chart of a method for separating a multi-chip package according to an embodiment of the present invention. FIG. 2 to FIG. 6 are top views of a method for separating a multi-chip package according to an embodiment of the present invention. FIG. 7 is a cross-sectional view of the multi-chip package of FIG. 2. For the sake of clarity and convenience of explanation, FIG. 2 to FIG. 6 omit some components in the multi-chip package.

The method for disassembling the multi-chip package 100 of the present embodiment may include but is not limited to the following steps:

First, please refer to FIG. 1, FIG. 2 and FIG. 7 to perform step S100 to provide a multi-chip package 100. The multi-chip package may include a substrate 110, a bottom chip 120, an insulating glue 130, a top chip 140, a lead frame 150, a first lead 160, a second lead 164, a second lead 165, a third lead 168 and a sealing body 170. In this embodiment, it is assumed that there is a problem with the circuit connection of the bottom chip 120, such as an open circuit or a short circuit in the connection between the bottom chip 120 and the first lead 160 or the connection between the first lead 160 and the lead frame 150, but it is not limited thereto.

Specifically, the bottom chip 120 is disposed on the substrate 110. The bottom chip 120 has an active surface 120a and a back surface 120b opposite to each other. The back surface 120b is closer to the substrate 110 than the active surface 120a. The bottom chip 120 may include a pad 121, a pad 121a, a pad 122, and a pad 122a. The pad 121, the pad 121a, the pad 122, and the pad 122a are respectively disposed on the active surface 120a.

The insulating glue 130 is disposed on the bottom chip 120 and between the top chip 140 and the bottom chip 120. The insulating glue 130 may expose a portion of the bottom chip 120, the pads 121 and 122, and cover another portion of the bottom chip 120, the pads 121a and 122a.

The top chip 140 is disposed on the insulating glue 130. The top chip 140 has an active surface 140a and a back surface 140b facing each other. The back surface 140b is closer to the bottom chip 120 than the active surface 140a. The back surface 140b of the top chip 140 can be attached to the active surface 120a of the bottom chip 120 through the insulating glue 130. The top chip 140 may include a pad 141, a pad 142, and a pad 143. The pad 141, the pad 142, and the pad 143 are respectively disposed on the active surface 140a.

The lead frame 150 includes a plurality of leads 151, a plurality of leads 152, and a body 153. The plurality of leads 151 and the plurality of leads 152 may surround the bottom chip 120 and the top chip 140.

The first wire 160 is disposed on the bottom chip 120. The first wire 160 can connect the pad 121 (or pad 121a) of the bottom chip 120 and the plurality of pins 151.

The second wires 164 and the second wires 165 are disposed on the top chip 140. The second wires 164 can connect the pads 141 of the top chip 140 and the plurality of pins 151, and the second wires 165 can connect the pads 142 of the top chip 140 and the plurality of pins 152.

The third wire 168 is disposed on the bottom chip 120. The third wire 168 can connect the pad 143 of the top chip 140 and the pad 122 (or pad 122a) of the bottom chip 120.

The sealing body 170 may cover the bottom chip 120 , the top chip 140 , the first wire 160 , the second wire 164 , the second wire 165 , and the third wire 168 , but is not limited thereto. In some embodiments, the sealing body 170 may further cover the substrate 110 and the insulating glue 130 .

Then, referring to FIG. 1 , FIG. 2 and FIG. 3 , step S102 is performed to remove a portion of the sealing body 170 to expose the top chip 140, the second wire 164, the second wire 165 and the third wire 168. Specifically, in the present embodiment, for example, the sealing body 170 located above the bottom chip 120 is removed to expose the top chip 140, the first wire 160, the second wire 164, the second wire 165, the third wire 168, a portion of the bottom chip 120, the pad 121 and the pad 122, but the present invention is not limited thereto. In the present embodiment, the method of removing a portion of the sealing body 170 may include, for example, a dry etching process or a wet etching process, but the present invention is not limited thereto.

Then, referring to FIG. 1 , FIG. 3 and FIG. 4 , step S104 is performed to cut the second wire 164, the second wire 165 and the third wire 168 to separate the second wire 164 from the plurality of leads 151, separate the second wire 165 from the plurality of leads 152, and separate the third wire 168 from the bottom wafer 120. In detail, in the present embodiment, the method of cutting the second wire 164, the second wire 165 and the third wire 168 may be, for example, using an ion beam of a focused ion beam (FIB) system to cut the second wire 164, the second wire 165 and the third wire 168, but is not limited thereto.

Then, referring to FIG. 1 , FIG. 4 and FIG. 5 , step S106 is performed to remove the top chip 140 to expose the insulating glue 130. In detail, in the present embodiment, the method for removing the top chip 140 may include, for example, the following steps: after cutting off the second wire 164, the second wire 165 and the third wire 168, heating is performed to separate the top chip 140 from the insulating glue 130. The heating condition may be, for example, 200° C. for 1 to 2 minutes, but is not limited thereto.

Then, referring to FIG. 1 , FIG. 5 and FIG. 6 , step S108 is performed to remove part of the insulating glue 130 to expose another part of the bottom chip 120, the pad 121a and the pad 122a, and obtain the chip package 100a that can be used for subsequent circuit analysis. Specifically, in this embodiment, the step of removing part of the insulating glue 130 can be, for example, an etching process using a chemical agent, but is not limited thereto. The step of using chemical reagents to perform an etching process may include the following steps: immersing the multi-chip package after removing the top chip 140 in ethylenediamine and performing a first heat treatment for 2 hours; then, taking out the multi-chip package after the ethylenediamine and the first heat treatment, and then performing a second heat treatment for 1 hour; then, immersing the multi-chip package after the second heat treatment in acetone and vibrating it for 1 hour. At this point, the decomposition step of the multi-chip package 100 has been substantially completed. In some embodiments, when removing part of the insulating glue, the thickness of the insulating glue covering the active surface of the bottom chip can also be reduced to facilitate the subsequent electrical analysis or physical property analysis of the bottom chip.

In the disassembly method of the multi-chip package 100 of the present embodiment, after cutting the second wire 164 (or the second wire 165) and the third wire 168 (i.e., step S104), removing the top chip 140 (i.e., step S106), and removing part of the insulating glue 130 (i.e., step S108), the bottom chip 120 itself and/or the original wire bonding of the bottom chip 120 (including the connection between the bottom chip 120 and the first wire 160 and/or the connection between the first wire 160 and the pin 151 of the lead frame 150, etc.) will not be damaged and will remain intact. In this way, there is no need to re-wire the bottom wafer 120, and subsequent electrical verification (such as electrical analysis and physical property analysis, etc.) can be directly performed on the bottom wafer 120, thereby not affecting the reliability of the electrical verification result.

Other embodiments are listed below for illustration. It must be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

FIG8 is a top view schematic diagram of a multi-chip package failure analysis method according to an embodiment of the present invention. The multi-chip package failure analysis method 100 according to the present embodiment may include but is not limited to the following steps:

First, referring to FIG. 8 , a socket board 200 is provided. The socket board 200 includes a substrate 210 and a plurality of detection units 220. The substrate 210 has an opening 211. The plurality of detection units 220 are disposed on the substrate 210. The plurality of detection units 220 may be disposed around the opening 211, and the plurality of detection units 220 may surround the opening 211. The plurality of detection units 220 may include a plurality of detection pads 221.

Next, please continue to refer to FIG8 , and place the chip package 100a after the disassembly method in FIG7 in the opening 211 of the socket board 200 for circuit analysis. In this way, the circuit connection problem (such as open circuit or short circuit, etc.) in the bottom chip 120 is detected for repair.

9A and 9B are circuit analysis results of a multi-chip package before and after separation according to an embodiment of the present invention.

Specifically, FIG. 9A is a circuit analysis result performed using a multi-chip package before separation (i.e., the multi-chip package 100 shown in FIG. 2 ), and FIG. 9B is a circuit analysis result performed using a multi-chip package after separation (i.e., the chip package 100a shown in FIG. 6 ).

From the results of Figures 9A and 9B, it can be seen that the curve in the current-voltage relationship diagram of Figure 9A is roughly similar to the curve in the current-voltage relationship diagram of Figure 9B, thereby indicating that the state of the bottom chip 120 in the multi-chip package before separation (i.e., the multi-chip package 100 shown in Figure 2) is roughly similar to the state of the bottom chip 120 in the multi-chip package after separation (i.e., the chip package 100a shown in Figure 6), and also indicating that after being processed by the decomposition method of this embodiment, the bottom chip 120 itself and/or the original wire bonding of the bottom chip 120 in the chip package 100a will not be damaged and will remain intact.

In summary, in the disassembly method and fault analysis method of a multi-chip package of an embodiment of the present invention, by cutting off the second wire and the third wire, removing the top chip and removing part of the insulating glue, the bottom chip itself and/or the original wire bonding of the bottom chip (including the connection between the bottom chip and the first wire and/or the connection between the first wire and the lead of the lead frame, etc.) will not be damaged and will remain intact. In this way, there is no need to re-wire the bottom chip, and subsequent electrical verification (such as electrical analysis and physical property analysis, etc.) can be directly performed on the bottom chip, thereby not affecting the reliability of the electrical verification result.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100: multi-chip package 100a: chip package 110: substrate 120: bottom chip 120a, 140a: active surface 120b, 140b: back surface 121, 121a, 122, 122a, 141, 142, 143: pads 130: insulating glue 140: top chip 150: lead frame 151, 152: lead 153: body 160: first lead 164, 165: second lead 168: third lead 170: sealing body 200: socket board 210: substrate 211: opening 220: detection unit 221: detection pad S100, S102, S104, S106, S108: Steps

FIG. 1 is a flow chart of a method for separating a multi-chip package according to an embodiment of the present invention. FIG. 2 to FIG. 6 are schematic top views of a method for separating a multi-chip package according to an embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of the multi-chip package of FIG. 2. FIG. 8 is a schematic top view of a method for analyzing a failure of a multi-chip package according to an embodiment of the present invention. FIG. 9A and FIG. 9B are circuit analysis results of a multi-chip package according to an embodiment of the present invention before and after separation, respectively.

100a: chip package 110: substrate 120: bottom chip 121, 121a, 122, 122a: pads 130: insulating glue 150: lead frame 151, 152: pins 153: body 160: first lead

Claims (9)

A method for disassembling a multi-chip package comprises: providing the multi-chip package, wherein the multi-chip package comprises a bottom chip, a top chip, an insulating glue, a lead frame, a first lead, a second lead, a third lead and a sealing body, wherein the bottom chip comprises a pad, the lead frame comprises a plurality of leads surrounding the bottom chip and the top chip, the first lead connects the bottom chip and the plurality of leads, the second lead connects the top chip and the plurality of leads, the third lead connects the top chip and the bottom chip, and the sealing body covers the bottom chip, the top chip, the first lead, the second lead and the third lead. The invention relates to a method for manufacturing a semiconductor device ... The decomposition method as described in claim 1, wherein the back surface of the top chip is adhered to the active surface of the bottom chip through the insulating glue. The decomposition method as described in claim 1, wherein the method of removing the portion of the sealant includes a dry etching process or a wet etching process. The decomposition method as described in claim 1, wherein the step of cutting the second wire and the third wire includes: cutting the second wire and the third wire using an ion beam of an ion focusing system. The decomposition method as described in claim 1, wherein the step of removing the top chip includes: after cutting the second wire and the third wire, heating to separate the top chip from the insulating glue. The decomposition method as described in claim 5, wherein the heating condition is: maintaining at 200°C for 1 minute to 2 minutes. In the decomposition method as described in claim 1, the method for removing part of the insulating glue includes: performing an etching process using a chemical agent. The decomposition method as described in claim 7, wherein the step of using the chemical agent to perform an etching process includes: immersing the multi-chip package after removing the top chip in ethylenediamine and performing a first heat treatment for 2 hours; taking out the multi-chip package after the ethylenediamine and the first heat treatment, and then performing a second heat treatment for 1 hour; and immersing the multi-chip package after the second heat treatment in acetone and vibrating it for 1 hour, thereby exposing the pad of the bottom chip. A method for failure analysis of a multi-chip package, comprising: providing a socket board; and placing the chip package processed by the decomposition method described in claim 1 in the socket board to perform circuit analysis.

Images