CN113849029B - Under-voltage detection circuit of self-biased reference source - Google Patents

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to a self-biased reference source under-voltage detection circuit. The circuit of the invention can be divided into two parts: a self-compensation circuit and a comparator circuit. The self-compensating circuit is used for acquiring voltage proportional to REF, 2 proportions can be realized, and OUT is low level and high level which respectively correspond to one proportion under the influence of the output state of the circuit. The comparator adopts a common core to realize the function of the comparator. The invention can realize an undervoltage detection circuit with a hysteresis reference, and can realize proportional voltage conversion of REF only by depending on a self-compensation circuit.

Description

A self-biased reference source undervoltage detection circuit

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to a self-biased reference source undervoltage detection circuit.

Background technique

In the integrated circuit, the undervoltage detection circuit of the reference source is a very important circuit. It detects and judges the reference voltage value of the system, and provides information on whether the reference is in a suitable state for subsequent circuits. The undervoltage information of the reference is usually It is a prerequisite for whether the overall system is enabled or not, and determines whether the subsequent circuits can start to work, avoiding system errors caused by insufficient reference voltage values. Taking the power management chip as an example, the reference voltage is usually the reference voltage of the internal LDO. If the reference voltage is in an under-voltage state, the output voltage of the LDO will be insufficient, causing the problem of insufficient power supply voltage of the subsequent circuits, which will affect the normal operation of the entire chip; In addition, the reference voltage is often the input of many key internal comparators, which determines the logic judgment of some signals. Insufficient reference voltage will seriously affect the logic judgment of the system, thereby affecting the expected effect and function of the entire system architecture. Therefore, it is very important to develop a suitable reference under-voltage detection circuit.

SUMMARY OF THE INVENTION

The purpose of the present invention is to solve the problem that the chip can't work normally due to insufficient reference voltage inside the chip and cause the chip to fail to achieve the expected function, and proposes a self-biased reference undervoltage detection circuit.

For achieving the above object, the technical scheme of the present invention is:

A self-biased reference source undervoltage detection circuit, comprising a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube PMOS tube, ninth PMOS tube, tenth PMOS tube, first NMOS tube, second NMOS tube, third NMOS tube, first resistor, second resistor, third resistor, fourth resistor, fifth resistor, first A triode, a second triode, a first inverter, a second inverter, a third inverter and a capacitor; the source of the first PMOS transistor is connected to the power supply, and its gate and drain are interconnected, and its The drain, the drain of the eighth PMOS tube and the drain of the first NMOS tube; the source of the eighth PMOS tube is connected to the power supply, and the gate of the eighth PMOS tube is connected to the enable signal; the gate of the first NMOS tube is connected to the second PMOS tube The drain, the source of which is grounded through the first resistor; the source of the second PMOS transistor is connected to the power supply, the gate of which is connected to the drain of the first PMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor The gate and drain of the second NMOS tube are interconnected, and the source is connected to the reference voltage; the source of the third PMOS tube is connected to the power supply, the gate is connected to the drain of the first PMOS tube, and the drain of the third PMOS tube It is connected to the source of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the output end of the second inverter, and its drain is connected to the reference voltage through the second resistor; the source of the fourth PMOS tube is connected to the power supply, and its gate The electrode is connected to the drain of the first PMOS tube, the drain of the fourth PMOS tube is connected to the reference voltage through the second resistor; the source of the fifth PMOS tube is connected to the power supply, its gate and drain are interconnected, and its drain is connected to the first The drain of the nine PMOS tubes; the source of the ninth PMOS tube is connected to the power supply, and its gate is connected to the enable signal; the collector of the first triode is connected to the drain of the fifth PMOS tube, and the base of the first triode It is connected to the connection point between the drain of the fourth PMOS tube and the drain of the fifth PMOS tube. The emitter of the first transistor passes through the third resistor and the fourth resistor in turn and is grounded; the source of the sixth PMOS tube is connected to the power supply, and its gate The electrode is connected to the drain of the fifth PMOS tube, the drain of the sixth PMOS tube is connected to the collector of the second triode, the drain of the tenth PMOS tube, one end of the capacitor and the gate of the seventh PMOS tube; the second triode The base of the tube is connected to the base of the first triode, and the emitter of the second triode is grounded after passing through the fourth resistor; the source of the tenth PMOS tube is connected to the power supply, and its gate is connected to the enable signal; the other side of the capacitor is connected to the power supply. One end is connected to the power supply; the source of the seventh PMOS tube is connected to the power supply, and its drain is connected to the input end of the second inverter and one end of the fifth resistor; the other end of the fifth resistor is grounded; the gate of the third NMOS tube is connected to the first The output terminal of an inverter, its drain is connected to the input terminal of the first inverter, the source terminal of the third NMOS transistor is grounded, and the input terminal of the first inverter is connected to the enable signal; the output of the second inverter The terminal is connected to the input end of the third inverter, and the output end of the third inverter is the output end of the detection circuit.

The beneficial effect of the present invention is that the present invention can realize an under-voltage detection circuit with a hysteresis reference, and can realize the proportional voltage conversion of REF only by relying on the self-compensation circuit.

Description of drawings

Figure 1 is the timing diagram of the undervoltage detection circuit of the benchmark;

Fig. 2 is the voltage detection circuit diagram of the reference.

Detailed ways

Below in conjunction with accompanying drawing, the technical scheme of the present invention is described in detail:

Figure 1 is the timing diagram of the reference undervoltage detection circuit. When the reference voltage REF starts to increase from a low voltage, and when REF increases to the voltage value of V _{REF_ON} , the output logic OUT will flip from low level to high level; when REF starts to decrease from a higher voltage. When REF decreases to a voltage value less than C _{REF_OFF} , the output logic OUT transitions from high level to low level. There is a hysteresis window for the brownout detection points for REF low-to-high and high-to-low changes, and V _{REF_ON} is higher than V _{REF_OFF} .

Figure 2 is a reference voltage detection circuit diagram, including 5 resistors, 1 capacitor, 2 npn bipolar transistors, 3 N-type MOSFETs, 10 P-type MOSFETs and 3 inverters. Both N-type MOSFET and P-type MOSFET are 5V low-voltage devices, and the size ratio of transistors Q1 and Q2 is 8:1. The input signal of the circuit includes two inputs: the reference voltage REF, the enable signal EN, the output signal of the circuit is OUT, the power rail of the circuit is VCC-GND, and the difference between the power rails is 5V.

The transistors N3, P8, P9, and P10 in the circuit are all enable tubes. When the enable signal EN is at a high level of 1, the circuit enable is valid, and the enable tubes are in the off state; when the enable signal EN is at a low level of 0 , the circuit enable is invalid, the enable tubes are all turned on, and the voltage of the key node of the circuit is pulled to the corresponding power rail voltage.

In addition to the enable tube, the circuit can be roughly divided into two parts: self-compensation circuit and comparator circuit. The self-compensation circuit is used to obtain a voltage proportional to REF, which can achieve two ratios, which are affected by the output state of the circuit. OUT is low level and high level respectively corresponds to one of the ratios. The comparator implements the comparator function using a common core, where the ratio between Q1 and Q2 is 8:1.

In the self-compensation circuit, the size ratio of N1 and N2 and the size ratio of P1 and P2 are both 4:1, R1 and R2 use matching resistors, and the size ratio of P1 and P3 and P4 are both 4:2. This circuit mainly adopts the method of voltage to current and current to voltage to realize a comparison voltage V _CMP proportional to REF. After the REF voltage value passes through N1 and N2 tubes, the voltage acting on both ends of R1 is:

V _R1 =REF+V _gs.N2 -V _gs.N1

Since the ratios of the circuit current mirrors N1 and N2 are the same as those of P1 and P2, the V _GS of N1 and N2 are equal, which realizes the self-compensation of V _GS , thereby realizing a current I1 determined by REF.

The current I1 acts on R2 after the current mirror to realize the function of current-to-voltage conversion. Finally, V _CMP proportional to REF can be obtained. When OUT is low, node A is high, and the P5 tube is in the off state. The current through R2 is 0.5 times the current of R1; when OUT is high, the A node is low, the P5 tube is in the open state, and the current flowing through R2 is 1 times the current of R1.

OUT为高电平

OUT is high

OUT为低电平

OUT is low

The comparator is a conventional comparator structure. The inversion point of the comparator is a conventional voltage value of 1.2V, which is mainly realized by the core. The ratio of Q1 and Q2 is 8:1. At the critical inversion point, the current flowing through Q1 and Q2 The values are equal, both equal to the current flowing through R3 at this time.

The inversion point V _Triggle of the input voltage realized by the comparator is:

When the input voltage of the comparator is lower than V _Triggle , the current flowing through Q1 will be greater than the current flowing through Q2, and the output of the comparator is low; when the input voltage of the comparator is higher than V _Triggle , the current flowing through Q1 The current will be less than the current flowing through Q2, and the output of the comparator will be high;

The specific working states of the circuit for the two changing trends of the input signal REF are described below.

1. REF increases from low voltage

When RFF is low, the voltage value of V _CMP is also low, lower than V _Trigggle , at this time OUT is low level, node A is also high level, P5 tube is in the off state, the difference between V _CMP and REF at this time is The proportional relationship between them is:

When RFF gradually increases, the voltage value of V _CMP also gradually increases. After reaching V _Trigggle , the current flowing through Q1 will be less than the current flowing through Q2, so that the state of OUT is flipped from low level to high level, Therefore, the following comparison points can be implemented for REF:

At this time, although OUT becomes high level, the potential of node A becomes low level, which causes the P5 tube to change from the off state to the on state, which means that the voltage drop on R2 becomes larger, and the output of the comparator will remain low and will not affect the comparator output.

2. REF starts to decrease from high voltage

When RFF is high, the voltage value of V _CMP is also high, higher than V _Trigggle , the current flowing through Q1 will be less than the current flowing through Q2, so OUT is high level, node A is low level, The P5 tube is in the open state, and the proportional relationship between V _CMP and REF at this time is:

When RFF gradually decreases, the voltage value of V _CMP also gradually decreases. After it is lower than V _Trigggle , the current flowing through Q1 will be greater than the current flowing through Q2, so that the state of OUT is flipped from high level to low level, Therefore, the following comparison points can be implemented for REF:

At this time, although OUT becomes low level, the potential of node A becomes high level, which causes the P5 tube to change from the on state to the off state, which means that the voltage drop on R2 becomes smaller, and the output of the comparator becomes smaller. will remain high and will not affect the comparator output.

To sum up, the present invention can realize a reference undervoltage detection circuit with hysteresis, and can realize the proportional voltage conversion of REF only by relying on the self-compensation circuit.

Claims (1)

1. A self-bias reference source under-voltage detection circuit is characterized by comprising a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first triode, a second triode, a first phase inverter, a second phase inverter, a third phase inverter and a capacitor; the source electrode of the first PMOS tube is connected with a power supply, the grid electrode and the drain electrode of the first PMOS tube are interconnected, and the drain electrode of the first PMOS tube, the drain electrode of the eighth PMOS tube and the drain electrode of the first NMOS tube are connected with the power supply; the source electrode of the eighth PMOS tube is connected with the power supply, and the grid electrode of the eighth PMOS tube is connected with the enable signal; the grid electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, and the source electrode of the first NMOS tube is grounded through the first resistor; the source electrode of the second PMOS tube is connected with a power supply, the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode and the drain electrode of the second NMOS tube are interconnected, and the source electrode of the second NMOS tube is connected with a reference voltage; the source electrode of the third PMOS tube is connected with a power supply, the grid electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the output end of the second phase inverter, and the drain electrode of the fifth PMOS tube is connected with reference voltage after passing through the second resistor; the source electrode of the fourth PMOS tube is connected with the power supply, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the reference voltage after passing through the second resistor; the source electrode of the fifth PMOS tube is connected with the power supply, the grid electrode of the fifth PMOS tube is interconnected with the drain electrode of the fifth PMOS tube, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the ninth PMOS tube; the source electrode of the ninth PMOS tube is connected with the power supply, and the grid electrode of the ninth PMOS tube is connected with the enable signal; a collector of the first triode is connected with a drain electrode of the fifth PMOS tube, a base electrode of the first triode is connected with a connection point of a drain electrode of the fourth PMOS tube and a drain electrode of the fifth PMOS tube, and an emitter of the first triode is grounded after passing through the third resistor and the fourth resistor in sequence; the source electrode of the sixth PMOS tube is connected with the power supply, the grid electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the collector electrode of the second triode, the drain electrode of the tenth PMOS tube, one end of the capacitor and the grid electrode of the seventh PMOS tube; the base electrode of the second triode is connected with the base electrode of the first triode, and the emitting electrode of the second triode is grounded after passing through the fourth resistor; the source electrode of the tenth PMOS tube is connected with the power supply, and the grid electrode of the tenth PMOS tube is connected with the enable signal; the other end of the capacitor is connected with a power supply; the source electrode of the seventh PMOS tube is connected with the power supply, and the drain electrode of the seventh PMOS tube is connected with the input end of the second phase inverter and one end of the fifth resistor; the other end of the fifth resistor is grounded; the grid electrode of the third NMOS tube is connected with the output end of the first phase inverter, the drain electrode of the third NMOS tube is connected with the input end of the first phase inverter, the source electrode of the third NMOS tube is grounded, and the input end of the first phase inverter is connected with an enable signal; the output end of the second phase inverter is connected with the input end of the third phase inverter, and the output end of the third phase inverter is the output end of the detection circuit.

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