CN113849029A - A self-biased reference source undervoltage detection circuit - Google Patents
A self-biased reference source undervoltage detection circuit Download PDFInfo
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- CN113849029A CN113849029A CN202111129201.8A CN202111129201A CN113849029A CN 113849029 A CN113849029 A CN 113849029A CN 202111129201 A CN202111129201 A CN 202111129201A CN 113849029 A CN113849029 A CN 113849029A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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Abstract
本发明属于电子电路技术领域，具体涉及一种自偏置基准源欠压检测电路。本发明的电路可以分为两个部分：自补偿电路和比较器电路。自补偿电路用于获取与REF成比例的电压，可实现2种比例，受电路的输出状态影响，OUT为低电平和高电平分别对应其中一种比例。比较器采用常见的核心实现比较器功能。本发明可以实现一个具有迟滞的基准的欠压检测电路，仅仅依赖自补偿电路就可以实现REF的成比例电压转换。
The invention belongs to the technical field of electronic circuits, and in particular relates to a self-biased reference source undervoltage detection circuit. The circuit of the present invention can be divided into two parts: a self-compensating circuit and a comparator circuit. The self-compensation circuit is used to obtain a voltage proportional to REF, which can achieve two ratios, which are affected by the output state of the circuit. OUT is low level and high level respectively corresponds to one of the ratios. The comparator implements the comparator function using a common core. The invention can realize an under-voltage detection circuit with a hysteresis reference, and can realize the proportional voltage conversion of REF only by relying on the self-compensating circuit.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a self-biased reference source under-voltage detection circuit.
Background
In an integrated circuit, a reference source under-voltage detection circuit is an important circuit, detects and judges a reference voltage value of a system, provides information whether a reference is in a proper state for a subsequent circuit, and the reference under-voltage information is usually a prerequisite condition whether the whole system is enabled to be effective or not, determines whether the subsequent circuit can start working or not, and avoids system errors caused by insufficient reference voltage value. Taking a power management chip as an example, the reference voltage is usually the reference voltage of the internal LDO, and if the reference voltage is in an undervoltage state, the output voltage of the LDO is insufficient, which causes the problem of insufficient supply voltage of a subsequent circuit, and affects the normal operation of the whole chip; in addition, the reference voltage is often input to many key comparators inside, which determine the logic judgment of some signals, and the shortage of the reference voltage will seriously affect the logic judgment of the system, thereby affecting the expected effect and function of the whole system architecture. Therefore, it is very important to develop a suitable reference undervoltage detection circuit.
Disclosure of Invention
The invention aims to solve the problems that the normal work of a chip is influenced and the chip cannot realize the expected function due to insufficient reference voltage in the chip, and provides a self-bias reference under-voltage detection circuit.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a self-bias reference source under-voltage detection circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first triode, a second triode, a first phase inverter, a second phase inverter, a third phase inverter and a capacitor; the source electrode of the first PMOS tube is connected with a power supply, the grid electrode and the drain electrode of the first PMOS tube are interconnected, and the drain electrode of the first PMOS tube, the drain electrode of the eighth PMOS tube and the drain electrode of the first NMOS tube are connected with the power supply; the source electrode of the eighth PMOS tube is connected with the power supply, and the grid electrode of the eighth PMOS tube is connected with the enable signal; the grid electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, and the source electrode of the first NMOS tube is grounded through the first resistor; the source electrode of the second PMOS tube is connected with a power supply, the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode and the drain electrode of the second NMOS tube are interconnected, and the source electrode of the second NMOS tube is connected with a reference voltage; the source electrode of the third PMOS tube is connected with a power supply, the grid electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the output end of the second phase inverter, and the drain electrode of the fifth PMOS tube is connected with reference voltage after passing through the second resistor; the source electrode of the fourth PMOS tube is connected with the power supply, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the reference voltage after passing through the second resistor; the source electrode of the fifth PMOS tube is connected with the power supply, the grid electrode of the fifth PMOS tube is interconnected with the drain electrode of the fifth PMOS tube, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the ninth PMOS tube; the source electrode of the ninth PMOS tube is connected with the power supply, and the grid electrode of the ninth PMOS tube is connected with the enable signal; a collector of the first triode is connected with a drain electrode of the fifth PMOS tube, a base electrode of the first triode is connected with a connection point of a drain electrode of the fourth PMOS tube and a drain electrode of the fifth PMOS tube, and an emitter of the first triode is grounded after passing through the third resistor and the fourth resistor in sequence; the source electrode of the sixth PMOS tube is connected with the power supply, the grid electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the collector electrode of the second triode, the drain electrode of the tenth PMOS tube, one end of the capacitor and the grid electrode of the seventh PMOS tube; the base electrode of the second triode is connected with the base electrode of the first triode, and the emitting electrode of the second triode is grounded after passing through the fourth resistor; the source electrode of the tenth PMOS tube is connected with the power supply, and the grid electrode of the tenth PMOS tube is connected with the enable signal; the other end of the capacitor is connected with a power supply; the source electrode of the seventh PMOS tube is connected with the power supply, and the drain electrode of the seventh PMOS tube is connected with the input end of the second inverter and one end of the fifth resistor; the other end of the fifth resistor is grounded; the grid electrode of the third NMOS tube is connected with the output end of the first phase inverter, the drain electrode of the third NMOS tube is connected with the input end of the first phase inverter, the source electrode of the third NMOS tube is grounded, and the input end of the first phase inverter is connected with an enable signal; the output end of the second phase inverter is connected with the input end of the third phase inverter, and the output end of the third phase inverter is the output end of the detection circuit.
The invention has the advantages that the invention can realize an undervoltage detection circuit with a hysteresis reference, and the proportional voltage conversion of REF can be realized only by depending on a self-compensation circuit.
Drawings
FIG. 1 is a timing diagram of a reference brown-out detection circuit;
fig. 2 is a diagram of a reference voltage detection circuit.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings:
FIG. 1 is a timing diagram of a reference brown-out detection circuit that begins increasing when a reference voltage REF starts to increase from a low voltage and reaches V when REF increasesREF_ONAfter the voltage value is reached, the output logic OUT is turned from low level to high level; when REF is decreased from a higher voltage, when REF is decreased to less than VREF_OFFThe output logic OUT is turned from high to low only after the voltage value of (1). There is a hysteresis window, V, for the under-voltage detection points where REF changes from low to high and from high to lowREF_ONRatio VREF_OFFIs high.
Fig. 2 is a reference voltage detection circuit diagram including 5 resistors, 1 capacitor, 2 npn bipolar transistors, 3N-type MOSFETs, 10P-type MOSFETs, and 3 inverters. The N-type MOSFET and the P-type MOSFET are both 5V low-voltage devices, and the size ratio of the triodes Q1 and Q2 is 8: 1. The input signal of the circuit comprises two inputs: reference voltage REF and an enable signal EN, an output signal of the circuit is OUT, a power supply rail of the circuit is VCC-GND, and the difference value between the power supply rails is 5V.
In the circuit, the N3, P8, P9 and P10 transistors are all enable tubes, when an enable signal EN is at a high level 1, the circuit is enabled, and the enable tubes are all in a cut-off state; when the enable signal EN is low level 0, the circuit is enabled inefficiently, the enable tubes are all in an open state, and the voltage of the key node of the circuit is pulled to the corresponding power supply rail voltage.
In addition to the enable tube, the circuit can be roughly divided into two parts: a self-compensation circuit and a comparator circuit. The self-compensating circuit is used for acquiring voltage proportional to REF, 2 proportions can be realized, and OUT is low level and high level which respectively correspond to one proportion under the influence of the output state of the circuit. The comparator uses a common core to implement the comparator function, wherein the ratio between Q1 and Q2 is 8: 1.
In the self-compensating circuit, the size ratio of N1 and N2 and the size ratio of P1 and P2 are both 4: 1, R1 and R2 adopt matched resistors, and the size ratio of P1, P3 and P4 is 4: 2. The circuit mainly adopts a mode of converting voltage into current and converting current into voltage to realize a sumREF proportional comparison voltage VCMPThe REF voltage value is the voltage applied to the two ends of R1 after passing through N1 and N2 tubes:
VR1＝REF+Vgs.N2-Vgs.N1
since the circuit current mirrors N1, N2 are in the same proportion as P1, P2, V of N1, N2GSEqual, realize VGSThereby achieving a REF-dependent current I1.
The current I1 is subjected to current mirror image and then acts on R2 to realize the function of current-to-voltage conversion, and finally V proportional to REF can be obtainedCMPWhen OUT is high, the a node is high, the P5 transistor is in off state, and the current flowing through R2 is 0.5 times the current of R1; when OUT is low, node a is low, the P5 transistor is on, and the current through R2 is 1 times the current of R1.
The comparator is of a conventional comparator structure, the switching point of the comparator is a conventional voltage value of 1.2V, the comparator is mainly realized by a core, the ratio of Q1 to Q2 is 8: 1, and at the critical switching point, the current values flowing through Q1 and Q2 are equal, and the current flowing through R3 is equal.
Inverting point V of input voltage realized by comparatorTriggleComprises the following steps:
when the input voltage of the comparator is lower than VTriggleThen, the current flowing through Q1 will be greater than the current flowing through Q2, and the output of the comparator is low; when the input voltage of the comparator is higher than VTriggleThen the current through Q1 will be less than the current through Q2 and the output of the comparator is high;
the following two trends of the input signal REF illustrate the specific operating state of the circuit.
1. REF increases from a low voltage
When RFF is low, VCMPAlso lower than VTrigggleAt this time, OUT is low, node a is high, and P5 is off, and V is at this timeCMPAnd REF is:
after the RFF is gradually increased, VCMPAlso gradually increases to reach VTrigggleThen, the current flowing through Q1 will be smaller than the current flowing through Q2, thereby flipping the state of OUT from low to high, so the following comparison point can be achieved for REF:
at this time, although OUT becomes high, the potential of the a node becomes low, which causes the P5 transistor to turn from off to on, which means that the voltage drop across R2 becomes larger, and the output of the comparator will remain low without affecting the output of the comparator.
2. REF decreases from high voltage
When RFF is high, VCMPAlso has a higher voltage value than VTrigggleAt this time, the current flowing through Q1 will be smaller than the current flowing through Q2, so OUT isHigh level, node A is low level, P5 tube is in open state, V at this timeCMPAnd REF is:
after the RFF is gradually reduced, VCMPAlso gradually decreases below VTrigggleThen, the current flowing through Q1 will be greater than the current flowing through Q2, causing the state of OUT to flip from low to high, thus achieving the following comparison point for REF:
at this time, although OUT becomes low, the potential of the a node becomes high, which causes the P5 transistor to turn from on state to off state, which means that the voltage drop across R2 becomes smaller, and the output of the comparator will remain high without affecting the output of the comparator.
In summary, the present invention can realize an under-voltage detection circuit with hysteresis reference, and only rely on the self-compensation circuit to realize the proportional voltage conversion of REF.
Claims (1)
1. A self-bias reference source under-voltage detection circuit is characterized by comprising a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first triode, a second triode, a first phase inverter, a second phase inverter, a third phase inverter and a capacitor; the source electrode of the first PMOS tube is connected with a power supply, the grid electrode and the drain electrode of the first PMOS tube are interconnected, and the drain electrode of the first PMOS tube, the drain electrode of the eighth PMOS tube and the drain electrode of the first NMOS tube are connected with the power supply; the source electrode of the eighth PMOS tube is connected with the power supply, and the grid electrode of the eighth PMOS tube is connected with the enable signal; the grid electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, and the source electrode of the first NMOS tube is grounded through the first resistor; the source electrode of the second PMOS tube is connected with a power supply, the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode and the drain electrode of the second NMOS tube are interconnected, and the source electrode of the second NMOS tube is connected with a reference voltage; the source electrode of the third PMOS tube is connected with a power supply, the grid electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the output end of the second phase inverter, and the drain electrode of the fifth PMOS tube is connected with reference voltage after passing through the second resistor; the source electrode of the fourth PMOS tube is connected with the power supply, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the reference voltage after passing through the second resistor; the source electrode of the fifth PMOS tube is connected with the power supply, the grid electrode of the fifth PMOS tube is interconnected with the drain electrode of the fifth PMOS tube, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the ninth PMOS tube; the source electrode of the ninth PMOS tube is connected with the power supply, and the grid electrode of the ninth PMOS tube is connected with the enable signal; a collector of the first triode is connected with a drain electrode of the fifth PMOS tube, a base electrode of the first triode is connected with a connection point of a drain electrode of the fourth PMOS tube and a drain electrode of the fifth PMOS tube, and an emitter of the first triode is grounded after passing through the third resistor and the fourth resistor in sequence; the source electrode of the sixth PMOS tube is connected with the power supply, the grid electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the collector electrode of the second triode, the drain electrode of the tenth PMOS tube, one end of the capacitor and the grid electrode of the seventh PMOS tube; the base electrode of the second triode is connected with the base electrode of the first triode, and the emitting electrode of the second triode is grounded after passing through the fourth resistor; the source electrode of the tenth PMOS tube is connected with the power supply, and the grid electrode of the tenth PMOS tube is connected with the enable signal; the other end of the capacitor is connected with a power supply; the source electrode of the seventh PMOS tube is connected with the power supply, and the drain electrode of the seventh PMOS tube is connected with the input end of the second inverter and one end of the fifth resistor; the other end of the fifth resistor is grounded; the grid electrode of the third NMOS tube is connected with the output end of the first phase inverter, the drain electrode of the third NMOS tube is connected with the input end of the first phase inverter, the source electrode of the third NMOS tube is grounded, and the input end of the first phase inverter is connected with an enable signal; the output end of the second phase inverter is connected with the input end of the third phase inverter, and the output end of the third phase inverter is the output end of the detection circuit.
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Cited By (3)
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| CN116400127A (en) * | 2023-06-09 | 2023-07-07 | 拓尔微电子股份有限公司 | Undervoltage detection circuit, power management chip and undervoltage detection method |
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