CN113838870A - Display panel and manufacturing method thereof - Google Patents
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- CN113838870A CN113838870A CN202111114150.1A CN202111114150A CN113838870A CN 113838870 A CN113838870 A CN 113838870A CN 202111114150 A CN202111114150 A CN 202111114150A CN 113838870 A CN113838870 A CN 113838870A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
- H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
- H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
- H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
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Abstract
一种显示面板及其制作方法，显示面板包括像素阵列基板及发光元件。像素阵列基板包括基板、主动元件、平坦层、多个金属接垫及多个导电氧化物图案。主动元件位于基板上并具有漏极。平坦层位于主动元件上。金属接垫位于平坦层上，主动元件的漏极电性连接金属接垫的其中之一。导电氧化物图案具有多个分别位于各金属接垫上的第一导电保护部，各第一导电保护部具有一开口，开口重叠于各金属接垫的顶面。发光元件位于像素阵列基板上，发光元件通过各第一导电保护部的开口电性连接各金属接垫。
A display panel and a manufacturing method thereof. The display panel includes a pixel array substrate and a light-emitting element. The pixel array substrate includes a substrate, an active element, a flat layer, a plurality of metal pads and a plurality of conductive oxide patterns. The active element is on the substrate and has a drain. The flat layer is on the active element. The metal pads are located on the flat layer, and the drain of the active device is electrically connected to one of the metal pads. The conductive oxide pattern has a plurality of first conductive protection portions respectively located on the metal pads, each of the first conductive protection portions has an opening, and the opening overlaps the top surface of each metal pad. The light-emitting element is located on the pixel array substrate, and the light-emitting element is electrically connected to each metal pad through the opening of each first conductive protection portion.
Description
Technical Field
The invention relates to a display panel and a manufacturing method thereof.
Background
The light emitting diode display panel has the advantages of electricity saving, high efficiency, high brightness, fast response time and the like, and is provided with a connecting pad and a circuit layer. In order to shield the light reflected by the circuit layer to maintain the display quality, a light shielding layer is required. However, the process of the light shielding layer includes a high temperature process, which may oxidize the pad. If the passivation layer is to be formed on the pad, the manufacturing cost will be increased. Therefore, the LED display panel with low manufacturing cost and capability of protecting the connecting pad is not easy to realize.
Disclosure of Invention
The invention provides a display panel, which can save cost and protect metal pads from being oxidized in a high-temperature process.
The invention provides a manufacturing method of a display panel, which can save cost and protect metal pads from being oxidized in a high-temperature process.
The display panel of an embodiment of the invention includes a pixel array substrate and a light emitting device. The pixel array substrate comprises a substrate, an active element, a flat layer, a plurality of metal pads and a plurality of conductive oxide patterns. The active element is positioned on the substrate and is provided with a drain electrode. The flat layer is located on the active device. The metal connecting pad is positioned on the flat layer, and the drain electrode of the active element is electrically connected with one of the metal connecting pads. The conductive oxide pattern has a plurality of first conductive protection portions respectively located on the metal pads, and each first conductive protection portion has an opening overlapping the top surface of each metal pad. The light-emitting element is positioned on the pixel array substrate and is electrically connected with the metal connecting pads through the openings of the first conductive protection parts.
The method for manufacturing the display panel of the embodiment of the invention comprises the following steps. An active device is formed on the substrate, wherein the active device comprises a drain. And forming a flat layer on the drain electrode, wherein the flat layer is provided with a plurality of through holes. And forming a metal layer on the flat layer so that the metal layer is filled in each through hole. A conductive oxide layer is formed on the metal layer. A photoresist material layer is formed on the conductive oxide layer. The photoresist material layer is defined with a mask to form a plurality of photoresist patterns. The conductive oxide layer is patterned using the photoresist pattern as a mask to form a plurality of conductive oxide patterns. And patterning the metal layer by using the photoresist pattern as a mask to form a plurality of metal pads, wherein the conductive oxide pattern comprises a plurality of first conductive protection parts positioned on each metal pad. And partially removing each first conductive protection part to enable each first conductive protection part to be provided with an opening to expose the top surface of each metal pad. And arranging a light-emitting element on each metal pad, wherein the light-emitting element is provided with a first electrode which is electrically connected with one of the metal pads.
Drawings
Various aspects of the disclosure can be understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that the various features of the drawings are not to scale in accordance with standard practice in the industry. In fact, the dimensions of the features described may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention.
Fig. 2 to 13 are schematic cross-sectional views illustrating a manufacturing process for manufacturing the display panel of fig. 1.
Description of reference numerals:
10: display panel
100: pixel array substrate
102: metal layer
102 a: metal pad
103: conductive oxide layer
104: conductive oxide pattern
104 a: a first conductive protection part
104 b: second conductive protection part
106: conductive layer
108: power supply line
110: mask and method for manufacturing the same
200: light emitting element
202: auxiliary electrode
300: annealing process
BF: buffer layer
BM: light shielding layer
BML: light-shielding material
BP1, BP2, BP3, BP 4: insulating layer
CH: channel region
D: drain electrode
DR: drain region
E1: a first electrode
E2: second electrode
G: grid electrode
GI: gate insulating layer
ILD: interlayer insulating layer
LDR: lightly doped drain region
LSR: lightly doped source region
OP1, OP 2: opening of the container
S: source electrode
SB: substrate
SC: semiconductor pattern
SR: source region
T: active component
PL1, PL2, PL 3: planarization layer
PR: layer of photoresist material
PR 1: photoresist pattern
V1, V2, V3: through hole
Detailed Description
Fig. 1 is a schematic cross-sectional view of a display panel 10 according to an embodiment of the invention. The display panel 10 includes a pixel array substrate 100 and a light emitting device 200. The pixel array substrate 100 includes a substrate SB, an active device T, a planarization layer PL1, a plurality of metal pads 102a, and a plurality of conductive oxide patterns 104. The substrate SB may be made of glass, quartz, organic polymer, opaque/reflective material (e.g., conductive material, metal, wafer, ceramic, or other suitable material) or other suitable material. If a conductive material or metal is used, an insulating layer (not shown) is formed over the substrate SB to prevent shorting.
In the embodiment, the pixel array substrate 100 may include a buffer layer BF on the substrate SB, the buffer layer BF includes a water blocking gas barrier layer, and may have a single-layer or multi-layer structure. The material of the buffer layer BF may include, for example, silicon oxide, silicon nitride, or a combination thereof.
The active device T is located on the substrate SB and has a gate G, a source S, a drain D, a semiconductor pattern SC, and a gate insulating layer GI. In this embodiment, the semiconductor pattern SC may include a source region SR, a lightly doped source region LSR, a channel region CH, a lightly doped drain region LDR and a drain region DR, the lightly doped source region LSR is located between the source region SR and the channel region CH, the lightly doped drain region LDR is located between the channel region CH and the drain region DR, and the gate G overlaps the channel region CH of the semiconductor pattern SC, but the invention is not limited thereto. According to other embodiments, the semiconductor pattern SC may include only the source region SR, the channel region CH, and the drain region DR.
The pixel array substrate 100 may include an interlayer insulating layer ILD on the gate G and having a plurality of vias V1, and the source S and the drain D are electrically connected to the source region SR and the drain region DR of the semiconductor pattern SC through the vias V1, respectively.
The pixel array substrate 100 may include a planarization layer PL1, an insulating layer BP1, and a conductive layer 106 sequentially disposed on the source electrode S, the drain electrode D, and the interlayer insulating layer ILD. The conductive layer 106 is electrically connected to the drain D through the via V2 in the planarization layer PLD1 and the insulating layer BP 1.
The pixel array substrate 100 may include an insulating layer BP2, a planarization layer PL2 and an insulating layer BP3 sequentially disposed on the insulating layer BP1 and the conductive layer 106. The metal pad 102a is disposed on the insulating layer BP2, the planarization layer PL2 and the insulating layer BP3, and is electrically connected to the conductive layer 106 through the via hole V3 in the insulating layer BP2, the planarization layer PL2 and the insulating layer BP3, so that the drain D of the active device T is electrically connected to one of the metal pads 102 a.
The conductive oxide pattern 104 has a plurality of first conductive protection portions 104a located on each metal pad 102a, each first conductive protection portion 104a has an opening OP1, and the opening OP1 overlaps the top surface of each metal pad 102 a. The light emitting device 200 is disposed on the pixel array substrate 100, and the light emitting device 200 is electrically connected to each metal pad 102a through the opening OP1 of each first conductive protection portion 104 a. Each of the first conductive protection portions 104a has high density, so as to protect the metal pad 102a from being oxidized in a high temperature process. For example, in the embodiment where the material of the metal pad 102a is copper (Cu), the metal pad 102a can be prevented from being changed into copper oxide (CuO) in a high temperature processx). In the present embodiment, each first conductive protection portion 104a and the metalThe pads 102a are defined in the same mask process, so that the embodiment can save at least one mask process, thereby saving the cost. In the present embodiment, the light emitting device 200 is, for example, an inorganic light emitting diode device, such as but not limited to: micro light emitting diodes (micro LEDs), sub-millimeter light emitting diodes (mini LEDs), or other size inorganic light emitting diodes.
Since each first conductive protection portion 104a and each metal pad 102a are defined in the same mask process, each first conductive protection portion 104a and each metal pad 102a have the same outer profile. The conductive oxide pattern 104 is made of Indium Zinc Oxide (IZO), which has high density as described above and can protect the metal pad 102a from being oxidized in a high temperature process. And the polycrystallization temperature of the indium zinc oxide is more than 400 ℃, so the indium zinc oxide is not easy to polycrystallize in a high-temperature process and has good stability. In the present embodiment, the material of the conductive oxide pattern 104 is not Indium Tin Oxide (ITO), because the polycrystallization temperature of ITO is lower than that of indium zinc oxide, so that ITO is easily polycrystallized in a high temperature process.
The pixel array substrate 100 further includes an insulating layer BP4, wherein the insulating layer BP4 is disposed on the planarization layer PL2, and the insulating layer BP4 extends from the sidewall of each metal pad 102a to cover the sidewall and the top surface of each first conductive protection portion 104a, so as to prevent external moisture or oxygen from entering each metal pad 102a and each first conductive protection portion 104 a.
The pixel array substrate 100 further includes a power supply line 108. The power supply line 108 is disposed on the insulating layer BP4, and the conductive oxide pattern 104 further has a second conductive protection portion 104b, and the second conductive protection portion 104b covers the power supply line 108. In the present embodiment, the second conductive protection portion 104b and the power supply line 108 are defined in the same mask process, so that the second conductive protection portion 104b and the power supply line 108 have the same outer contour.
The pixel array substrate 100 further includes a light-shielding layer BM. The light-shielding layer BM is located on the second conductive protection portion 104b and covers the power supply line 108 and the second conductive protection portion 104 b. In the present embodiment, the power supply line 108 and the second conductive protection portion 104b have a mesh structure (mesh), for example. In the embodiment, the metal pad 102a and the power supply line 108 are made of copper, which has a low resistance, so that the rc load of the power supply line 108 can be reduced. In the embodiment, the auxiliary electrode 202 is further disposed between the light emitting device 200 and the pixel array substrate 100, the material of the auxiliary electrode 202 may be solder paste (solder paste), and since copper and tin may form an Interfacial Metal Compound (IMC), the auxiliary electrode 202 may stably fix the light emitting device 200 on the pixel array substrate 100. Since the copper has high reflectivity, the light emitted by the light-emitting element 200 or the ambient light from the outside can be absorbed by the light-shielding layer BM if the light-shielding layer BM is disposed on the second conductive protection portion 104b and covers the power supply line 108 and the second conductive protection portion 104b, so that the display panel 10 can provide good display quality. The light-shielding layer BM is, for example, a black matrix (black matrix). In addition, in the present embodiment, the material of the second conductive protection portion 104b is indium zinc oxide, which is transparent and has a low reflectivity, and is not easy to reflect light (e.g., light emitted by the light emitting device 200 or ambient light from the outside) to affect the display quality.
Fig. 2 to 13 are schematic cross-sectional views illustrating a manufacturing process for manufacturing the display panel 10 of fig. 1. Referring to fig. 2, first, an active device T is formed on a substrate SB.
In this embodiment, the buffer layer BF may be formed on the substrate SB before the active device T is formed. The buffer layer BF includes, for example, a water-blocking gas barrier layer, and may have a single-layer or multi-layer structure. The material of the buffer layer BF may include, for example, silicon oxide, silicon nitride, or a combination thereof.
The method of forming the active device T may include the following steps. A semiconductor pattern SC, a gate insulating layer GI, a gate G, an interlayer insulating layer ILD, a source S and a drain D are sequentially formed on the buffer layer BF. As described above, the semiconductor pattern SC may include the source region SR, the lightly doped source region LSR, the channel region CH, the lightly doped drain region LDR, and the drain region DR formed by an ion doping process using the gate G as a mask.
The gate G overlaps the channel region CH in the normal direction of the substrate SB. The source S is electrically connected to the source region SR through a via V1 formed in the gate insulating layer GI and the interlayer insulating layer ILD, and the drain D is electrically connected to the drain D through a via V2 formed in the gate insulating layer GI and the interlayer insulating layer ILD.
In this embodiment, the semiconductor pattern SC, the gate insulating layer GI, the gate G, the interlayer insulating layer ILD, the source S and the drain D may be respectively implemented by any semiconductor layer, any gate insulating layer, any gate, any interlayer insulating layer, any source and any drain for the display panel 10, which are well known to those skilled in the art, and thus the material and the forming method of the semiconductor layer SC, the gate insulating layer GI, the gate G, the interlayer insulating layer ILD, the source S and the drain D are not described herein again.
In the present embodiment, the active device T may be any Thin Film Transistor known to those skilled in the art, such as a Low Temperature polysilicon Thin Film Transistor (LTPS TFT), an Amorphous Silicon Thin Film Transistor (a-Si TFT), a microcrystalline Silicon Thin Film Transistor (micro-Si TFT) or a Metal Oxide Transistor (Metal Oxide Transistor). In addition, in the present embodiment, the active device T belongs to a top gate thin film transistor, but the invention is not limited thereto. In other embodiments, the active device T may belong to a bottom gate thin film transistor.
Next, referring to fig. 3, a planarization layer PL1, an insulating layer BP1, a conductive layer 106, an insulating layer BP2, a planarization layer PL2, and an insulating layer BP3 are sequentially formed on the drain D. The conductive layer 106 is electrically connected to the drain D through a via V2 formed in the planarization layer PL1 and the insulating layer BP 1. The planarization layer PL2 and the insulation layer BP2 have a plurality of vias V3, and the via V3 exposes a portion of the conductive layer 106.
Referring to fig. 4, a metal layer 102 is formed on the insulating layer BP3 such that the metal layer 102 fills each via hole V3. In the present embodiment, the conductive layer 106 and the metal layer 102 are low resistance materials, such as copper (Cu), which can provide low resistance capacitive load.
Referring to fig. 5, a conductive oxide layer 103 is formed on the metal layer 102. In the present embodiment, the conductive oxide layer 103 is made of Indium Zinc Oxide (IZO).
Referring to fig. 6, a photoresist material layer PR is formed on the conductive oxide layer 103.
Referring to fig. 7, the photoresist material layer PR is defined by a mask 110 to form a plurality of photoresist patterns PR 1. Such as a process of exposing and developing the photoresist material layer PR through the mask 110.
Referring to fig. 8, the conductive oxide layer 103 is patterned using the photoresist pattern PR1 as a mask to form a plurality of conductive oxide patterns 104 and expose the metal layer 102 not covered by the conductive oxide patterns 104.
Referring to fig. 9, the metal layer 102 is patterned by using the photoresist pattern PR1 as a mask to form a plurality of metal pads 102a and power supply lines 108, wherein the conductive oxide pattern 104 has a plurality of first conductive protection portions 104a respectively located on the metal pads 102a and includes second conductive protection portions 104b located on the power supply lines 108. Next, the photoresist pattern PR1 is removed with a stripper photoresist (stripper).
Referring to fig. 10, an insulating layer BP4 is formed on each of the first conductive protection portion 104a and the second conductive protection portion 104b, and the insulating layer BP4 covers a portion of the insulating layer BP 3. Next, a planarization layer PL3 is formed on the insulating layer BP4, and the planarization layer PL3 exposes each of the first conductive protection portions 104a and covers the second conductive protection portion 104 b. Next, a light-shielding material BML was formed on the planarization layer PL 3. And the light blocking material BML covers the planarization layer PL3, the insulating layer BP4, the second conductive protection portion 104b, and the power supply line 108. The insulating layer BP4 extends from the sidewall of each metal pad 102a to the sidewall and the top surface covering each first conductive protection portion 104a, and the insulating layer BP4 also extends from the sidewall of the power supply line 108 to the sidewall and the top surface covering the second conductive protection portion 104 b. The insulating layer BP4 has a plurality of openings OP2, each opening OP2 corresponds to each first conductive protection portion 104a, in other words, each opening OP2 exposes a portion of the top surface of each first conductive protection portion 104 a.
Referring to fig. 11, after forming the light-shielding material BML, an annealing process 300 is performed to cure the light-shielding material BML to form the light-shielding layer BM. The annealing process 300 is a high temperature process, for example, the temperature of the annealing process 300 is between 200 ℃ and 250 ℃.
Referring to fig. 12, each first conductive protection portion 104a is partially removed, so that each first conductive protection portion 104a has an opening OP1 exposing a top surface of each metal pad 102 a. For example, partially removing each first conductive protection portion 104a is to etch the first conductive protection portion 104a that is not protected (e.g., covered) by the insulation layer BP4 using the insulation layer BP4 as a mask (hard mask). The method has the advantage of cost saving because no additional mask is needed. Since the annealing process 300 is performed before the first conductive protection portions 104a are partially removed, the first conductive protection portions 104a completely cover the metal pads 102a during the annealing process 300, so that the metal pads are prevented from being oxidized during the annealing process 300. Here, the pixel array substrate 100 according to an embodiment of the invention is substantially completed.
Referring to fig. 13, a light emitting device 200 is disposed on each of the metal pads 102a, wherein the light emitting device 200 has a first electrode E1 and a second electrode E2, the first electrode E1 is electrically connected to one of the metal pads 102a, and the second electrode E2 is electrically connected to the other of the metal pads 102 a. The light emitting device 200 is electrically connected to each metal pad 102a through the opening OP1 of each first conductive protection portion 104 a.
In the present embodiment, before the light emitting device 200 is disposed, a plurality of auxiliary electrodes 202 are formed on the metal pads 102 a. The first electrode E1 and the second electrode E2 of the light emitting device 200 can be electrically connected to each metal pad 102a through the auxiliary electrode 202. The material of the first electrode E1 and the second electrode E2 includes a metal (e.g., chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or an alloy thereof). As mentioned above, in the present embodiment, the material of the auxiliary electrode 202 may be solder paste (solder paste), and an Interfacial Metal Compound (IMC) may be formed with the metal pad 102a, so that the light emitting device 200 is stably fixed on the pixel array substrate 100.
In summary, in the display panel and the manufacturing method thereof according to the embodiment of the invention, the conductive oxide pattern has a plurality of first conductive protection portions located on each metal pad, each first conductive protection portion has an opening, and the opening overlaps the top surface of each metal pad. The light-emitting element is positioned on the pixel array substrate and is electrically connected with the metal connecting pads through the openings of the first conductive protection parts. Each first conductive protection part has high density so as to protect the metal connecting pad from being oxidized in a high-temperature process. In addition, in the present embodiment, each of the first conductive protection portions and the metal pads are defined in the same mask process, so that the present embodiment can save at least one mask process, thereby saving the cost.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. A display panel, comprising:
a pixel array substrate, comprising:
a substrate;
an active element located on the substrate and having a drain;
a planar layer on the active device;
a plurality of metal pads located on the planarization layer, wherein the drain of the active device is electrically connected to one of the metal pads; and
a plurality of conductive oxide patterns having a plurality of first conductive protection portions respectively located on the metal pads, wherein each first conductive protection portion has an opening overlapping the top surface of each metal pad; and
and the light-emitting element is positioned on the pixel array substrate, and is electrically connected with each metal pad through the opening of each first conductive protection part.
2. The display panel of claim 1, wherein the conductive oxide patterns are made of indium zinc oxide.
3. The display panel of claim 1, wherein the pixel array substrate further comprises:
and a power supply line on the planar layer, wherein the conductive oxide patterns further have a second conductive protection portion covering the power supply line.
4. The display panel of claim 3, wherein each of the first conductive protection portions and each of the metal pads have a uniform outer profile, and the second conductive protection portions and the power supply lines have a uniform outer profile.
5. The display panel of claim 3, wherein the pixel array substrate further comprises:
a shading layer located on the second conductive protection part and covering the power supply line and the second conductive protection part.
6. The display panel of claim 1, further comprising:
and the insulating layer is positioned on the flat layer, wherein the insulating layer extends from the side wall of each metal connecting pad to the side wall and the top surface covering each first conductive protection part.
7. A manufacturing method of a display panel comprises the following steps:
forming an active device on a substrate, the active device including a drain;
forming a flat layer on the drain electrode, wherein the flat layer is provided with a plurality of through holes;
forming a metal layer on the flat layer to fill the metal layer into each through hole;
forming a conductive oxide layer on the metal layer;
forming a photoresist material layer on the conductive oxide layer;
defining the photoresist material layer with a mask to form a plurality of photoresist patterns;
patterning the conductive oxide layer using the photoresist patterns as a mask to form a plurality of conductive oxide patterns;
patterning the metal layer by using the photoresist patterns as a mask to form a plurality of metal pads, wherein the conductive oxide patterns comprise a plurality of first conductive protection parts respectively positioned on the metal pads;
partially removing each first conductive protection part to enable each first conductive protection part to be provided with an opening to expose the top surface of each metal pad; and
and arranging a light-emitting element on each metal pad, wherein the light-emitting element is provided with a first electrode which is electrically connected with one of the metal pads.
8. The method of manufacturing of claim 7, further comprising:
before partially removing each first conductive protection portion, forming an insulating layer on each first conductive protection portion, wherein the insulating layer extends from the sidewall of each metal pad to cover the sidewall and the top surface of each first conductive protection portion.
9. The method of manufacturing of claim 7, further comprising:
forming a light-shielding material on the flat layer; and
before partially removing each first conductive protection part, an annealing process is carried out to solidify the shading material so as to form a shading layer.
10. The method of claim 7, wherein the conductive oxide layer is indium zinc oxide.
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| TW109146555A TWI759041B (en) | 2020-12-28 | 2020-12-28 | Display panel and manufacturing method thereof |
| TW109146555 | 2020-12-28 |
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| CN114864620A (en) * | 2021-12-30 | 2022-08-05 | 友达光电股份有限公司 | Light-emitting element, light-emitting module, display device, and method for manufacturing display device |
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| TW202230000A (en) | 2022-08-01 |
| CN113838870B (en) | 2023-04-18 |
| TWI759041B (en) | 2022-03-21 |
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