CN113193012A - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN113193012A CN113193012A CN202110395496.7A CN202110395496A CN113193012A CN 113193012 A CN113193012 A CN 113193012A CN 202110395496 A CN202110395496 A CN 202110395496A CN 113193012 A CN113193012 A CN 113193012A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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Abstract
本发明提供了一种阵列基板及其制备方法、显示装置。所述阵列基板包括薄膜晶体管结构层、第一金属层、钝化层以及第二金属层。所述第一金属层设于所述薄膜晶体管结构层上。所述钝化层覆盖所述薄膜晶体管结构层和所述第一金属层。所述第二金属层设于所述钝化层远离所述第一金属层的一表面上，并与所述第一金属层电连接。
The invention provides an array substrate, a preparation method thereof, and a display device. The array substrate includes a thin film transistor structure layer, a first metal layer, a passivation layer and a second metal layer. The first metal layer is disposed on the thin film transistor structure layer. The passivation layer covers the thin film transistor structure layer and the first metal layer. The second metal layer is disposed on a surface of the passivation layer away from the first metal layer, and is electrically connected to the first metal layer.
Description
Technical Field
The invention relates to the field of display equipment, in particular to an array substrate, a preparation method of the array substrate and a display device.
Background
An Organic Light Emitting diode Display (OLED) has many advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of nearly 180 °, a wide temperature range, flexible Display, large-area full color Display, and the like, and is considered as a Display device with the most potential for development.
In order to reduce the wiring resistance, copper is usually selected as the wiring material for the source, drain and gate of the thin film transistor in the large-sized OLED backplane. However, copper has poor stability and is easily oxidized and corroded when exposed to external environment. When copper is used as the main material of the connecting trace in the bonding region, it is easily corroded by the etching solution used in the subsequent process of the array substrate, which affects the stability.
Disclosure of Invention
The invention aims to provide an array substrate, a preparation method thereof and a display device, and aims to solve the technical problems that in the prior art, connecting wires in a binding area are easily corroded by etching liquid adopted in the subsequent processing of the array substrate and easily oxidized and deteriorated.
In order to achieve the above object, the present invention provides an array substrate having a display area and a bonding area connected to the display area. The array substrate comprises a thin film transistor structure layer, a first metal layer, a passivation layer and a second metal layer.
The thin film transistor structure layer is positioned in the display area and extends to the binding area; and a source electrode is arranged at the top of the thin film transistor structure layer. The first metal layer is arranged on the thin film transistor structure layer in the binding region. The passivation layer covers the thin film transistor structure layer and the first metal layer. The second metal layer is located in the binding region and is arranged on one surface, far away from the first metal layer, of the passivation layer, the protruding portion of the bottom surface of the second metal layer penetrates through the passivation layer and is electrically connected with the first metal layer, and the second metal layer is made of corrosion-resistant metal or corrosion-resistant metal oxide.
Further, the array substrate further comprises a third metal layer. The third metal layer is positioned in the display area and arranged on one surface of the passivation layer far away from the first metal layer, and the third metal layer penetrates through the passivation layer and is electrically connected with the source electrode.
Further, the array substrate further comprises a flat layer, a pixel electrode and a pixel defining layer. The flat layer is arranged on the passivation layer and covers the tops of the second metal layer, the thin film transistor structure layer and the third metal layer. The pixel electrode is arranged on the flat layer, and the protruding part at the bottom of the pixel electrode penetrates through the flat layer and is electrically connected with the third metal layer. The pixel defining layer is disposed on the planarization layer.
Further, the array substrate further comprises a first through hole, a second through hole and a third through hole. The first through hole is arranged opposite to the pixel electrode and penetrates through the pixel defining layer. The second through hole is arranged opposite to the second metal layer and penetrates through the pixel limiting layer. The third through hole is opposite to the second metal layer and penetrates through the flat layer.
Further, the first metal layer is copper; the second metal layer comprises at least one of indium tin oxide, molybdenum and titanium.
The invention also provides a preparation method of the array substrate, which comprises the following steps:
preparing a thin film transistor structure layer on a substrate, wherein the thin film transistor structure layer comprises a source electrode; in the process of preparing the source electrode, simultaneously preparing a first metal layer on the upper surface of the thin film transistor structure layer; preparing a passivation layer on the thin film transistor structure layer and the first metal layer; etching more than two through holes on the passivation layer, penetrating through the passivation layer, wherein each through hole is arranged opposite to the first metal layer or the source electrode; and preparing a second metal layer on the passivation layer, wherein the protruding part on the bottom surface of the second metal layer penetrates through a through hole and is electrically connected with the first metal layer.
Further, the preparation method of the array substrate further comprises the following steps: forming a third metal layer simultaneously with forming the second metal layer on the passivation layer.
Further, the preparation method of the array substrate further comprises the following steps: forming a planarization layer on the passivation layer; forming a pixel electrode on the planarization layer; forming a pixel defining layer on the planarization layer and the pixel electrode.
Further, the preparation method of the array substrate further comprises the following steps: etching a third through hole in the flat layer; a first via and a second via are etched in the pixel defining layer.
The invention also provides a display device, which comprises the array substrate.
The invention has the advantages that:
according to the array substrate and the preparation method thereof, the second metal layer with high reliability is additionally arranged above the first metal layer of the binding region, the first metal layer is protected by the second metal layer, etching liquid is prevented from corroding the first metal layer in subsequent processing procedures, and the stability of the array substrate is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic view of a layered structure of an array substrate according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a layered structure of an array substrate according to an embodiment of the invention;
FIG. 3 is a schematic flow chart illustrating a method for fabricating an array substrate according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a layered structure of the array substrate after step S10 according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a layered structure of the array substrate after step S20 according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a layered structure of the array substrate after step S30 according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a layered structure of the array substrate after step S40 according to an embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a layered structure of the array substrate after step S50 according to an embodiment of the present invention.
The components in the figures are represented as follows:
an array substrate 100;
a display area 101; a binding region 102;
a thin film transistor structure layer 10; a substrate 11;
a light-shielding layer 12; a buffer layer 13;
an active layer 14; a gate insulating layer 15;
a source electrode 18; a drain electrode 19;
a first metal layer 20; a passivation layer 30;
a second metal layer 40; a third metal layer 50;
a planarization layer 60; a pixel electrode 70;
a reflective layer 71; a light-transmitting layer 72;
a pixel defining layer 80; a first through hole 81;
a second through hole 82; a third through hole 61;
a via 31; and a connecting hole 62.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the invention also provides a display device, and the display device comprises an array substrate 100, an organic light emitting device and other display devices. The display device can be any display device with a display function, such as a mobile phone, a notebook computer, a television and the like.
As shown in fig. 1, the array substrate 100 has a display area 101 and a bonding area 102 connected to the display area 101, where the display area 101 is used for displaying a picture, and the bonding area 102 is used for connecting a flip-chip film or other components. The array substrate 100 includes a thin film transistor structure layer 10, a first metal layer 20, a passivation layer 30, a second metal layer 40, and a third metal layer 50.
As shown in fig. 2, the thin film transistor structure layer 10 has an insulating material layer and a conductive material layer therein. The insulating material layer includes a substrate 11, a buffer layer 13, a gate insulating layer 15, and an interlayer dielectric layer 17, and the conductive material layer includes a light shielding layer 12, an active layer 14, a gate electrode 16, a source electrode 18, and a drain electrode 19. The substrate 11, the buffer layer 13 and the interlayer dielectric layer 17 extend from the display region 101 to the bonding region 102 of the array substrate 100, and the conductive material layer is located in the display region 101.
The substrate 11 is an insulating substrate, such as a glass substrate or a quartz substrate. The light-shielding layer 12 is disposed on one surface of the substrate 11, and the buffer layer 13 is disposed on the substrate 11 and covers the light-shielding layer 12. The active layer 14 is disposed on a surface of the buffer layer 13 away from the light-shielding layer 12, and is disposed opposite to the light-shielding layer 12. Wherein the active layer 14 has two connections therein and a channel region therebetween. The gate insulating layer 15 is disposed on a surface of the active layer 14 away from the buffer layer 13, and is disposed opposite to the channel region of the active layer 14. The gate electrode 16 is disposed on a surface of the gate insulating layer 15 away from the active layer 14. The interlayer dielectric layer 17 is disposed on the buffer layer 13 and covers the active layer 14, the gate insulating layer 15, and the gate electrode 16.
The source electrode 18 and the drain electrode 19 are both arranged on a surface of the interlayer dielectric layer 17 far away from the gate electrode 16, and the source electrode 18 and the drain electrode 19 respectively correspond to two ends of the active layer 14. The bottom surface of the source electrode 18 has two protruding portions, one of which is electrically connected to a connection terminal of the active layer 14 through the interlayer dielectric layer 17, and the other of which is electrically connected to the light shielding layer 12 through the interlayer dielectric layer 17 and the buffer layer 13. The bottom surface of the drain electrode 19 has a protrusion, which protrudes through the interlayer dielectric layer 17 and is electrically connected to the other connection terminal of the active layer 14.
The light shielding layer 12 is generally made of an opaque metal material, and is used for shielding the active layer 14, preventing the light from irradiating to affect the operation of the active layer 14, and preventing the tft from generating a threshold voltage negative drift phenomenon. Meanwhile, the source 18 of the thin film transistor structure layer 10 is electrically connected to the light-shielding layer 12, so that a stable voltage can be generated on the light-shielding layer 12, thereby avoiding a floating gate effect, and effectively improving the working stability of the array substrate 100. The buffer layer 13, the gate insulating layer 15, and the interlayer dielectric layer 17 are made of inorganic materials such as silicon oxide and silicon nitride. The buffer layer 13 is used for buffering impact force on the display panel device in the production and transportation process, and insulating and isolating the light shielding layer 12 from the remote areas. The gate insulating layer 15 and the interlayer dielectric layer 17 are used for insulating and protecting conductive wires such as a gate 16, a source 18, a drain 19 and the like in the display panel, and preventing short circuit between the wires.
The thin film transistor structure layer 10 generates an electric field by applying a current voltage to the gate electrode 16, and the electric field causes the channel region of the active layer 14 to generate induced charges, so as to change the thickness of the conductive channel, thereby achieving the purpose of controlling the current of the source electrode 18 and the drain electrode 19, and realizing the driving of each sub-pixel in the display device.
As shown in fig. 1, the first metal layer 20 is disposed on the same layer as the top of the source 18 and the drain 19 in the thin film transistor structure layer 10, and is disposed on the interlayer dielectric layer 17 in the bonding region 102. The first metal layer 20 and the source electrode 18 and the drain electrode 19 in the thin film transistor structure layer 10 are made of the same metal material, which is typically copper. The first metal layer 20 is used as a bonding trace for electrically connecting with components such as a chip on film, a flexible circuit board, etc., and transmitting a control signal sent by an IC chip on the chip on film or the flexible circuit board.
The passivation layer 30 is disposed on the interlayer dielectric layer 17 and covers the source electrode 18, the drain electrode 19 and the first metal layer 20. The passivation layer 30 is generally made of an insulating inorganic material, and protects the source electrode 18, the drain electrode 19, and the first metal layer 20 with passivation.
The second metal layer 40 is disposed on a surface of the passivation layer 30 away from the first metal layer 20, is located in the bonding region 102, and is disposed opposite to the first metal layer 20. The bottom surface of the second metal layer 40 has a protrusion, which penetrates through the passivation layer 30 and is electrically connected to the first metal layer 20. The width of the first metal layer 20 is less than or equal to the width of the second metal layer 40, and an orthographic projection of the first metal layer 20 on the thin film transistor structure layer 10 completely falls into an orthographic projection of the second metal layer 40 on the thin film transistor structure layer 10. The second metal layer 40 is made of a simple metal substance, an alloy or a metal oxide, which has high corrosion resistance, stability and reliability and excellent conductivity, preferably, the simple metal substance is molybdenum, titanium or aluminum, the alloy is a molybdenum alloy, a titanium alloy, an iridium alloy or a nickel alloy, and the metal oxide is indium tin oxide, titanium oxide or ferroferric oxide. The second metal layer 40 is used to protect the first metal layer 20, prevent etching solution used in the manufacturing process of the array substrate 100 from corroding the first metal layer 20, and improve the stability of the first metal layer 20.
The third metal layer 50 is also disposed on a surface of the passivation layer 30 away from the source electrode 18, and is located in the display region 101 and opposite to the source electrode 18. The bottom surface of the third metal layer 50 is electrically connected to the source electrode 18 through the passivation layer 30. The third metal layer 50 and the second metal layer 40 are made of the same material. The third metal layer 50 is used to protect the source electrode 18, prevent etching solution used in the manufacturing process of the array substrate 100 from corroding the source electrode 18, and improve the stability of routing of the source electrode 18.
The array substrate 100 further includes a planarization layer 60, a pixel electrode 70, and a pixel defining layer 80.
The planarization layer 60 is disposed on the top surface of the passivation layer 30 and covers the second metal layer 40 and the third metal layer 50. The planarization layer 60 is made of an insulating inorganic material, and is used for planarizing the surface of the array substrate 100 to protect the second metal layer 40 and the third metal layer 50 in an insulating manner.
The pixel electrode 70 is disposed on a surface of the planarization layer 60 away from the third metal layer 50, is located in the display area 101, and has a bottom portion passing through the planarization layer 60 and electrically connected to the third metal layer 50. As shown in fig. 2, the pixel electrode 70 has a reflective layer 71 and a transparent layer 72.
The reflective layer 71 is disposed on the top surface of the flat layer 60, and has a protruding portion at the bottom end thereof, wherein the protruding portion penetrates through the flat layer 60 and is electrically connected to the third metal layer 50. The reflective layer 71 is made of conductive metal with high light reflectivity, and the conductive metal may be silver, tin, aluminum, or the like. The reflective layer 71 is used for reflecting light emitted by the organic light emitting device, reducing light loss and improving display brightness.
The transparent layer 72 is disposed on a surface of the reflective layer 71 away from the planarization layer 60, and is electrically connected to the reflective layer 71. The light-transmitting layer 72 is a transparent conductive film made of metal oxide, and the metal oxide may be indium tin oxide.
The pixel defining layer 80 is disposed on the planarization layer 60 and covers the pixel electrode 70. As shown in fig. 2, the pixel defining layer 80 has a first through hole 81 therein, the first through hole 81 is disposed corresponding to the pixel electrode 70, and the first through hole 81 penetrates through the pixel defining layer 80 to the surface of the pixel electrode 70, so that the surface of the pixel electrode 70 is exposed. The organic light emitting device may be disposed on the top surface of the pixel electrode 70 in the first via hole 81 and electrically connected to the pixel electrode 70. The pixel defining layer 80 is used to define the size of a pixel, i.e., the size of an organic light emitting device placed in the first through hole 81 by controlling the size of the first through hole 81 thereof.
The pixel electrode 70 is electrically connected with the source/drain electrode 19 layer through the third metal layer 50 to obtain electric energy, and the electric energy is transmitted to the organic light emitting device, and the organic light emitting device converts the electric energy into light energy to realize light emitting display.
As shown in fig. 2, the pixel defining layer 80 further has a second through hole 82 therein, the second through hole 82 penetrates through the pixel defining layer 80, and the second through hole 82 is disposed opposite to the second metal layer 40. The planar layer 60 has a third through hole 61 therein, the third through hole 61 penetrates through the planar layer 60, and the third through hole 61 is also disposed opposite to the second metal layer 40. As shown in fig. 1, the second through hole 82 and the third through hole 61 are connected to and penetrate the top surface of the second metal layer 40, so that the top surface of the second metal layer 40 is exposed, which is convenient for the second metal layer 40 to be lapped with components such as a chip on film.
In the array substrate 100 provided in the embodiment of the present invention, a second metal layer 40 made of a metal or a conductive metal oxide with high corrosion resistance and stability is additionally disposed above the first metal layer 20 in the bonding region 102, and the second metal layer 40 is electrically connected to the first metal layer 20, so that the first metal layer 20 is protected while the circuit connection is not affected, corrosion of the first metal layer 20 by an etching solution in a subsequent process is prevented, a rejection rate in a production process is reduced, and stability of the array substrate 100 is improved.
The embodiment of the present invention further provides a method for manufacturing an array substrate 100, wherein the flow of the manufacturing method is shown in fig. 3, and the method includes the following steps:
step S10) preparing the thin film transistor structure layer 10 and the first metal layer 20: a light shielding layer 12, a buffer layer 13, an active layer 14, a gate insulating layer 15, a gate 16, an interlayer dielectric layer 17, a source 18, and a drain 19 are sequentially prepared on a substrate 11 by a thin film transistor manufacturing process, the first metal layer 20 is etched on the interlayer dielectric layer 17 of the bonding region 102 while the source 18 and the drain 19 are prepared, and after the completion, the layered structure of the array substrate 100 is as shown in fig. 4.
Step S20) preparing the passivation layer 30: depositing a layer of inorganic material on the first metal layer 20 and the thin film transistor structure layer 10 to form the passivation layer 30. The passivation layer 30 is patterned by exposure, development, etching, etc. to form a plurality of vias 31 penetrating through the passivation layer 30 as shown in fig. 5. The via hole 31 is disposed opposite to the source 18 of the thin film transistor structure layer 10 or opposite to the first metal layer 20.
Step S30) preparing the second metal layer 40 and the third metal layer 50: a layer of metal material is prepared on a surface of the passivation layer 30 away from the thin film transistor structure layer 10, and the metal material fills each via hole 31 in the passivation layer 30. The metallic material layer is patterned to form a second metallic layer 40 connected to the first metallic layer 20 and a third metallic layer 50 connected to the source electrode 18 as described in fig. 6. Wherein the protrusion of the second metal layer 40 is formed in the via hole 31 disposed opposite to the first metal layer 20.
Step S40) preparing the planarization layer 60: depositing a layer of inorganic material on the top surface of the passivation layer 30 to form the planarization layer 60, wherein the planarization layer 60 covers the second metal layer 40 and the third metal layer 50. The planarization layer 60 is patterned by exposure, development, etching, and the like to form a third via hole 61 disposed opposite to the second metal layer 40 and a connection hole 62 disposed opposite to the third metal layer 50 as shown in fig. 7.
Step S50) preparing the pixel electrode 70: a layer of metallic material is applied over the planar layer 60 and fills the connection holes 62 in the planar layer 60. Patterning the metal material layer to form a reflection layer 71, wherein the protrusion of the reflection layer 71 is formed in the connection hole 62. A metal oxide layer is formed on the reflective layer 71, and the metal oxide layer is patterned to form a light-transmitting layer 72. As shown in fig. 8, the reflective layer 71 and the light-transmissive layer 72 form the pixel electrode 70 in combination.
Step S60) preparing the pixel defining layer 80: a layer of inorganic material is deposited on the top surface of the planarization layer 60 to form the pixel defining layer 80, and the pixel defining layer 80 covers the pixel electrode 70. Patterning the planarization layer 60 to form a first via hole 81 disposed opposite to the pixel electrode 70 and a second via hole 82 disposed opposite to the third via hole 61 as shown in fig. 1, thereby completing the preparation of the array substrate 100.
In the array substrate 100 and the method for manufacturing the same provided in the embodiments of the present invention, a second metal layer 40 made of a metal or a conductive metal oxide with high corrosion resistance and stability is additionally disposed above the first metal layer 20 in the bonding region 102, and the second metal layer 40 is electrically connected to the first metal layer 20, so that the first metal layer 20 is protected while the circuit connection is not affected, the corrosion of the first metal layer 20 by an etching solution in a subsequent process is prevented, the rejection rate in a production process is reduced, and the stability of the array substrate 100 is improved.
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| CN114420729A (en) * | 2022-01-05 | 2022-04-29 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN114823729A (en) * | 2022-04-20 | 2022-07-29 | 深圳市华星光电半导体显示技术有限公司 | Display panel and method for producing the same |
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| CN111370453A (en) * | 2020-03-18 | 2020-07-03 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN111883574A (en) * | 2020-09-02 | 2020-11-03 | 深圳市华星光电半导体显示技术有限公司 | OLED display panel and manufacturing method thereof |
| CN112420739A (en) * | 2020-11-02 | 2021-02-26 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114203750A (en) * | 2021-12-07 | 2022-03-18 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN114420729A (en) * | 2022-01-05 | 2022-04-29 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN114823729A (en) * | 2022-04-20 | 2022-07-29 | 深圳市华星光电半导体显示技术有限公司 | Display panel and method for producing the same |
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