CN114864620A - Light-emitting element, light-emitting module, display device, and method for manufacturing display device - Google Patents

Abstract

A light-emitting element includes: a first-type semiconductor pattern, a second-type semiconductor pattern, a light-emitting pattern, a first electrode, a second electrode, and a protective layer. The second type semiconductor pattern overlaps the first type semiconductor pattern and is located on the first side of the first type semiconductor pattern. The light emitting pattern is located between the first type semiconductor pattern and the second type semiconductor pattern. The first electrode is located on the second side of the first type semiconductor pattern, the second side is opposite to the first side, and the first electrode is connected to the first type semiconductor pattern. The second electrode is located on the same side of the second-type semiconductor pattern as the first-type semiconductor pattern, and is connected to the second-type semiconductor pattern. The protective layer is located on the opposite side of the second-type semiconductor pattern and the first-type semiconductor pattern, and the refractive index difference between the protective layer and the second-type semiconductor pattern is less than 1.8. In addition, a light-emitting assembly including the above-mentioned light-emitting element, a display device including the above-mentioned light-emitting element, and a manufacturing method of the display device are also proposed.

Description

Light-emitting element, light-emitting component, display device, and manufacturing method of the display device

technical field

The present invention relates to a light-emitting element, a light-emitting component including the same, a display device, and a manufacturing method of the display device.

Background technique

Micro-LEDs (micro-LEDs) are suitable for constructing pixel structures of micro-LED display devices because of their low power consumption, high brightness, high resolution, and high color saturation. Due to the extremely small size of micro-LEDs, the current method for manufacturing micro-LED display devices is to use Mass Transfer technology, that is, to use micro-electromechanical array technology to pick and place micro-LED dies to transfer a large number of micro-LED displays. The LED die is transported to the driving backplane with the pixel circuit at one time.

In order to be able to perform mass transfer, the light-emitting element must be in a suspended state. At present, silicon oxide (SiOx) is mainly used as a connecting member for suspending the light-emitting element because of its low fracture strength. However, the tie member is also formed on the surface of the light-emitting element. Since the refractive index of silicon oxide is lower than that of the semiconductor layer of the light-emitting element, the light emitted by the light-emitting element is prone to total reflection, resulting in the light extraction efficiency of the light-emitting element. efficiency, LEE) decreased.

SUMMARY OF THE INVENTION

The present invention provides a light-emitting element with improved light extraction efficiency.

The present invention provides a light-emitting assembly with improved light extraction efficiency.

The present invention provides a display device with improved light extraction efficiency.

The present invention provides a method of manufacturing a display device capable of providing a display device with improved light extraction efficiency.

An embodiment of the present invention provides a light-emitting element, including: a first-type semiconductor pattern; a second-type semiconductor pattern overlapping the first-type semiconductor pattern and located on a first side of the first-type semiconductor pattern; a light-emitting pattern located on a first side of the first-type semiconductor pattern; between the first type semiconductor pattern and the second type semiconductor pattern; the first electrode is located on the second side of the first type semiconductor pattern, the second side is opposite to the first side, and the first electrode is connected to the first type semiconductor pattern; the third Two electrodes, located on the same side of the second-type semiconductor pattern as the first-type semiconductor pattern, and connected to the second-type semiconductor pattern; and a protective layer, located on the opposite side of the second-type semiconductor pattern and the first-type semiconductor pattern , and the refractive index difference between the protective layer and the second-type semiconductor pattern is less than 1.8.

In an embodiment of the present invention, the above-mentioned protective layer has a refractive index greater than 1.46.

In an embodiment of the present invention, the protective layer includes silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, hafnium dioxide, zirconium dioxide, diamond-like carbon or amorphous carbon.

In an embodiment of the present invention, the above-mentioned second-type semiconductor pattern includes a P-type semiconductor material.

In an embodiment of the present invention, the thickness of the above-mentioned second-type semiconductor pattern is between 1 μm and 3 μm.

In an embodiment of the present invention, the thickness of the above-mentioned first-type semiconductor pattern is between 0.1 μm and 1 μm.

An embodiment of the present invention provides a light-emitting assembly, comprising: a carrier board; a plurality of support members located on the carrier board; and the above-mentioned light-emitting element suspended between the plurality of support members by a connecting member.

In an embodiment of the present invention, the above-mentioned connecting member extends from the sidewalls of the second-type semiconductor pattern, the light-emitting pattern and the first-type semiconductor pattern, and is connected to the support member.

In an embodiment of the present invention, the above-mentioned connecting member further extends on the side opposite to the protective layer on the first type semiconductor pattern and the second type semiconductor pattern, and the first electrode and the second electrode pass through the connecting member respectively The first through hole in the device is connected to the first type semiconductor pattern and the second type semiconductor pattern.

In an embodiment of the present invention, the material of the aforementioned connecting element is different from the material of the protective layer.

In an embodiment of the present invention, the refractive index of the protective layer is greater than the refractive index of the connecting member.

In an embodiment of the present invention, the above-mentioned connecting member includes silicon oxide.

In an embodiment of the present invention, the above-mentioned light-emitting component further includes a support layer located between the support member, the light-emitting element, and the carrier.

An embodiment of the present invention provides a display device, including: a circuit substrate; and the above-mentioned light-emitting element, which is located on the circuit substrate and is electrically connected to the circuit substrate.

In an embodiment of the present invention, the above-mentioned circuit substrate further includes a first pad and a second pad, wherein the first pad is electrically connected to the first electrode, and the second pad is electrically connected to the second electrode.

In an embodiment of the present invention, the above-mentioned circuit substrate further includes a switch element, and the switch element is electrically connected to the first pad or the second pad.

One embodiment of the present invention provides a method for manufacturing a display device, including: providing a growth substrate; forming a multilayer semiconductor layer on the growth substrate; forming a first sacrificial layer on the multilayer semiconductor layer; forming an interposer substrate on the first sacrificial layer layer; removing the growth substrate; patterning multiple semiconductor layers to form a semiconductor stack; forming tie members on the semiconductor stack and the interposer substrate, and the tie members have a plurality of first vias exposing the semiconductor stack ; respectively forming a first electrode and a second electrode in a plurality of first through holes; forming a plurality of support members on the connecting member, and the support members do not overlap the semiconductor stack; forming a carrier plate on the plurality of supports and the semiconductor stack removing the interposer substrate; removing a portion of the first sacrificial layer to expose the semiconductor stack; and forming a protective layer on the semiconductor stack.

In an embodiment of the present invention, the above-mentioned forming the first sacrificial layer on the multilayer semiconductor layer includes: roughening the surface of the multilayer semiconductor layer; and forming the first sacrificial layer on the roughened surface of the multilayer semiconductor layer .

In an embodiment of the present invention, forming the interposer on the first sacrificial layer includes: forming an adhesive layer on the first sacrificial layer; and forming an interposer on the adhesive layer.

In an embodiment of the present invention, the above-mentioned forming a plurality of support members on the connecting member includes: forming a second sacrificial layer on the semiconductor stack and the connecting member, and the second sacrificial layer has a plurality of second through holes , a plurality of second through holes do not overlap the semiconductor stack and expose the connecting member; and a support member is formed in the second through holes.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following examples are given and described in detail with the accompanying drawings, but are not intended to limit the present invention.

Description of drawings

FIG. 1 to FIG. 11 are partial cross-sectional schematic views of the steps of the manufacturing method of the display device 10 according to an embodiment of the present invention.

Among them, reference numerals:

10: Display device

10A: Light-emitting components

110: circuit substrate

112: Bottom plate

114: Driver circuit layer

120: Light-emitting element

BL: adhesive layer

CP: protective layer

CS: carrier board

E1: first electrode

E2: Second electrode

EL: Light Emitting Layer

EP: Glow Pattern

F1, Fs: Surface

GS: Growth Substrate

I1: buffer layer

I2: gate insulating layer

I3: Interlayer insulating layer

I4: insulating layer

IS: Interposer substrate

PC: Support

PD1, PD2: pads

PL: support layer

PR: patterned photoresist layer

RS: Surface

S1: first side

S2: Second side

SF1: first sacrificial layer

SF2: second sacrificial layer

SL1: first type semiconductor layer

SL2: second type semiconductor layer

SP1: First type semiconductor pattern

SP2: Second type semiconductor pattern

SS: Semiconductor Stack

T: switching element

TC: semiconductor layer

TD: Drain

TG: Gate

TR: tie

TS: source

t1, t2: thickness

V11, V12: first through hole

V2: second via

VA1, VA2, VA3: Through hole

VL1, VL2: Power cord

W1, W2, We: Sidewalls

Detailed ways

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. The same reference numerals refer to the same elements throughout the specification. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

It will be understood that, although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or parts shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms including "at least one" or mean "and/or" unless the content clearly dictates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the presence of stated features, regions, integers, steps, operations, elements and/or parts, but do not exclude one or more The presence or addition of other features, regions, integers, steps, operations, elements, parts and/or combinations thereof.

Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element, as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" may include an orientation of "lower" and "upper", depending on the particular orientation of the drawings. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "below" can encompass both an orientation of above and below.

"About," "approximately," or "substantially" as used herein includes the stated value and those of ordinary skill in the art, given the measurement in question and the particular amount of error associated with the measurement (ie, the limitations of the measurement system). The average within an acceptable deviation range for a specific value determined by a person. For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately", or "substantially" as used herein may select a more acceptable range of variation or standard deviation depending on optical properties, etching properties, or other properties, and may not apply to all nature.

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Thus, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and/or tolerances, are to be expected. Accordingly, the embodiments described herein should not be construed as limited to the particular shapes of regions as shown herein, but rather include deviations in shapes resulting from, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and/or nonlinear features. Additionally, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

FIG. 1 to FIG. 11 are partial cross-sectional schematic views of the steps of the manufacturing method of the display device 10 according to an embodiment of the present invention. Referring to FIG. 1 , in the process flow of the manufacturing method of the display device 10 of the present embodiment, first, a growth substrate GS is provided, and the growth substrate GS may be a sapphire (Sapphire) substrate, a gallium arsenide (GaAs) substrate, or a gallium phosphide substrate. (GaP) substrate, indium phosphide (InP) substrate, silicon carbide (SiC) substrate, gallium nitride (GaN) substrate or other substrates suitable for epitaxial process, but not limited thereto.

Next, in some embodiments, a release layer (not shown) may be formed on the surface of the growth substrate GS as required, and the release layer may facilitate subsequent removal of the growth substrate GS, and also facilitate subsequent epitaxy. crystal process. The material of the release layer is, for example, aluminum nitride (AlN).

Next, a blanket multilayer semiconductor layer is formed on the growth substrate GS and the release layer (if any). For example, the first-type semiconductor layer SL1 can be firstly formed on the growth substrate GS and the release layer (if any); then, the light-emitting layer EL can be formed on the first-type semiconductor layer SL1; then, the second-type semiconductor layer SL1 can be formed The semiconductor layer SL2 is on the light emitting layer EL. The first type semiconductor layer SL1 and the second type semiconductor layer SL2 may include II-VI group materials (eg, zinc selenide (ZnSe)) or III-V group materials (eg, gallium nitride (GaN), gallium phosphide ( GaP), Aluminum Nitride (AlN), Indium Nitride (InN), Indium Gallium Nitride (InGaN), Indium Gallium Phosphide (InGaP), Aluminum Gallium Nitride (AlGaN), Aluminum Indium Gallium Nitride (AlInGaN) or Aluminum Indium Gallium Phosphide (AlInGaP)). For example, in this embodiment, the first-type semiconductor layer SL1 is, for example, an N-type doped semiconductor layer, and the material of the N-type doped semiconductor layer is, for example, N-type aluminum indium gallium phosphide (AlInGaP), and the second-type semiconductor layer is The layer SL2 includes, for example, a P-type doped semiconductor material, and the P-type doped semiconductor material is, for example, P-type gallium phosphide (GaP), but not limited thereto. In this embodiment, the structure of the light-emitting layer EL is, for example, a multi-layer quantum well structure (Multiple Quantum Well, MQW). GaP), by designing the ratio of indium or gallium in the light-emitting layer EL, the light-emitting wavelength range of the light-emitting layer EL can be adjusted, but the present invention is not limited to this.

Next, in some embodiments, a surface treatment may be performed on the surface RS of the second type semiconductor layer SL2 as required, for example, the surface RS of the second type semiconductor layer SL2 may be roughened to facilitate the adhesion of subsequent film layers.

Next, referring to FIG. 2, a first sacrificial layer SF1 is formed on the surface of the second type semiconductor layer SL2, and then an adhesive layer BL can be formed on the first sacrificial layer SF1 as needed, and then an interposer IS is formed on the adhesive layer BL and on the first sacrificial layer SF1. In this embodiment, the interposer substrate IS may be disposed on the adhesive layer BL by means of attachment, but it is not limited thereto.

The material of the first sacrificial layer SF1 may be a material having etching selectivity with respect to silicon oxide (SiOx). For example, the first sacrificial layer SF1 may include metal, diamond-like carbon (DLC) or chemical abrasive resistant material, but is not limited thereto. In some embodiments, the material of the adhesive layer BL may be silicon oxide (SiOx), but is not limited thereto.

Next, referring to FIG. 3 , the growth substrate GS is removed to expose the first-type semiconductor layer SL1 . The manner of removing the growth substrate GS may be, for example, heat treatment or a laser lift off process, but not limited thereto.

4, the first type semiconductor layer SL1, the light emitting layer EL and the second type semiconductor layer SL2 are patterned to form the first type semiconductor pattern SP1, the light emitting pattern EP and the second type semiconductor pattern SP2, wherein, The first type semiconductor pattern SP1, the light emitting pattern EP, and the second type semiconductor pattern SP2 may constitute a semiconductor stack SS. In this embodiment, the first-type semiconductor pattern SP1 and the light-emitting pattern EP may partially overlap the second-type semiconductor pattern SP2, and part of the second-type semiconductor pattern SP2 is exposed.

Next, a tie member TR is formed on the surface Fs of the first sacrificial layer SF1, the sidewall W2 of the second type semiconductor pattern SP2, the sidewall We of the light emitting pattern EP, the sidewall W1 of the first type semiconductor pattern SP1, and the first type semiconductor pattern SP1. On the surface F1 of the semiconductor pattern SP1, the connecting member TR has first through holes V11 and V12 exposing the first type semiconductor pattern SP1 and the second type semiconductor pattern SP2 respectively. In this way, both the connecting element TR and the second-type semiconductor pattern SP2 can be attached to the surface Fs of the first sacrificial layer SF1, so that the surface of the connecting element TR and the second-type semiconductor pattern SP2 facing the first sacrificial layer SF1 can be flush. Next, the first electrode E1 and the second electrode E2 are respectively formed in the first through holes V11 and V12.

In this embodiment, the material of the connecting member TR is, for example, silicon oxide (SiOx), but is not limited thereto. The materials of the first electrode E1 and the second electrode E2 may include metals with good electrical conductivity, such as aluminum (Al), titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), chromium (Cr), etc. A metal, an alloy of the foregoing metals, or a combination or stack of the foregoing metals and/or alloys. For example, the first electrode E1 or the second electrode E2 may include metal stacks such as Ti/Au, Ti/Al/Ti/Au or Cr/Al/Ti/Pt/Au.

Next, referring to FIG. 5 , in some embodiments, a second sacrificial layer SF2 may be formed on the semiconductor stack SS, the first electrode E1 , the second electrode E2 and the connecting member TR, and the second sacrificial layer SF2 may be A plurality of second through holes V2 are formed, the orthographic projection of each second through hole V2 on the interposer substrate IS does not overlap the orthographic projection of the semiconductor stack SS on the interposer substrate IS, and the second through holes V2 can expose the tie member TR. A part of the first sacrificial layer SF1 is attached. The second sacrificial layer SF2 may include an organic material, but is not limited thereto. In some embodiments, the second through hole V2 may have an inverted trapezoid shape with an upper width and a lower width, but is not limited thereto.

Next, referring to FIG. 6 , a support PC can be formed in each of the second through holes V2 . Since the second through hole V2 can expose the tie member TR, and the second through hole V2 does not overlap the semiconductor stack SS, the support member PC can be located on the tie member TR and connected to the tie member TR, and the support member PC does not Overlapping semiconductor stacks SS. In some embodiments, the support layer PL may also be formed on the support member PC and the second sacrificial layer SF2, and the support layer PL and the support member PC may belong to the same film layer, in other words, the support layer PL may be integrally formed with the support member PC , but not limited to this. In this way, it can be ensured that the support PC and the second sacrificial layer SF2 have a flat upper surface. In some embodiments, the support member PC and/or the support layer PL may comprise a material having a certain rigidity, such as metal. In some embodiments, the support PC and/or the support layer PL may also have a multi-layer structure.

Next, the carrier CS may be formed on the support layer PL, the support member PC, the second sacrificial layer SF2, the first electrode E1, the second electrode E2 and the semiconductor stack SS. For example, the carrier CS can be attached to the surface of the support layer PL. Next, referring to FIG. 7 , after the carrier CS is formed, the interposer IS and the adhesive layer BL may be removed, for example, by means of laser lift-off, heat treatment and/or etching to remove the interposer IS and the adhesive layer BL.

Next, referring to FIG. 8 , a portion of the first sacrificial layer SF1 is removed to expose the semiconductor stack SS. For example, in this embodiment, the patterned photoresist layer PR may be formed by a thin film deposition process and a lithography process, and then a part of the first sacrificial layer that is not shielded by the patterned photoresist layer PR may be removed by an etching process SF1, thereby exposing the second-type semiconductor pattern SP2 of the semiconductor stack SS.

Next, referring to FIG. 9 , a protective layer CP is formed on the semiconductor stack SS. For example, in this embodiment, the protective layer CP can be deposited again using the patterned photoresist layer PR as a shield, so that the protective layer CP is formed on the surface of the second-type semiconductor pattern SP2 of the semiconductor stack SS. In some embodiments, the protective layer CP may also extend onto the surface of the tie member TR. The material of the protective layer CP may include, for example, silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiOx), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), diamond-like Carbon (DLC) or amorphous carbon (Amorphous Carbon), but not limited thereto.

So far, the light-emitting element 120 is formed on the carrier CS, and the light-emitting element 120 may include: a first-type semiconductor pattern SP1; a second-type semiconductor pattern SP2 overlapping the first-type semiconductor pattern SP1 and located in the first-type semiconductor pattern SP1 The first side S1 of the pattern; the light emitting pattern EP, located between the first type semiconductor pattern SP1 and the second type semiconductor pattern SP2, wherein the first type semiconductor pattern SP1, the second type semiconductor pattern SP2 and the light emitting pattern EP constitute a semiconductor stack layer SS; the first electrode E1 is located on the second side S2 of the first type semiconductor pattern SP1, the second side S2 is opposite to the first side S1, and the first electrode E1 is connected to the first type semiconductor pattern SP1; the second electrode E2, the second type semiconductor pattern SP2 is located on the same side as the first type semiconductor pattern SP1 and is connected to the second type semiconductor pattern SP2; and the protective layer CP is located on the second type semiconductor pattern SP2 and opposite to the first type semiconductor pattern SP1 side, and the refractive index difference between the protective layer CP and the second-type semiconductor pattern SP2 is less than 1.8.

In some embodiments, the thickness t1 of the first type semiconductor pattern SP1 may be between 0.1 μm and 1 μm, and the thickness t2 of the second type semiconductor pattern SP2 may be between 1 μm and 3 μm. By adjusting the thickness t1 of the first-type semiconductor pattern SP1 and the thickness t2 of the second-type semiconductor pattern SP2 within the above-mentioned ranges, the light waves emitted from the light-emitting element 120 can cause constructive interference, thereby improving the light extraction efficiency of the light-emitting element 120 ( LEE). In addition, by making the refractive index difference between the protective layer CP and the second type semiconductor pattern SP2 less than 1.8, the proportion of total reflection of the light emitted by the light emitting element 120 can also be reduced, thereby improving the light extraction efficiency (LEE) of the light emitting element 120 .

In this embodiment, the first electrode E1 and the second electrode E2 of the light emitting element 120 are located on the same side of the semiconductor stack SS, and the light emitting element 120 may be a flip chip light emitting diode. In some embodiments, the second-type semiconductor pattern SP2 of the semiconductor stack SS of the light-emitting element 120 may be located on the light-emitting surface, and the second-type semiconductor pattern SP2 may include a P-type semiconductor material. In some embodiments, the light-emitting element 120 may be a red-emitting, high-efficiency light-emitting diode.

Next, referring to FIG. 10 , after the protective layer CP is formed, the patterned photoresist layer PR may be removed to expose the first sacrificial layer SF1 . Next, the first sacrificial layer SF1 may also be removed to expose the tie member TR. Next, after the protective layer CP is formed and the patterned photoresist layer PR and the first sacrificial layer SF1 are removed, the second sacrificial layer SF2 may also be removed. For example, the second sacrificial layer SF2 can be removed by exposing and developing. So far, the light emitting assembly 10A according to an embodiment of the present invention is completed, and the light emitting assembly 10A may include: a carrier board CS; a plurality of support members PC, located on the carrier board CS; between the support parts PC; and the support layer PL, located between the plurality of support parts PC and the light emitting elements 120 and the carrier board CS. By making the refractive index difference between the protective layer CP of the light-emitting element 120 of the light-emitting element 120 and the second-type semiconductor pattern SP2 less than 1.8, the ratio of total reflection of the light emitted by the light-emitting element 120 can be reduced, thereby improving the light extraction of the light-emitting element 10A efficiency.

Please refer to FIG. 4 and FIG. 10 at the same time, in some embodiments, the connecting member TR extends on the sidewall W1 of the first type semiconductor pattern SP1 , the sidewall We of the light emitting pattern EP, and the sidewall W2 of the second type semiconductor pattern SP2 and on the supporting member PC, and the connecting member TR is connected to the supporting member PC, so that the light-emitting element 120 can be suspended between the supporting members PC. In addition, the connecting element TR may also extend on the opposite side of the first type semiconductor pattern SP1 and the second type semiconductor pattern SP2 from the protective layer CP, and the first electrode E1 and the second electrode E2 pass through the connecting element TR respectively. The first vias V11 and V12 of the first vias are connected to the first-type semiconductor pattern SP1 and the second-type semiconductor pattern SP2.

In some embodiments, the material of the tie member TR and the material of the protective layer CP may be different, and the refractive index of the protective layer CP may be greater than that of the tie member TR. In some embodiments, the tie TR may include silicon oxide to facilitate bulk transfer processes. In some embodiments, the refractive index of the protective layer CP may be greater than that of silicon oxide, eg, the refractive index of the protective layer CP may be greater than about 1.46. In some embodiments, the protective layer CP may include silicon oxynitride (SiON) having a refractive index of about 1.6.

In some embodiments, the protective layer CP may include HfO 2 having a refractive index between about 1.85 and 2.1.

In some embodiments, the protective layer CP may include ZrO 2 having a refractive index between about 1.9 and 2.15.

In some embodiments, the protective layer CP may include diamond-like carbon having a refractive index of about 2.4. In some embodiments, the protective layer CP may include amorphous carbon having an index of refraction between about 1.5 to 3.1.

Next, referring to FIG. 11 , after the second sacrificial layer SF2 is removed, a circuit substrate 110 may be further provided, wherein the circuit substrate 110 may include pads PD1 and PD2 on the surface thereof. After that, a mass transfer process can be performed, that is, the light-emitting element 120 in the light-emitting assembly 10A of FIG. 10 is taken out and then placed on the circuit substrate 110, for example, the first electrode E1 of the light-emitting element 120 is placed on the pad PD1, And the second electrode E2 of the light-emitting element 120 is placed on the pad PD2, so that the first electrode E1 is located between the semiconductor stack SS and the pad PD1 of the circuit substrate 110, and the second electrode E2 is located between the semiconductor stack SS and the circuit between the pads PD2 of the substrate 110 . Afterwards, the first electrode E1 and the second electrode E2 of the light-emitting element 120 may be electrically connected to the pads PD1 and PD2, respectively, by heat treatment, for example. So far, the display device 10 according to an embodiment of the present invention can be completed, and the display device 10 may include: the circuit substrate 110 ; Since the refractive index difference between the protective layer CP of the light-emitting element 120 of the display device 120 and the second-type semiconductor pattern SP2 is less than 1.8, the light emitted by the light-emitting element 120 is less likely to be totally reflected, so the light extraction efficiency of the display device 10 can be improved.

For example, the circuit substrate 110 may include a bottom plate 112 and a driving circuit layer 114 . The bottom plate 112 of the circuit substrate 110 can be a transparent substrate, an opaque substrate, a flexible substrate or an inflexible substrate, and its material can be a quartz substrate, a glass substrate, a polymer substrate or other suitable materials. The driving circuit layer 114 may include elements or lines required by the display device 10 , such as driving elements, switching elements, storage capacitors, power lines, driving signal lines, timing signal lines, current compensation lines, detection signal lines, and the like. The driving circuit layer 114 can be formed on the base plate 112 by using a thin film deposition process, a lithography process and an etching process. The driving circuit layer 114 may include at least one insulating layer and at least one conductive layer, and the driving circuit layer 114 may include more insulating layers and conductive layers as required.

In some embodiments, the driving circuit layer 114 of the circuit substrate 110 may further include a switch element array, wherein the switch element array includes a plurality of switch elements T arranged in an array, and the switch elements T may be electrically connected to the light emitting element 120 . In detail, the driving circuit layer 114 may include, for example, switching elements T, power lines VL1 and VL2, pads PD1 and PD2, buffer layer I1, gate insulating layer I2, interlayer insulating layer I3 and insulating layer I4. The switching element T is composed of a semiconductor layer TC, a gate TG, a source TS, and a drain TD. The region where the semiconductor layer TC overlaps the gate TG can be regarded as a channel region of the switching element T. The buffer layer I1 is located between the bottom plate 112 and the semiconductor layer TC for preventing impurities in the bottom plate 112 from moving into the semiconductor layer TC and enhancing the adhesion between the semiconductor layer TC and the bottom plate 112 . The gate insulating layer I2 is located between the gate TG and the semiconductor layer TC. The interlayer insulating layer I3 is provided between the source TS, the drain TD, and the power supply line VL1 and the gate TG and the power supply line VL2. The insulating layer I4 is disposed between the source electrode TS, the drain electrode TD, the power supply line VL1 and the pads PD1 and PD2. The pads PD1 and PD2 can be electrically connected to the power line VL1 and the drain TD through the through holes VA1 and VA2 in the insulating layer I4 respectively, and the source TS can be electrically connected to the power line VL2 through the through hole VA3 in the insulating layer I3. When the gate TG receives a signal from, for example, the driving element to turn on the switching element T, the signal received by the source TS from the power line VL2 may be transmitted to the second electrode E2 of the light emitting element 120 . In some embodiments, the pad PD1 can be electrically connected to the switching element T, and the pad PD2 can be electrically connected to the power line VL1.

The material of the semiconductor layer TC may include siliceous semiconductor materials (eg, polysilicon, amorphous silicon, etc.), oxide semiconductor materials, and organic semiconductor materials, but is not limited thereto. The materials of the gate TG, the source TS, the drain TD, the power lines VL1, VL2, and the pads PD1, PD2 may include metals with good conductivity, such as metals such as aluminum, molybdenum, titanium, copper, alloys of the above metals, or Laminates of the above metals and alloys, but not limited to this. For example, the pad PD1 may include sequentially stacked titanium layers, aluminum layers, and titanium layers, or sequentially stacked molybdenum layers, aluminum layers, and molybdenum layers, but not limited thereto.

The materials of the buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3 and the insulating layer I4 may include transparent inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride or a stack of the above materials, but not limited to this. In some embodiments, the buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3, and the insulating layer I4 may also have a single-layer structure or a multi-layer structure, respectively, such as any two or more layers of the above-mentioned insulating materials. Multi-layer stacks can be combined and changed as needed.

In some embodiments, the first electrode E1 and the second electrode E2 can also be electrically connected to the pads PD1 and PD2 through connecting materials, such as conductive glue (such as silver glue), solder, metal or other materials. Material. In some embodiments, other conductive materials or conductive glue may be further included between the above-mentioned connecting material and the pads PD1 , PD2 , the first electrode E1 or the second electrode E2 .

To sum up, the light-emitting element, light-emitting assembly and display device of the present invention can reduce the proportion of total reflection of light emitted from the light-emitting element by making the refractive index difference between the protective layer and the second-type semiconductor pattern less than about 1.8, thereby improving the Light extraction efficiency of a light-emitting element, a light-emitting assembly, and a display device.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended claims.

Claims (20)

1. A light-emitting element characterized by comprising:

a first type semiconductor pattern;

the second type semiconductor pattern is overlapped with the first type semiconductor pattern and is positioned on the first side of the first type semiconductor pattern;

a light emitting pattern between the first type semiconductor pattern and the second type semiconductor pattern;

a first electrode on a second side of the first type semiconductor pattern, the second side being opposite to the first side, the first electrode being connected to the first type semiconductor pattern;

the second electrode is positioned on the same side of the second type semiconductor pattern as the first type semiconductor pattern and is connected with the second type semiconductor pattern; and

and the protective layer is positioned on one side of the second type semiconductor pattern, which is opposite to the first type semiconductor pattern, and the difference between the refractive indexes of the protective layer and the second type semiconductor pattern is less than 1.8.

2. The light-emitting element according to claim 1, wherein a refractive index of the protective layer is greater than 1.46.

3. The light-emitting element according to claim 1, wherein the protective layer comprises silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, hafnium oxide, zirconium dioxide, diamond-like carbon, or amorphous carbon.

4. The light emitting device as claimed in claim 1, wherein the second type semiconductor pattern comprises a P-type semiconductor material.

5. The light-emitting device according to claim 1, wherein the second type semiconductor pattern has a thickness of 1 μm to 3 μm.

6. The light-emitting element according to claim 1, wherein a thickness of the first type semiconductor pattern is between 0.1 μm and 1 μm.

7. A light emitting assembly, comprising:

a carrier plate;

a plurality of supporting members positioned on the carrier plate; and

the light-emitting device according to any one of claims 1 to 6, suspended between the plurality of supporting members by a linking member.

8. The light-emitting device according to claim 7, wherein the tie member extends along sidewalls of the second type semiconductor pattern, the light-emitting pattern and the first type semiconductor pattern, and is connected to the supporting member.

9. The light emitting device according to claim 8, wherein the tie further extends on a side of the first type semiconductor pattern and the second type semiconductor pattern opposite to the protective layer, and the first electrode and the second electrode are connected to the first type semiconductor pattern and the second type semiconductor pattern through a first via hole in the tie, respectively.

10. The light emitting assembly of claim 7, wherein the tie is a different material than the protective layer.

11. The light emitting assembly of claim 7, wherein the protective layer has a refractive index greater than a refractive index of the tether.

12. The light emitting assembly of claim 7, wherein the tie comprises silicon oxide.

13. The illumination assembly of claim 7, further comprising a support layer between the support member and the carrier and between the light emitting elements and the carrier.

14. A display device, comprising:

a circuit substrate; and

the light-emitting device according to any one of claims 1 to 6, located on the circuit substrate and electrically connected to the circuit substrate.

15. The display device according to claim 14, wherein the circuit substrate further comprises a first pad and a second pad, and the first pad is electrically connected to the first electrode and the second pad is electrically connected to the second electrode.

16. The display device according to claim 15, wherein the circuit substrate further comprises a switching element, and the switching element is electrically connected to the first pad or the second pad.

17. A method of manufacturing a display device, comprising:

providing a growth substrate;

forming a plurality of semiconductor layers on the growth substrate;

forming a first sacrificial layer on the multilayer semiconductor layer;

forming an intermediate substrate on the first sacrificial layer;

removing the growth substrate;

patterning the multilayer semiconductor layer to form a semiconductor stack;

forming a tie on the semiconductor stack and the interposer, the tie having a plurality of first vias exposing the semiconductor stack;

respectively forming a first electrode and a second electrode in the plurality of first through holes;

forming a plurality of supports on the tie, the supports not overlapping the stack of semiconductor layers;

forming a carrier plate on the plurality of supporting pieces and the semiconductor lamination layer;

removing the interposer substrate;

removing part of the first sacrificial layer to expose the semiconductor laminated layer; and

and forming a protective layer on the semiconductor lamination layer.

18. The method of manufacturing a display device according to claim 17, wherein the forming a first sacrificial layer on the multilayer semiconductor layer comprises:

roughening a surface of the multilayer semiconductor layer; and

forming the first sacrificial layer on the roughened surface of the multi-layer semiconductor layer.

19. The method of claim 17, wherein the forming the interposer substrate on the first sacrificial layer comprises:

forming an adhesive layer on the first sacrificial layer; and

forming the intermediate substrate on the adhesive layer.

20. The method of claim 17, wherein the forming the plurality of support members on the tie member comprises:

forming a second sacrificial layer on the semiconductor lamination layer and the tie piece, wherein the second sacrificial layer is provided with a plurality of second through holes which do not overlap the semiconductor lamination layer and expose the tie piece; and

forming the support member in the second through hole.

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