CN113782598B - A nanotube tunneling transistor with asymmetric double-gate structure - Google Patents

Abstract

The invention discloses a nanotube tunneling transistor with an asymmetric double-gate structure, which comprises an internal gate, an internal high-dielectric-constant gate oxide, a channel overlapping region, a source side channel non-overlapping region, a drain side channel non-overlapping region, an external high-dielectric-constant gate oxide, an external gate, a source, a drain, an internal drain dielectric isolation layer, an external drain dielectric isolation layer, an internal source dielectric isolation layer, an external source dielectric isolation layer, an insulating isolation layer and a substrate. The invention is characterized in that the asymmetric structures of the internal grid and the external grid are used for tunneling between the electron hole layers which are reversely formed in the channel overlapping region through different work function settings and voltage bias. Compared with the existing nanotube tunneling transistor, the source electrode channel junction is not required to have steep doping distribution, so that the process difficulty is reduced; the larger current density can be obtained on the same area, and the current driving capability is improved; the current source has a steep subthreshold slope in a large current range, and is beneficial to scaling of working voltage.

Description

A nanotube tunneling transistor with asymmetric double-gate structure

technical field

The invention relates to a field effect transistor in the technical field of semiconductors, in particular to a nanotube tunneling transistor with an asymmetric double gate structure.

Background technique

Under the guidance of Moore's Law, the semiconductor industry has continuously reduced the size of MOS devices in order to reduce power consumption and increase the integration level of integrated circuits. However, with the continuous scaling of the feature size of devices, problems such as short channel effects and leakage make Moore's law close to the physical limit. In order to improve these problems, many new devices have emerged one after another. Tunneling transistors based on the quantum tunneling mechanism between carrier bands are considered to be the best low-voltage and low-power devices because of their performance advantages of low sub-threshold swing and low power consumption. One of the potential research directions, but the problem of its low on-state current needs to be solved. The current of the nanowire tunneling transistor is limited by the channel diameter, and increasing the current through arrangement will cause problems of parasitic, power consumption and chip area. Speed, power consumption and area are important indicators for evaluating digital integrated circuits. Circuit cost depends on chip area, so high integration is one of the main goals of circuit design. The nanotube tunneling transistor uses the inner and outer gates to provide a larger effective tunneling area and achieve good electrostatic control, but the small saturation current will cause the problem of insufficient driving ability.

Contents of the invention

The purpose of the present invention is to provide a nanotube tunneling transistor with an asymmetric double gate structure in view of the deficiencies of the prior art. By setting different metal work functions and applying different voltage biases to the asymmetric double gate, the Tunneling occurs between the inversion electron-hole bilayers in the overlapping region. The present invention does not require a steep doping distribution at the source channel junction, which reduces the difficulty of the process; a larger current density can be obtained on the same area, thereby improving the current driving capability; a steeper sub-doping distribution can be obtained in a large current range. The threshold slope facilitates further scaling of the operating voltage.

The concrete technical scheme that realizes the object of the invention is:

A nanotube tunneling transistor with an asymmetric double-gate structure is characterized in that it includes:

The channel non-overlapping region on the drain side, the channel overlapping region and the channel non-overlapping region on the source side stacked from top to bottom;

an internal high-k gate oxide disposed inside the channel overlap region and the source side channel non-overlap region;

an inner gate disposed inside the inner high-k gate oxide;

An external high dielectric constant gate oxide wrapped outside the channel non-overlapping region and the channel overlapping region on the drain side;

An external gate wrapped around an external high-k gate oxide;

The drain on the top of the channel non-overlapping region on the drain side;

The source electrode located at the bottom of the non-overlapping region of the channel on the source side;

An internal drain dielectric isolation layer disposed inside the drain and the non-overlapping region of the channel on one side of the drain;

an external drain dielectric isolation layer arranged outside the drain;

an internal source dielectric isolation layer disposed inside the source;

An external source dielectric isolation layer arranged on the channel non-overlapping region on the source side and outside the source;

an insulating barrier layer provided at the bottom of the structure;

The substrate at the bottom of the insulating spacer.

The channel non-overlapping region on the drain side, the channel overlapping region and the channel non-overlapping region on the source side are made of silicon, germanium, silicon germanium, gallium arsenide, zinc oxide, gallium nitride, indium phosphide or carbon material production;

The drain and source are made of silicon or silicon germanium;

The inner high dielectric constant gate oxide and the outer high dielectric constant gate oxide are made of hafnium dioxide, titanium oxide, silicon nitride, aluminum oxide, tantalum pentoxide or zirconium dioxide;

The internal gate and the external gate are made of tungsten, titanium nitride, aluminum or polysilicon;

The outer drain dielectric isolation layer, the inner drain dielectric isolation layer, the outer source dielectric isolation layer, the inner source dielectric isolation layer and the insulating isolation layer are made of silicon dioxide, hafnium dioxide, titanium oxide, silicon nitride, oxide Made of aluminum, tantalum pentoxide or zirconia;

The substrate is made of SOI, silicon dioxide, sapphire, silicon, germanium, gallium arsenide or gallium nitride material.

The present invention consists of a top-down stacked channel non-overlapping region on the drain side, a channel overlapping region, and a source-side channel non-overlapping region; The internal high dielectric constant gate oxide on the inside; the internal gate located inside the internal high dielectric constant gate oxide; the external high dielectric constant wrapped around the drain side channel non-overlapping region and outside the channel overlapping region Permittivity gate oxide; external gate wrapped outside high-k gate oxide; drain on top of channel non-overlapping region on drain side; channel non-overlapping on source side The source at the bottom of the region; the internal drain dielectric isolation layer inside the channel non-overlapping region on the drain and drain side; the external drain dielectric isolation layer outside the drain; the internal source dielectric isolation layer inside the source; The channel non-overlapping region on the pole side and the external source dielectric isolation layer outside the source; the insulating isolation layer arranged at the bottom of the above structure; and the substrate arranged at the bottom of the insulating isolation layer.

In the present invention, by setting different metal work functions and applying different voltage biases to the asymmetric double gate, the electron layer and the hole layer are respectively inverted in the channel overlapping region, and tunneling occurs between the electron layer and the hole layer. turn on the device. The tunneling of the present invention occurs inside the channel, and does not require a steep doping distribution at the source channel junction, which reduces the difficulty of the process; a larger current density can be obtained on the same area, thereby improving the current driving capability; A steeper subthreshold slope is obtained in the current range, which is conducive to further scaling of the working voltage.

Description of drawings

Fig. 1 is a structural representation of the present invention;

Fig. 2 is the A-A sectional schematic diagram of Fig. 1;

Fig. 3 is the B-B sectional schematic diagram of Fig. 1;

Fig. 4 is the C-C sectional schematic diagram of Fig. 1;

Fig. 5 is the D-D sectional schematic diagram of Fig. 1;

Fig. 6 is the E-E sectional schematic diagram of Fig. 1;

Fig. 7 is the transfer characteristic figure of the present invention;

Fig. 8 is a sub-threshold slope characteristic diagram of the present invention;

Fig. 9 is the energy band diagram when the present invention works in the off state and the on state;

Fig. 10 is the energy band diagram when the nanotube tunneling transistor works in the off state and the on state;

Fig. 11 is a preparation flow chart of the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

Referring to Fig. 1, the present invention includes a drain side channel non-overlapping region 2, a channel overlapping region 3, and a source side channel non-overlapping region 4 stacked from top to bottom; The internal high dielectric constant gate oxide 7 inside the channel non-overlapping region 4 on the pole side; the internal gate 6 located inside the internal high dielectric constant gate oxide; the non-overlapping channel wrapped on the drain side The external high dielectric constant gate oxide 8 outside the region 2 and the channel overlapping region 3; the external gate 9 wrapped outside the external high dielectric constant gate oxide 8; the non-overlapping channel on the drain side The drain 1 at the top of the region 2; the source 5 arranged at the bottom of the channel non-overlapping region 4 on the source side; the drain 1 and the internal drain dielectric isolation layer 12 inside the channel non-overlapping region 2 on the drain side; The external drain dielectric isolation layer 10 outside the drain 1; the internal source dielectric isolation layer 13 inside the source 5; the channel non-overlapping region 4 on the source side and the external source dielectric isolation layer 11 outside the source 5; An insulating isolation layer 14 disposed at the bottom of the structure; a substrate 15 disposed at the bottom of the insulating isolation layer.

The channel non-overlapping region 2 on the drain side, the channel overlapping region 3 and the channel non-overlapping region 4 on the source side are made of silicon, germanium, silicon germanium, gallium arsenide, zinc oxide, gallium nitride, phosphide Made of indium or carbon materials;

The drain 1 and the source 5 are made of silicon or silicon germanium;

The inner high dielectric constant gate oxide 7 and the outer high dielectric constant gate oxide 8 are made of hafnium dioxide, titanium oxide, silicon nitride, aluminum oxide, tantalum pentoxide or zirconium dioxide;

The internal gate 6 and the external gate 9 are made of tungsten, titanium nitride, aluminum or polysilicon;

The outer drain dielectric isolation layer 10, the inner drain dielectric isolation layer 12, the outer source dielectric isolation layer 11, the inner source dielectric isolation layer 13 and the insulating isolation layer 14 are made of silicon dioxide, hafnium dioxide, titanium oxide, Made of silicon nitride, alumina, tantalum pentoxide or zirconia;

The substrate 15 is made of silicon-on-insulator (SOI), silicon dioxide, sapphire, silicon, germanium, gallium arsenide or gallium nitride.

Example 1

Referring to Figures 1-6, in the present invention, the channel non-overlapping region 2 on the drain side, the channel overlapping region 3 and the source side channel non-overlapping region 4 are made of silicon material, and the drain 1 and source 5 are made of silicon material. The inner high dielectric constant gate oxide 7 and the outer high dielectric constant gate oxide 8 are made of hafnium dioxide material, the inner gate 6 and the outer gate 9 are made of tungsten material, the outer drain dielectric isolation layer 10, the inner drain The pole dielectric isolation layer 12 , the external source dielectric isolation layer 11 , the internal source dielectric isolation layer 13 and the insulating isolation layer 14 are made of silicon dioxide, and the substrate 15 is made of silicon.

Referring to Fig. 1-6, Fig. 11, the manufacturing process of present embodiment is as follows:

(1) growing a silicon dioxide insulating isolation layer 14 on the surface of the substrate 15;

(2) Grow silicon and dope high-concentration boron to the bottom, dope high-concentration phosphorus to the top, etch to form drain 1, channel non-overlapping region 2 on the drain side, channel overlapping region 3, and source side Channel non-overlapping region 4 and source 5;

(3) Depositing silicon dioxide to form an external source dielectric isolation layer 11;

(4) Depositing hafnium dioxide and tungsten in sequence to form an external high dielectric constant gate oxide 8 and an external gate 9;

(5) Depositing silicon dioxide to form an external drain dielectric isolation layer 10;

(6) Etching to form the interior of the cylindrical silicon, forming a groove in the center, depositing silicon dioxide, and forming the internal source dielectric isolation layer 13;

(7) Deposit hafnium dioxide and tungsten in sequence to form internal high dielectric constant gate oxide 7 and internal gate 6;

(8) Deposit silicon dioxide to form the internal drain dielectric isolation layer 12 . Embodiment 1 is completed.

Example 2

Referring to Figures 1-6, in the present invention, the channel non-overlapping region 2 on the drain side, the channel overlapping region 3 and the source side channel non-overlapping region 4 are made of silicon material, and the drain 1 and source 5 are made of silicon material. The inner high dielectric constant gate oxide 7 and the outer high dielectric constant gate oxide 8 are made of titanium dioxide, the inner gate 6 and the outer gate 9 are made of titanium nitride, the outer drain dielectric isolation layer 10, the inner drain The dielectric isolation layer 12 , the external source dielectric isolation layer 11 and the internal source dielectric isolation layer 13 are made of silicon nitride, the insulating isolation layer 14 is made of silicon dioxide, and the substrate 15 is made of silicon.

Referring to Fig. 1-6, Fig. 11, the manufacturing process of present embodiment is as follows:

(1) growing a silicon dioxide insulating isolation layer 14 on the surface of the substrate 15;

(2) Grow silicon and dope high-concentration boron to the bottom, dope high-concentration phosphorus to the top, etch to form drain 1, channel non-overlapping region 2 on the drain side, channel overlapping region 3, and source side Channel non-overlapping region 4 and source 5;

(3) depositing silicon nitride to form an external source dielectric isolation layer 11;

(4) Depositing titanium dioxide and titanium nitride in sequence to form an external high dielectric constant gate oxide 8 and an external gate 9;

(5) Depositing silicon nitride to form an external drain dielectric isolation layer 10;

(6) Etching to form the inside of the cylindrical silicon, forming a groove in the center, depositing silicon nitride, and forming the internal source dielectric isolation layer 13;

(7) Depositing titanium dioxide and titanium nitride in sequence to form an internal high dielectric constant gate oxide 7 and an internal gate 6;

(8) Deposit silicon nitride to form the internal drain dielectric isolation layer 12 . Complete embodiment 2.

The invention works like this:

Referring to Figures 1-6, the present invention is based on the vertical nanotube structure. By setting different metal work functions and applying different voltage biases to the asymmetric inner and outer gates, the channel non-overlapping area and channel overlapping area on the source side Inversion-type hole-exiting layer, inversion-type electron-exiting layer in the channel non-overlapping region on the drain side and the channel overlapping region, the hole layer in the channel non-overlapping region on the source side and the non-overlapping channel on the drain side The electron layer in the region connects the source and drain respectively, and the channel overlapping region forms an electron-hole double layer. When the external gate voltage increases to a certain voltage value, the valence band of the hole layer in the channel overlap region is higher than the conduction band of the electron layer, forming a tunneling window, and the electrons and holes tunnel to turn on the device. Different from the nanotube field effect transistor in which point tunneling occurs at the junction of the source and the channel, the present invention produces line tunneling in the entire channel overlapping region, which can increase the tunneling area.

Referring to Figures 7 to 8: the drain 5 and the external gate 9 of the present invention are set to an operating voltage of 0.5V, and the internal gate 6 is set to -0.1V. When the gate voltage is 0V, the drain current of the device is 2.36×10 ^-18 A, and the device is turned off at this time. When the gate voltage rises to 0.5V, the drain current of the device is 4.59×10 ^-9 A, and the device is turned on. Compared with the on-state current of 8.03×10 ^-11 A of the traditional nanotube tunneling transistor, the on-state current of the present invention is increased by 57.2 times, and the current switch ratio is increased by about 265 times. In the present invention, the subthreshold slope is less than 60mV/dec in the range of the drain current from 3.7×10 ^-18 A to 3×10 ^-11 A, and the minimum subthreshold slope is 2.1mV/dec. Compared with the traditional nanotube tunneling transistor, the present invention realizes a steep subthreshold slope in a larger drain current range.

The on-state current and the steep subthreshold slope characteristics of the present invention can be drawn from Fig. 9 and Fig. 10, Fig. 9 is the channel energy band diagram of the present invention along the direction perpendicular to the channel, and Fig. 10 is nanotube tunneling The channel energy band diagram of the transistor along the direction parallel to the channel, where A represents the off-state conduction band energy level, B represents the on-state conduction band energy level, C represents the off-state valence band energy level, and D represents the on-state valence band energy level class. In the off state, there is no overlapping area between the conduction band and the valence band in the channel of the present invention, and no tunneling occurs at this time. As the gate voltage increases, the energy band near the outer gate is gradually pulled down, and when the energy bands start to align, line tunneling occurs in the channel, and the current increases sharply, thus having a steep subthreshold slope. In the on state, the tunneling distances of the present invention and the nanotube tunneling transistor are 3.95 nanometers and 5.48 nanometers respectively, and the tunneling of the present invention occurs in the entire channel, and has a larger tunneling area. According to the tunneling probability relationship, the present invention can obtain a larger tunneling current, thereby obtaining a higher on-state current.

Claims (7)

1. A nanotube tunneling transistor of asymmetric double gate structure, comprising:

a drain-side channel non-overlapping region (2), a channel overlapping region (3), and a source-side channel non-overlapping region (4) stacked from top to bottom;

an internal high-dielectric-constant gate oxide (7) provided inside the channel overlap region (3) and the source-side channel non-overlap region (4);

an internal gate electrode (6) provided inside the internal high-permittivity gate oxide (7);

an external high dielectric constant gate oxide (8) wrapped around the drain side channel non-overlap region (2) and the outside of the channel overlap region (3);

an external gate (9) wrapped outside the external high dielectric constant gate oxide (8);

a drain electrode (1) arranged on top of the drain electrode side channel non-overlapping region (2);

a source electrode (5) arranged at the bottom of the source electrode side channel non-overlapping region (4);

an internal drain dielectric spacer layer (12) provided inside the drain (1) and the drain-side channel non-overlapping region (2);

an external drain dielectric isolation layer (10) provided outside the drain electrode (1);

an internal source dielectric isolation layer (13) provided inside the source electrode (5);

an external source dielectric isolation layer (11) provided outside the source-side channel non-overlapping region (4) and the source (5);

an insulating isolation layer (14) arranged at the bottom of the structure;

and a substrate (15) arranged at the bottom of the insulating isolation layer (14).

2. The asymmetric double-gate nanotube tunneling transistor according to claim 1, characterized in that said drain-side channel non-overlapping region (2), channel overlapping region (3) and source-side channel non-overlapping region (4) are made of silicon, germanium, silicon germanium, gallium arsenide, zinc oxide, gallium nitride, indium phosphide or carbon material.

3. Nanotube tunneling transistor of asymmetric double gate structure according to claim 1 characterized in that the drain (1) and source (5) are made of silicon or silicon germanium material.

4. The nanotube tunneling transistor of asymmetric double gate structure according to claim 1, wherein said inner high dielectric constant gate oxide (7) and outer high dielectric constant gate oxide (8) are made of hafnium oxide, titanium oxide, silicon nitride, aluminum oxide, tantalum pentoxide or zirconium dioxide materials.

5. Nanotube tunneling transistor of asymmetric double gate structure according to claim 1 characterized in that the inner gate (6) and outer gate (9) are made of tungsten, titanium nitride, aluminum or polysilicon material.

6. The nanotube tunneling transistor of asymmetric double gate structure according to claim 1, wherein said outer drain dielectric spacer (10), inner drain dielectric spacer (12), outer source dielectric spacer (11), inner source dielectric spacer (13) and insulating spacer (14) are made of silicon dioxide, hafnium dioxide, titanium oxide, silicon nitride, aluminum oxide, tantalum pentoxide or zirconium dioxide materials.

7. Nanotube tunneling transistor of asymmetric double gate structure according to claim 1 characterized in that said substrate (15) is made of silicon on insulator, SOI, silicon dioxide, sapphire, silicon, germanium, gallium arsenide or gallium nitride material.

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