CN110459541B - Planar complementary type tunneling field effect transistor inverter - Google Patents

Abstract

The invention relates to a planar complementary tunneling field effect transistor inverter which is a planar structure consisting of an InAs/Si heterojunction TFET and a Ge/Si heterojunction TFET, wherein the InAs/Si heterojunction TFET and the Ge/Si heterojunction TFET are respectively used as an NTFET and a PTFET. The tunneling junctions of the NTFET and the PTFET in the novel planar CTFET inverter are in a heterojunction tunneling junction mode that the channel covers the source region, the heterojunction tunneling can improve the working frequency of the inverter, and the tunneling current of the NTFET and the PTFET can be adjusted by regulating and controlling the length of the channel covering the source region. The NTFET and the PTFET are both buried layer and drain plane structures, the process complexity of drain-to-void isolation is avoided by utilizing an electrical characteristic isolation mode, and the compatibility with the traditional CMOS process can be realized.

Description

A Planar Complementary Tunneling Field Effect Transistor Inverter

technical field

The invention belongs to the technical field of microelectronics, and in particular relates to a planar complementary tunneling field effect transistor inverter.

Background technique

As the size of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) continues to shrink, power consumption has become the biggest problem limiting the development of integrated circuits. At present, the leakage-induced barrier reduction effect and Fermi tailing effects seriously affect the power dissipation of MOSFETs in small size. The leakage-induced barrier lowering effect increases the leakage of short-channel MOSFETs and increases the static power consumption of the integrated circuit; the Fermi tailing effect makes the sub-threshold swing of the MOSFET not less than 60mv/dec, which limits the MOSFET's operation. As the voltage continues to shrink, it is difficult to reduce the power consumption of integrated circuits.

Due to the working mechanism of BTBT (Band-To-Band-Tunneling), TFET (Tunneling Field Effect Transistor, Tunneling Field Effect Transistor) is not affected by the leakage-induced barrier lowering effect and the Fermi tailing effect. Circuits composed of TFETs can achieve lower power consumption. The CTFET (Complementary Tunneling Field Effect Transistor, complementary tunneling field effect transistor) inverter is the most basic logic unit of digital circuits, so the study of CTFET inverter is a necessary part of reducing the power consumption of integrated circuits.

Due to the limitation of the band gap and the effective mass of carriers, the on-state current of All-Silicon TFET (All-Silicon Tunneling Field Effect Transistor) is low and its working performance is limited, so it is difficult to apply it to the circuit. HTFET (Heterojunction Tunneling Field Effect Transistor, Heterojunction tunneling field effect transistor) can greatly improve the on-state current due to the inherent band bias at the tunneling junction, but most HTFETs use process schemes such as nanowire vertical structure or leakage isolation, which makes the fabrication The process difficulty of the CTFET inverter increases and it is difficult to be compatible with the existing CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) process.

SUMMARY OF THE INVENTION

In order to solve the above problems in the prior art, the present invention provides a planar complementary tunnel field effect transistor inverter. The technical problem to be solved by the present invention is realized by the following technical solutions:

The present invention provides a planar complementary tunneling field effect transistor inverter, comprising:

Intrinsic Si substrate;

an isolation region, located on the upper surface of the intrinsic Si substrate, the bottom of which extends to the interior of the intrinsic Si substrate, and the isolation regions are respectively arranged on both sides and the middle of the intrinsic Si substrate;

The P ⁺ source region, the N ⁺ drain region, the P ⁺ drain region and the N ⁺ source region are arranged at intervals on the upper surface of the intrinsic Si substrate in sequence, and the bottoms thereof all extend to the interior of the intrinsic Si substrate, and the N ⁺ drain region and the P ⁺ drain region are located on both sides of the isolation region in the middle;

An InAs channel layer on the intrinsic Si substrate and in contact with at least a portion of the P ⁺ source region and the N ⁺ drain region;

A Ge channel layer on the intrinsic Si substrate and in contact with at least a portion of the P ⁺ drain region and the N ⁺ source region;

two gate oxide layers, respectively located on the InAs channel layer and the Ge channel layer;

two gate metal layers, respectively located on the corresponding gate oxide layers;

two source metal layers, both located on the intrinsic Si substrate and in contact with the P ⁺ source region and the N ⁺ source region, respectively;

two drain metal layers, respectively located on the InAs channel layer and the Ge channel layer;

a passivation layer, located between the gate metal layer, the source metal layer and the drain metal layer, and the uncovered area on the intrinsic Si substrate;

an interconnection metal layer, located on the gate metal layer, the source metal layer and the drain metal layer, and the interconnection metal layers on the gate metal layer are connected to each other, and the drain metal layer The interconnect metal layers above are connected to each other.

In an embodiment of the present invention, the doping concentration of the P ⁺ source region and the P ⁺ drain region is 2×10 ¹⁹ -5×10 ¹⁹ cm ^-3 .

In an embodiment of the present invention, the doping concentration of the N ⁺ drain region and the N ⁺ source region is 2×10 ¹⁹ -5×10 ¹⁹ cm ^-3 .

In an embodiment of the present invention, the thickness of the InAs channel layer is 5-7 nm, the length of the region covering the P ⁺ source region is 30-45 nm, and the doping concentration is 1×10 ¹³ -1 ×10 ¹⁵ cm ^-3 .

In an embodiment of the present invention, the thickness of the Ge channel layer is 5-7 nm, the length of the region covering the N ⁺ source region is 30-45 nm, and the doping concentration is 1×10 ¹² -1 ×10 ¹³ cm ^-3 .

In an embodiment of the present invention, the material of the gate oxide layer is Al ₂ O ₃ or HfO ₂ , and the thickness is 3-5 nm.

In an embodiment of the present invention, the length of the region of the gate oxide layer not covered by the gate metal layer is 45-75 nm.

In an embodiment of the present invention, the isolation medium filled in the isolation region is SiO ₂

Compared with the prior art, the beneficial effects of the present invention are:

The planar complementary tunneling field effect transistor inverter of the present invention is a planar structure composed of InAs/Si heterojunction TFET and Ge/Si heterojunction TFET, has no leakage isolation, and can be well matched with CMOS technology. Due to the inherent band bias of the heterojunction InAs/Si and Ge/Si, the heterojunction TFET can obtain a larger current and a lower subthreshold swing at a smaller gate voltage, thus making the present invention The new planar CTFET inverter has higher speed.

And has excellent steady-state characteristics and transient characteristics.

The above description is only an overview of the technical solution of the present invention, in order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description, and in order to make the above and other objects, features and advantages of the present invention more obvious and easy to understand , the following specific preferred embodiments, and in conjunction with the accompanying drawings, are described in detail as follows.

Description of drawings

1 is a schematic structural diagram of a planar CTFET inverter provided by an embodiment of the present invention;

2a-2m are schematic process diagrams of a planar CTFET inverter provided by an embodiment of the present invention.

Description of reference numerals

1-intrinsic Si substrate; 2-isolation region; 3-P ⁺ source region; 4-N ⁺ drain region; 5-P ⁺ drain region; 6-N ⁺ source region; 7-InAs channel layer; 8- Ge channel layer; 9-gate oxide layer; 10-gate metal layer; 11-source metal layer; 12-drain metal layer; 13-passivation layer; 14-interconnection metal layer.

Detailed ways

In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, a planar complementary tunneling field effect transistor inverter according to the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

The foregoing and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description of the specific implementation with the accompanying drawings. Through the description of the specific embodiments, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the accompanying drawings are only for reference and description, not for the technical analysis of the present invention. program is restricted.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a planar CTFET inverter provided by an embodiment of the present invention. As shown in the figure, the novel planar CTFET inverter of this embodiment includes:

Intrinsic Si substrate 1;

The isolation region 2 is located on the upper surface of the intrinsic Si substrate 1, and its bottom extends to the interior of the intrinsic Si substrate 1. The isolation region 2 is arranged on both sides and the middle of the intrinsic Si substrate 1, respectively. Intrinsic Si substrate 1 is divided into NTFET active region and PTFET active region;

The P ⁺ source region 3 , the N ⁺ drain region 4 , the P ⁺ drain region 5 and the N ⁺ source region 6 are arranged at intervals on the upper surface of the intrinsic Si substrate 1 in order, and the bottoms of the bottoms all extend to the bottom of the intrinsic Si substrate 1 . Inside, and N ⁺ drain region 4 and P ⁺ drain region 5 are located on both sides of the middle isolation region 2, wherein, P ⁺ source region 3 serves as the source region of the NTFET, N ⁺ drain region 4 serves as the drain region of the NTFET, and P ⁺ drain region Region 5 serves as the drain region of PTFET, and N ⁺ source region 6 serves as the source region of PTFET;

The InAs channel layer 7 is located on the intrinsic Si substrate 1, and is in contact with at least a part of the P ⁺ source region 3 and the N ⁺ drain region 4, as the channel region of the NTFET;

The Ge channel layer 8 is located on the intrinsic Si substrate 1, and is in contact with at least a part of the P ⁺ drain region 5 and the N ⁺ source region 6, as a channel region of the PTFET;

Two gate oxide layers 9 are respectively located on the InAs channel layer 7 and the Ge channel layer 8;

The two gate metal layers 10 are respectively located on the corresponding gate oxide layers 9;

Two source metal layers 11 are located on the intrinsic Si substrate 1 and are in contact with the P ⁺ source region 3 and the N ⁺ source region 6 respectively;

The two drain metal layers 12 are respectively located on the InAs channel layer 7 and the Ge channel layer 8;

The passivation layer 13 is located between the gate metal layer 10, the source metal layer 11 and the drain metal layer 12, and the uncovered area on the intrinsic Si substrate 1;

The interconnection metal layer 14 is located on the gate metal layer 10 , the source metal layer 11 and the drain metal layer 12 , and the interconnection metal layer 14 on the gate metal layer 10 is connected to each other, and the interconnection metal layer 12 on the drain metal layer 12 The layers 14 are interconnected. The interconnection metal layer 14 on the gate metal layer 10 is connected to each other, so that the gate electrode of the PTFET is connected to the gate electrode of the NTFET to form the input terminal Vin of the planar CTFET inverter, and the interconnection metal layer on the drain metal layer 12 is formed. 14 are connected to each other, so that the drain electrode of PTFET is connected with the drain electrode of NTFET, forming the output terminal Vout of the planar CTFET inverter, the source electrode of PTFET is connected to high level VDD through the interconnection metal 14 on the source metal layer 11, and the NTFET The source electrode of is connected to the low level GND through the interconnection metal 14 on the other source metal layer 11 .

Optionally, the doping concentration of the P ⁺ source region 3 and the P ⁺ drain region 5 is 2×10 ¹⁹ -5×10 ¹⁹ cm ^-3 , and the doping ions are boron ions.

Optionally, the doping concentration of the N ⁺ drain region 4 and the N ⁺ source region 6 is 2×10 ¹⁹ -5×10 ¹⁹ cm ^-3 , and the doping ions are arsenic ions.

Optionally, the thickness of the InAs channel layer 7 is 5-7nm, and if the thickness is too thick, the tunneling capability of the heterojunction will be affected, and the length of the region covered by the InAs channel layer 7 on the P ⁺ source region 3 is 30-45nm, This length can take into account both the area of the TFET and the on-state current. The doping concentration of the InAs channel layer 7 is 1×10 ¹³ -1×10 ¹⁵ cm ^-3 , and the doping ions are arsenic ions.

Optionally, the thickness of the Ge channel layer 8 is 5-7 nm, and if the thickness is too thick, the tunneling capability of the heterojunction will be affected, and the length of the region covered by the Ge channel layer 8 on the N ⁺ source region 6 is 30-45 nm, This length can take into account both the area of the TFET and the on-state current. The doping concentration of the Ge channel layer 8 is 1×10 ¹² -1×10 ¹³ cm ^-3 , and the doping ions are boron ions.

Optionally, the material of the gate oxide layer 9 is a high-k dielectric material such as Al ₂ O ₃ or HfO ₂ , and the thickness is 3-5 nm. The high-k gate oxide layer 9 can improve the gate control capability of the TFET.

Optionally, the length of the area of the gate oxide layer 9 not covered by the gate metal layer 10 is 45-75nm, that is, the distance between the gate and the drain is 45-75nm, this length can suppress the bipolar effect of the TFET without affecting the on-state current.

Optionally, the isolation medium filled in the isolation region 2 is SiO ₂ , which is used to completely separate the electrical properties of the InAs/Si heterojunction TFET from the Ge/Si heterojunction TFET.

When the planar CTFET inverter of this embodiment works, a positive voltage VDD is applied to the source electrode of the PTFET, the source electrode of the NTFET is grounded, the gate electrodes of the two are connected as the inverter input terminal Vin, and the drain electrodes of the two are connected as the output terminal Vout. When the input terminal Vin is at a low level of 0, since the NTFET is turned off, the PTFET is turned on linearly, so that the output terminal Vout is at a high level; when the input voltage gradually increases to a high level of 1, the PTFET is turned off, and the NTFET is turned on linearly. The output terminal Vout is made to be low level to complete the inversion function.

In this embodiment, the InAs/Si heterojunction is used in the NTFET, and the Ge/Si heterojunction is used in the PTFET. Different, the electron affinity is also different, so there is an inherent band bias. For NTFET, there is a smaller energy difference between the conduction band of InAs in the channel region and the valence band of Si in the source region, and for PTFET, there is a smaller energy difference between the valence band of Ge in the channel region and the conduction band of Si in the source region Therefore, an effective tunneling window can occur at a smaller gate voltage, which is beneficial to obtain a larger on-state current and a steeper subthreshold slope, which can increase the operating frequency of the CTFET inverter.

Meanwhile, in this embodiment, both the channel region InAs and the channel region Ge cover the source region, forming a line tunneling window. Compared with point tunneling, line tunneling has a larger tunneling capacity. Therefore, a larger working current can be obtained, and the working current can be controlled by adjusting the length of the line tunneling window, which is beneficial to the design of the TFET circuit. In addition, the design of the distance between the gate and the drain can effectively suppress the bipolar effect of the TFET, thereby reducing the static power consumption of the inverter, and at the same time suppressing the overshoot voltage caused by the Miller capacitance.

The planar CTFET inverter of this embodiment is composed of InAs/Si heterojunction TFET and Ge/Si heterojunction TFET, wherein InAs/Si heterojunction TFET and Ge/Si heterojunction TFET are used as NTFET and PTFET respectively, Both NTFET and PTFET are planar structures with buried layer leakage. The isolation of the pin electrical characteristics reduces the complexity of the structure and is beneficial to the realization of the inverter structure.

Embodiment 2

Please refer to FIGS. 2a-2m. FIGS. 2a-2m are schematic process diagrams of a planar CTFET inverter provided by an embodiment of the present invention. The manufacturing method of the planar CTFET inverter includes the following steps:

Step 1: Substrate preparation;

A single-throw N100 intrinsic Si substrate with a thickness of 500±25 μm and a size of 4 inches was selected as the intrinsic Si substrate 1 .

Step 2: forming an isolation region 2 in the intrinsic Si substrate 1, as shown in FIG. 2a;

A trench with a depth of 300±50nm and a sidewall angle of 80°-85° is etched on the intrinsic Si substrate 1 by the method of shallow trench isolation, and _SiO2 is filled as the isolation medium to form an isolation region 2, which is isolated from Region 2 divides intrinsic Si substrate 1 into an NTFET active region and a PTFET active region.

Step 3: forming P ⁺ source region 3 and P ⁺ drain region 5 by ion implantation, as shown in Figure 2b;

Using photoresist as a mask to achieve ion implantation, the dopant ions are boron ions, the implantation dose is 2×10 ¹⁵ -3×10 ¹⁵ cm ^-2 , the implantation energy is 4-10kev, and the P ⁺ source region 3 is used as the NTFET. Source region, P ⁺ drain region 5 as the drain region of PTFET.

Step 4: ion implantation to form N ⁺ drain region 4 and N ⁺ source region 6, as shown in FIG. 2c;

Using photoresist as a mask, ion implantation is realized, wherein the doping ions are arsenic ions, the implantation dose is 2×10 ¹⁵ -3×10 ¹⁵ cm ^-2 , the implantation energy is 8-12kev, and the N ⁺ drain region 4 is used as the NTFET. The drain region, the N ⁺ source region 6 serves as the source region of the PTFET.

Step 5: perform rapid thermal annealing, the annealing temperature is 950-1050°C, and the annealing time is 5s, the rapid thermal annealing can activate the impurity ions and repair the lattice damage caused by the ion implantation;

Step 6: forming an InAs channel layer 7, as shown in FIG. 2d;

An InAs channel layer 7 with a thickness of 5-7 nm is bonded to the intrinsic Si substrate 1 by a bonding technique.

Step 7: forming the Ge channel layer 8, as shown in FIG. 2e;

A Ge channel layer 8 with a thickness of 5-7 nm is bonded to the intrinsic Si substrate 1 by a bonding technique.

Step 8: forming a gate oxide layer 9, as shown in FIG. 2f;

By atomic layer deposition (ALD), a HfO ₂ layer with a thickness of 3-5 nm is deposited and formed, and the high-k gate oxide layer 9 can improve the gate control capability of the TFET.

Step 9: forming the gate metal layer 10;

Using photoresist as a mask, a TiN metal layer is formed by metal sputtering, as shown in FIG. 2g, and the photoresist is peeled off to form a gate metal layer 10 with a thickness of 200-300 nm, as shown in FIG. 2h.

Step 10: Etch the gate oxide layer 9 by wet method, and drain the source-drain electrode region, as shown in FIG. 2i;

Step 11: forming the source metal layer 11 and the drain metal layer 12;

Using the photoresist as a mask, a Ni metal layer with a thickness of 200-300 nm is formed in the source and drain electrode regions by electron beam evaporation technology. As shown in Figure 2j, the photoresist is peeled off to form a source metal layer 11 and a drain metal layer. Layer 12, as shown in Figure 2k.

Step 12: perform rapid thermal annealing, the annealing temperature is 600-650°C, and the annealing time is 30s, and a nickel-silicon alloy is formed on the Si surface through rapid thermal annealing to form a good ohmic contact;

Step 13: forming a passivation layer 13;

By chemical vapor deposition (PECVD) technology, a 500-600 nm SiO ₂ layer is deposited on the device formed in step 12, and the SiO ₂ layer is etched to form a passivation layer 13, as shown in FIG. 21;

Step 14: Form the interconnect metal layer 14 .

A metal Al layer of 2-3 μm is deposited on the device formed in step 13, and an interconnection metal layer is formed by reverse etching the metal Al layer, as shown in FIG. 2m. The interconnection metal layer 14 on the gate metal layer 10 is connected to each other, so that the gate electrode of the PTFET is connected to the gate electrode of the NTFET to form the input terminal Vin of the planar CTFET inverter, and the interconnection metal layer on the drain metal layer 12 is formed. 14 are connected to each other, so that the drain electrode of PTFET is connected with the drain electrode of NTFET, forming the output terminal Vout of the planar CTFET inverter, the source electrode of PTFET is connected to high level VDD, and the source electrode of NTFET is connected to low level GND.

Since the planar CTFET inverter of this embodiment is a planar structure composed of an InAs/Si heterojunction TFET and a Ge/Si heterojunction TFET, there is no leakage isolation, so it can be well matched with the CMOS process during the fabrication process. In addition, due to the inherent band bias of the heterojunction InAs/Si and Ge/Si, the heterojunction TFET can obtain a larger current and a lower subthreshold swing at a smaller gate voltage, which makes the The invented planar CTFET inverter has higher speed.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (6)

1. a planar complementary tunneling field effect transistor inverter, is characterized in that, comprises: Intrinsic Si substrate (1); An isolation region (2) is located on the upper surface of the intrinsic Si substrate (1), the bottom of which extends to the interior of the intrinsic Si substrate (1), and the isolation regions (2) are respectively arranged on the Both sides and the middle of the intrinsic Si substrate (1); The P ⁺ source region (3), the N ⁺ drain region (4), the P ⁺ drain region (5) and the N ⁺ source region (6) are sequentially arranged at intervals on the upper surface of the intrinsic Si substrate (1), Its bottoms all extend to the interior of the intrinsic Si substrate (1), and the N ⁺ drain region (4) and the P ⁺ drain region (5) are located on both sides of the isolation region (2) in the middle , wherein the P ⁺ source region (3) serves as the source region of the NTFET, the N ⁺ drain region (4) serves as the drain region of the NTFET, the P ⁺ drain region (5) serves as the drain region of the PTFET, and the and N ⁺ source region (6) as the source region of PTFET; An InAs channel layer (7) on the intrinsic Si substrate (1) and in contact with at least a portion of the P ⁺ source region (3) and the N ⁺ drain region (4), the InAs The channel layer (7) is used as the channel region of the NTFET; the thickness of the InAs channel layer (7) is 5-7nm, and the length of the region covering the P ⁺ source region (3) is 30-45nm, The doping concentration is 1×10 ¹³ -1×10 ¹⁵ cm ^-3 ; A Ge channel layer (8) on the intrinsic Si substrate (1) and in contact with at least a portion of the P ⁺ drain region (5) and the N ⁺ source region (6), the Ge The channel layer (8) is used as the channel region of the PTFET; the thickness of the Ge channel layer (8) is 5-7nm, and the length of the region covering the N ⁺ source region (6) is 30-45nm, The doping concentration is 1×10 ¹² -1×10 ¹³ cm ^-3 ; two gate oxide layers (9), respectively located on the InAs channel layer (7) and the Ge channel layer (8); two gate metal layers (10), respectively located on the corresponding gate oxide layers (9); two source metal layers (11), both located on the intrinsic Si substrate (1) and in contact with the P ⁺ source region (3) and the N ⁺ source region (6), respectively; two drain metal layers (12), respectively located on the InAs channel layer (7) and the Ge channel layer (8); a passivation layer (13) located between the gate metal layer (10), the source metal layer (11) and the drain metal layer (12), and the intrinsic Si substrate (1) areas that are not covered; An interconnection metal layer (14) is located on the gate metal layer (10), the source metal layer (11) and the drain metal layer (12), and on the gate metal layer (10) The interconnection metal layers (14) are connected to each other, and the interconnection metal layers (14) on the drain metal layer (12) are connected to each other; The interconnecting metal layers (14) on the gate metal layer (10) are connected to each other, so that the gate electrode of the PTFET is connected to the gate electrode of the NTFET to form the input terminal Vin of the planar CTFET inverter, and the drain metal layer ( The interconnecting metal layers (14) on 12) are connected to each other, so that the drain electrode of the PTFET is connected to the drain electrode of the NTFET to form the output terminal Vout of the planar CTFET inverter, and the source electrode of the PTFET passes through the source metal layer (11). The interconnect metal layer (14) on the ) is connected to a high level VDD, and the source electrode of the NTFET is connected to a low level GND through another interconnect metal layer (14) on the source metal layer (11). 2 . The planar complementary tunneling field effect transistor inverter according to claim 1 , wherein the doping concentration of the P ⁺ source region ( 3 ) and the P ⁺ drain region ( 5 ) is 2. 3 . ×10 ¹⁹ -5 × 10 ¹⁹ cm ^-3 . 3 . The planar complementary tunneling field effect transistor inverter according to claim 1 , wherein the doping concentration of the N ⁺ drain region ( 4 ) and the N ⁺ source region ( 6 ) 2×10 ¹⁹ -5×10 ¹⁹ cm ^-3 . 4 . The planar complementary tunneling field effect transistor inverter according to claim 1 , wherein the gate oxide layer ( 9 ) is made of Al ₂ O ₃ or HfO ₂ and has a thickness of 3-5 nm. 5 . 5. The planar complementary tunneling field effect transistor inverter according to claim 1, wherein the length of the region of the gate oxide layer (9) not covered by the gate metal layer (10) is 45- 75nm. 6 . The planar complementary tunneling field effect transistor inverter according to claim 1 , wherein the isolation medium filled in the isolation region ( 2 ) is SiO ₂ . 7 .

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