CN113740599B - Power frequency zero-crossing counting time-stamp verification device and method based on network synchronous clock - Google Patents
Power frequency zero-crossing counting time-stamp verification device and method based on network synchronous clock Download PDFInfo
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Abstract
本发明公开了一种基于网络同步时钟的工频过零计数时标校验装置及方法，属于电力通信和测量技术领域。本发明装置，包括：工频过零信号源；过零电压驱动电路；过零检测电路；通信信号分离电路；通信侦听电路；计数和锁存电路；控制和计算电路。本发明基于网络中央节点设备所发送的信标报文、工频过零计数时标报文完成对被测设备工频过零计数时标误差的测量，且测量的每个步骤均可进行测量精度的标定。
The present invention discloses a power frequency zero-crossing counting time-mark calibration device and method based on a network synchronous clock, belonging to the field of power communication and measurement technology. The device of the present invention comprises: a power frequency zero-crossing signal source; a zero-crossing voltage driving circuit; a zero-crossing detection circuit; a communication signal separation circuit; a communication monitoring circuit; a counting and latching circuit; and a control and calculation circuit. The present invention completes the measurement of the power frequency zero-crossing counting time-mark error of the device under test based on the beacon message sent by the network central node device and the power frequency zero-crossing counting time-mark message, and each step of the measurement can be calibrated for the measurement accuracy.
Description
Technical Field
The invention relates to the technical field of power communication and measurement, in particular to a power frequency zero crossing counting time mark verification device and method based on a network synchronous clock.
Background
At present, a high-speed carrier communication technology is widely adopted in local communication in the field of low-voltage power consumption information acquisition, and a network synchronous clock established by taking a 25MHz clock as a frequency, increasing 1 count and 32-bit unsigned count value in a beacon can be applied to accurate measurement of power frequency voltage zero-crossing phase differences among different node positions in a low-voltage radio station area.
The zero-crossing phase difference parameter together with the characteristic parameters such as the effective voltage value, the signal-to-noise ratio, the power frequency period and the like can be used for distinguishing different station area household transformer relations where metering communication nodes under two adjacent transformers are located. The two voltage zero crossing points in the waveforms of the two adjacent areas in the field actual measurement have phase differences, so that two different areas corresponding to the two positions can be distinguished. However, because the manufacturers are different, or the different schemes of the same manufacturer are different in setting and processing the network synchronous clock, the time for stamping the time stamp of the received message is different, the zero-crossing judging circuit is different, the triggering mechanism for locking the counting value of the network synchronous clock is different, and the software processing modes for recording the power frequency zero-crossing counting time mark are different, the factors cause different time delays of the power frequency zero-crossing counting time mark results recorded by the network center nodes of different manufacturers and different schemes. If the time delays are not calibrated and measured uniformly, the network sub-nodes cannot compare the power frequency zero crossing count time scale data of the network center nodes of two different manufacturers and different schemes, and the station area identification cannot be performed.
Therefore, accurate measurement of the synchronous clock count value of the communication network corresponding to the zero crossing moment of the power frequency voltage, in particular to establishment of a unified time scale for different manufacturers and different design schemes, is a necessary condition for guaranteeing field station area identification realized by adopting a zero crossing phase difference principle.
Disclosure of Invention
Aiming at the problems, the invention relates to a power frequency zero crossing counting time mark verification device based on a network synchronous clock, which comprises the following steps:
the power frequency zero-crossing signal source is connected with the zero-crossing voltage driving circuit and the zero-crossing detection circuit and transmits zero-crossing voltage signals to the zero-crossing voltage driving circuit and the zero-crossing detection circuit;
The zero-crossing voltage driving circuit is connected with the network central node equipment to be tested and the communication signal separation circuit, drives the network central node equipment to be tested to meet the power requirement received by the central node equipment through the zero-crossing voltage signal, and drives the communication signal separation circuit to send out a communication signal;
The zero-crossing detection circuit outputs a zero-crossing trigger signal corresponding to the zero-crossing moment of the voltage signal according to the zero-crossing voltage signal and the setting of the zero-crossing direction type, and inputs the zero-crossing trigger signal to the counting and latching circuit;
The communication signal separation circuit is connected with the zero-crossing trigger signal and sends out a communication signal to the zero-crossing trigger signal;
A communication interception circuit for generating a beacon indication signal according to the communication signal and inputting the beacon indication signal to the counting and latching circuit;
The counting and latching circuit receives the beacon indication signal and the zero-crossing trigger signal and transmits the beacon indication signal and the zero-crossing trigger signal to the test control and calculation circuit;
The control and calculation circuit is connected with the tested network central node equipment, and determines the average error and variance error result of the power frequency zero crossing counting time scale of the tested network central node equipment according to the beacon indication signal and the zero crossing trigger signal.
Optionally, the zero-crossing trigger signal is a pulse level signal, and the zero-crossing direction type of the zero-crossing trigger signal has a voltage rising direction and a voltage falling direction.
Optionally, the beacon indication signal is generated at a time corresponding to a beacon time stamp specified by the communication standard.
Optionally, the apparatus further comprises: the high-precision adjustable clock source is connected with the communication interception circuit and the counting and latching circuit and has an output frequency fine tuning function and a clock signal dithering function.
The invention also provides a power frequency zero crossing counting time mark verification method based on the network synchronous clock, which comprises the following steps:
Step 1: the test control and calculation circuit sends a communication starting command to the tested network central node equipment through the central node access data, and controls the operation of the tested network central node equipment and sends a beacon message according to the communication switching command;
Step 2: calculating a frequency offset error measurement result of the measured network central node equipment:
step 3: setting frequency setting parameters input to a high-precision adjustable clock source according to the frequency offset error measurement result;
Step 4: calculating a count value of the counting and latching circuit and a count difference value of the tested network central node equipment;
step 5: the test control and calculation circuit sets count value increasing and decreasing control parameters to the counting and latching circuit;
step 6: the test control and calculation circuit sends a power frequency period message sending command to the tested network central node equipment through the central node access data, and controls the tested network central node equipment to send a power frequency zero crossing count time mark message;
step 7: the communication interception circuit acquires a power frequency zero crossing count time mark of the tested network central node equipment;
step 8: the test control and calculation circuit outputs average error and variance error according to the power frequency zero crossing counting time scale.
The invention completes the measurement of the power frequency zero crossing counting time mark error of the tested equipment based on the beacon message and the power frequency zero crossing counting time mark message sent by the network central node equipment, and each measuring step can calibrate the measuring precision.
Drawings
FIG. 1 is a block diagram of the apparatus of the present invention;
Fig. 2 is a flow chart of the method of the present invention.
Detailed Description
The exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, however, the present invention may be embodied in many different forms and is not limited to the examples described herein, which are provided to fully and completely disclose the present invention and fully convey the scope of the invention to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the accompanying drawings is not intended to be limiting of the invention. In the drawings, like elements/components are referred to by like reference numerals.
Unless otherwise indicated, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. In addition, it will be understood that terms defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.
The invention is further illustrated by the following examples:
The invention provides a power frequency zero crossing counting time mark verification device based on a network synchronous clock, which is shown in figure 1 and comprises the following components:
comprising the following steps: the device comprises a power frequency zero-crossing signal source, a zero-crossing voltage driving circuit, a zero-crossing detection circuit, a communication signal separation circuit, a communication interception circuit, a high-precision adjustable clock source, a counting and latching circuit, a test control and calculation circuit:
The tested network central node equipment is connected with the test control and counting circuit through a bidirectional communication interface for central node data access, receives a central node data access command and replies central node data; the communication and zero-crossing voltage mixed signal interface of the tested network central node equipment is connected with the zero-crossing voltage driving circuit and the communication signal separation circuit;
the power frequency zero-crossing signal source, its zero-crossing voltage signal output end connects zero-crossing voltage driving circuit and zero-crossing voltage signal input end of the zero-crossing detection circuit;
The zero-crossing voltage driving circuit is connected with the network central node equipment to be tested and the communication signal separation circuit through a zero-crossing voltage mixed signal interface, and is used for driving zero-crossing voltage signals input by the power frequency zero-crossing signal source to meet the power requirement received by the central node equipment, has low output impedance at the power frequency, and simultaneously avoids the communication and zero-crossing voltage mixed signals from damaging the power frequency zero-crossing signal source;
The zero-crossing detection circuit outputs an effective zero-crossing trigger signal at a zero-crossing trigger signal output end of the zero-crossing detection circuit corresponding to the zero-crossing moment of the voltage signal according to the zero-crossing voltage signal from the power frequency zero-crossing signal source and the setting of the zero-crossing direction type, the zero-crossing trigger signal is a pulse level signal, and the zero-crossing direction type is provided with a voltage rising direction and a voltage falling direction;
the communication signal separation circuit is connected with the communication interception circuit at the communication signal output end;
the communication interception circuit generates an effective received beacon indication signal at a time corresponding to a beacon time mark specified by a communication standard according to a communication signal corresponding to the beacon message, and the output end of the received beacon indication signal is connected with the input end of the counting and latching circuit; the communication interception circuit sends a beacon time mark BC (i) and a zero-crossing time mark ZC (j) which are analyzed according to a communication signal from the central node equipment of the tested network to the test control and calculation circuit part, wherein i is the sequence number of each beacon time mark data, and j is the sequence number of each zero-crossing time mark data;
The output end of the high-precision adjustable clock source is connected with the input end of the communication interception circuit and the input end of the counting and latching circuit, and the high-precision adjustable clock source has an output frequency fine tuning function and low clock signal jitter;
the output end of the beacon latch count value B S (i) latched and output by the beacon indication signal received by the communication interception circuit and the zero crossing latch count value Z S (k) latched and output by the zero crossing trigger signal from the zero crossing detection circuit is connected with the test control and calculation circuit, wherein k is the serial number of each zero crossing latch count value;
The output end of the frequency setting parameter F 1 of the test control and calculation circuit is connected with the input end of the high-precision adjustable clock source, the output end of the count value increasing and decreasing control parameter J S is connected with the input end of the counting and latching circuit, the bidirectional communication interface of the central node data access is connected with the tested network central node equipment, and the test control and calculation circuit finally outputs the average error and variance error result of the power frequency zero crossing counting time scale of the tested network central node equipment.
The communication interception circuit and the test control and counting circuit adopt one circuit integrating a communication interception part and a test control and counting part.
The invention provides a power frequency zero crossing count time mark verification method based on a network synchronous clock, which is shown in fig. 2 and comprises the following steps:
Step 1, a test control and calculation circuit sends a communication starting command to a tested network central node device through central node access data, and starts the work of the tested network central node device and beacon message sending;
Step 2, setting a frequency setting parameter F 1 input to a high-precision adjustable clock source by a test control and calculation circuit to be 2 P times of a nominal working frequency F S of a communication network, namely F 1＝FS×2P, wherein P is a positive integer bit number amplified compared with a synchronous clock count value of the communication network of a network central node; under the control of a high-precision clock signal CLK 1 output by a high-precision adjustable clock source, the counting and latching circuit increases 1 count, the count value is an unsigned integer value, and after the count value reaches the maximum value, the cycle count is started from 0; the communication interception circuit receives a communication signal sent by the tested network central node equipment and passing through the communication signal separation circuit, when a beacon message of the tested network central node equipment is received, a received beacon indication signal in a valid pulse form is generated at a time corresponding to a beacon time mark specified by a communication standard, and then the beacon message is analyzed to obtain a beacon time mark B C1 (i) of the tested network central node equipment contained in the beacon message; when the received beacon indication signal changes from invalid to valid, the counting and latching circuit latches a beacon latch count value B S1 (i); the test control and calculation circuit calculates a frequency offset error measurement result E C of the measured network central node equipment according to the following formula according to a beacon time mark B C1 (i) and a beacon latch count value B S1(i),i＝0,1,…,N1 of the measured network central node equipment, which are obtained by N 1 beacon messages:
Step 3, the test control and calculation circuit sets the frequency setting parameter F 1 input to the high-precision adjustable clock source as F 1＝(1+EC)×FS×2P according to the frequency deviation error measurement result E C of the measured network central node equipment measured in the step 2;
Step 4, the communication interception circuit receives the communication signal sent by the tested network central node equipment and passing through the communication signal separation circuit, when the beacon message of the tested network central node equipment is received, a received beacon indication signal in a valid pulse form is generated at the corresponding moment of the beacon time mark specified by the communication standard, and then the beacon message is analyzed and the beacon time mark B C2 (i) of the tested network central node equipment contained in the beacon message is obtained; when the received beacon indication signal changes from invalid to valid, the counting and latching circuit latches a beacon latch count value B S2 (i); the test control and calculation circuit calculates the difference between the count value of the counting and latching circuit and the count value of the measured network central node equipment according to the following formula according to the beacon time mark B C2 (i) and the beacon latch count value B S2(i),i＝0,1,…,N2 of the measured network central node equipment obtained by N 2 beacon messages:
Step 5, the test control and calculation circuit sets a count value increasing and decreasing control parameter J S＝(CB+CP to the count and latch circuit; if J S is greater than 0, the current count value of the count and latch circuit is incremented (C B+CP); if J S is less than 0, the current count value of the count and latch circuit is decremented by |C B+CP |, where C P is the count value of the F S×2P frequency corresponding to the inherent delay T P of the communication listening circuit output received beacon indication signal, namely:
CP＝TP×FS×2P；
Step 6, the test control and calculation circuit sends a power frequency period message sending command to the central node equipment of the tested network through the central node access data, and starts the power frequency zero crossing count time mark message sending of the central node equipment of the tested network; the zero-crossing voltage signal generated by the power frequency zero-crossing signal source is input into the central node equipment of the network to be tested after passing through the zero-crossing voltage driving circuit to carry out zero-crossing detection, and the power frequency zero-crossing counting time mark is marked; meanwhile, a zero-crossing voltage signal generated by a power frequency zero-crossing signal source generates a zero-crossing trigger signal in an effective pulse form at a voltage zero-crossing moment through a zero-crossing detection circuit, and when the zero-crossing trigger signal is changed from invalid to valid, a counting and latching circuit latches a zero-crossing latch count value Z S (k) and outputs the zero-crossing latch count value Z S (k) to a test control and calculation circuit, wherein k is the serial number of the zero-crossing latch count value;
step 7, the communication interception circuit receives a communication signal sent by the central node equipment of the tested network and passing through the communication signal separation circuit, and when receiving a power frequency zero crossing count time mark message of the central node equipment of the tested network, analyzes the power frequency zero crossing count time mark message to obtain a power frequency zero crossing count time mark Z C (j) of the central node equipment of the tested network, wherein the power frequency zero crossing count time mark data corresponds to a plurality of continuous power frequency zero crossings which are obtained by the central node equipment of the tested network and are separated by a plurality of zero crossings; the test control and calculation circuit searches the zero-crossing latch count value Z S(kj meeting the requirement of |Z S(kj)-ZC(j)|<TZ according to Z C (j), wherein j is 1,2, … and the serial numbers of N 3, N 3 is the number of data used for error calculation, k j is the number of the zero-crossing latch count value, T Z is the threshold value for setting and searching the corresponding zero-crossing latch count value, and the value is smaller than (F S×2P-1)/F0,F0 is an operating frequency value;
Step 8, the average error E avg of the power frequency zero crossing count time scale of the tested network central node equipment output by the test control and calculation circuit is calculated according to the following formula:
Variance error sigma E of power frequency zero crossing counting time scale:
And finally outputting an average error E avg and a variance error sigma E as a test result of the power frequency zero crossing count time scale of the tested network central node equipment.
The invention completes the measurement of the power frequency zero crossing counting time mark error of the tested equipment based on the beacon message and the power frequency zero crossing counting time mark message sent by the network central node equipment;
The precision of the zero-crossing trigger signal output by the zero-crossing detection circuit of the device can be directly sampled and displayed and observed by adopting the oscilloscope and the zero-crossing voltage signal output by the power frequency zero-crossing signal source, so that the delay error of the zero-crossing trigger signal is determined and compensation and calibration are carried out.
The method of the invention, step 2, can adopt the network central node equipment with high precision clock to access for measurement.
Step one, obtaining a frequency offset error measurement result E C of the tested network central node equipment through the step 2.
Secondly, measuring the clock frequency F S of the network central node equipment and the output frequency F 1 of the high-precision adjustable clock by adopting a high-precision frequency meter, and calculating a frequency offset error E' C according to the following formula:
Finally, error analysis is carried out on the frequency offset error E' C obtained in the second step and the frequency offset error E C obtained in the first step so as to evaluate the frequency offset measurement precision of the device.
The frequency offset measurement precision of the device is influenced by the precision of the used high-precision adjustable clock source, the precision of the received signal indication signal output by the communication interception circuit, the number P of bits expanded by the counting and latching circuit, the number N 1 of beacon messages adopted by the test control and calculation circuit and the formula calculation precision and other performances, so that the performance bottleneck can be analyzed according to the performance bottleneck, and the frequency offset measurement precision of the device is improved. In addition, the problem of insufficient frequency offset measurement precision can also be found by the method, and the method comprises the following specific steps: firstly, measuring by adopting network central node equipment access with a high-precision clock, and executing the steps 1, 2 and 3 of the method; then, the frequency offset error is measured again according to the step 2 to confirm the frequency setting parameters set in the step 3, and if the obtained frequency offset error is close to 0, the frequency offset measurement precision and the frequency adjustment precision of the high-precision adjustable clock source of the device are better.
In step 5 of the method of the present invention, C P is a compensation parameter of the inherent delay of the output of the received beacon indication signal by the communication listening circuit in the device of the present invention.
The measurement step of C P is as follows: firstly, a standard network central node device capable of outputting a self-transmitted beacon time mark signal is accessed to the device; then adopting an oscilloscope to compare the beacon time mark signal output by the standard network central node equipment with the beacon receiving indication signal output by the communication interception circuit in the device, and measuring the delay time T P corresponding to the effective edge change of the signal; finally, C P is calculated and obtained according to the following formula, and is used for correcting the device of the invention:
CP＝TP×FS×2P。
The step designed by the power frequency zero crossing counting time scale verification method can strictly verify the precision of the device by the calibration method and perform self calibration.
Meanwhile, the method obtains the count which is the same as the measured network central node equipment in frequency and the average value of the count value error approaches to 0 through the frequency setting of the high-frequency adjustable clock source in the step5, so as to finish the inspection of the power frequency zero crossing count time mark, and realize the verifiability and the originality of the measuring method.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The scheme in the embodiment of the invention can be realized by adopting various computer languages, such as object-oriented programming language Java, an transliteration script language JavaScript and the like.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
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| CN109253749A (en) * | 2018-09-18 | 2019-01-22 | 中国电力科学研究院有限公司 | A kind of grade for measuring equipment clock error event determines method |
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| CN102680842A (en) * | 2012-06-06 | 2012-09-19 | 杭州海兴电力科技有限公司 | Distribution room automatic identification tester and identification method thereof |
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