CN118518932B

CN118518932B - Phase compensation method and system for power test unit

Info

Publication number: CN118518932B
Application number: CN202410985047.1A
Authority: CN
Inventors: 许晓东; 白洪超; 彭文敏
Original assignee: Qingdao Ainuo Instrument Co ltd
Current assignee: Qingdao Ainuo Instrument Co ltd
Priority date: 2024-07-23
Filing date: 2024-07-23
Publication date: 2024-10-22
Anticipated expiration: 2044-07-23
Also published as: CN118518932A

Abstract

The invention relates to the technical field of phase compensation, and discloses a phase compensation method and a phase compensation system for a power test unit, wherein the phase compensation method comprises the following steps: in a test mode, reading the delay amount; dividing a clock source with a preset frequency into a first test clock signal and a second test clock signal by using the time delay quantity, wherein the frequencies of the first test clock signal and the second test clock signal are equal; processing the first test clock signal into a test voltage CNV signal; processing the second test clock signal into a test current CNV signal; sampling the test voltage signal by using the test voltage CNV signal; sampling the test current signal by using the test current CNV signal; based on the sampled test voltage signal and test current signal, a power calculation is performed. The invention can accurately realize phase difference compensation.

Description

Phase compensation method and system for power test unit

Technical Field

The present invention relates to the field of phase compensation technologies, and in particular, to a phase compensation method and system for a power test unit.

Background

In the measurement of power test, the power accuracy of alternating voltage (or current) is an important measurement item, and at the same time of voltage and current test accuracy, how to eliminate the phase difference of voltage and current analog sampling becomes an industry pain point, especially in the new energy industry, the power consumption test is particularly important under the low power factor of the reactance of the photovoltaic inverter module, and most of the new energy related power tests not only relate to the local test, but also large current also needs to be matched with the connection of equipment such as a transformer, so that the accurate compensation of the test channel position deviation becomes the industry pain point.

The power test formula is: Wherein n is the number of sampling points in unit time, u _i is the voltage instantaneous sampling value, i _i is the current instantaneous sampling value, besides ensuring the precision of u _i and i _i, the phase difference between the sampling moments of u _i and i _i due to factors such as hardware is also an important factor affecting the active power measurement.

Currently, there are two most widely used phase compensation methods: one is a memory buffer method and the other is a hardware compensation method.

The memory buffer method is to increase the buffer mode of voltage and current sampling to adjust the phase of sampling point, before the data calculation, the voltage and current sampling point data is needed to be stored in the buffer, before the calculation, the data is moved back and forth by taking the sampling time as the unit, so as to achieve the effect of phase adjustment.

The method has the advantages of no influence of external and load conditions, and accurate and controllable offset time; the disadvantage is that (1) the offset step is a sampling period, for example, the sampling rate is 500kHz, the adjustable minimum time unit is 1/500 khz=2us, but when the actual offset time is smaller than the time, the offset value cannot be equal to the actual offset value, and there is a deviation, and (2) the cache part of hardware needs to be added in the cache, so that the cost is high, and the algorithm processing is also higher.

The hardware compensation method is to make the voltage or current analog path obtain the fixed phase compensation by the RC unit to delay the signal.

The method has the advantages of low cost and can be realized by adding a small number of devices; the method has the defects that (1) the fixed load and the hardware condition are limited, RC has a filtering effect, is accurate as a time delay circuit, and has weakening influence on broadband signals; (2) The change is inflexible, the adjustment delay needs to be changed into a hardware circuit, and if the method is applied to products, the method has an influence on later maintenance.

Therefore, how to find a phase compensation method which is accurate in modulation, small in step and capable of adapting to multiple scenes becomes an important difficulty in the field of low-power-factor power analysis,

The above information disclosed in this background section is only for enhancement of understanding of the background section of the application and therefore it may not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

The embodiment of the invention aims to provide a phase compensation method for a power test unit, which is used for obtaining the time delay between a standard source current and a standard source voltage in a debugging mode and applying the time delay to a test mode to enable CNV signals with time delay to change test voltage signals and sampling moments of test current signals, so that the effect of phase compensation is achieved, the influence on the phase difference between the current and the voltage is reduced, and the power test accuracy is improved.

In order to achieve the aim of the invention, the invention is realized by adopting the following technical scheme:

The application relates to a phase compensation method for a power test unit, which comprises a debugging mode and a test mode, wherein the debugging mode comprises the following steps:

dividing a clock source with a preset frequency into a first clock signal and a second clock signal, wherein the frequencies of the first clock signal and the second clock signal are equal;

processing the first clock signal into a voltage CNV signal;

processing the second clock signal into a current CNV signal;

Processing a standard source voltage signal into a voltage zero crossing point waveform by utilizing the voltage CNV signal;

Processing a standard source current signal into a current zero crossing point waveform by utilizing the current CNV signal, wherein the standard source current signal and the standard source voltage signal have the same phase;

based on the current zero crossing point waveform and the voltage zero crossing point waveform, respectively extracting current voltage signal zero crossing information;

Acquiring the time delay amount between the current and the voltage based on the extracted zero crossing information of the current and the voltage signals;

storing the delay amount;

the test mode comprises the following steps:

reading the delay amount;

dividing a clock source with preset frequency into a first test clock signal and a second test clock signal by using the time delay amount, wherein the frequencies of the first test clock signal and the second test clock signal are equal;

Processing the first test clock signal into a test voltage CNV signal;

processing the second test clock signal into a test current CNV signal;

sampling the test voltage signal by using the test voltage CNV signal;

sampling the test current signal by using the test current CNV signal;

based on the sampled test voltage signal and test current signal, a power calculation is performed.

In some embodiments of the present application, the phase compensation method further includes a switching mode for controlling switching between a debug mode and a test mode, the switching mode including the steps of:

when switching to a debugging mode, configuring a write address for storing the delay amount;

when switching to the test mode, a read address for reading the delay amount is configured.

In some embodiments of the present application, in the debug mode, all steps in the debug mode are sequentially cycled to obtain a plurality of delay amounts written in different addresses;

And in the test mode, correspondingly reading the delay amount under the corresponding address.

In some embodiments of the application, the crossover frequency of the clock source in the debug mode is greater than the crossover frequency of the clock source in the test mode.

In some embodiments of the present application, based on the current zero crossing waveform and the voltage zero crossing waveform, current voltage signal zero crossing information is extracted respectively, specifically, a plurality of current zero crossing moments and a plurality of corresponding voltage zero crossing moments are obtained;

based on the extracted zero crossing information of the current and voltage signals, the time delay between the current and the voltage is obtained, specifically:

Acquiring the number of sampling points between each current zero crossing point moment and the corresponding voltage zero crossing point moment;

Calculating the average value of the number of a plurality of sampling points;

Taking the product of the average value and the current sampling period as the time delay amount.

In some embodiments of the application, the calculating of the power comprises:

Calculating active power;

calculating apparent power;

calculating reactive power;

a power factor is calculated.

In the phase compensation method, in a debugging mode, a standard source voltage signal and a standard source current signal are adopted to obtain the time delay, and in a test mode, the time delay is applied to a voltage CNV signal and a current CNV signal to generate a CNV signal with time delay, so that the sampling time of a test voltage signal and a test current signal is changed, the phase difference caused by factors such as hardware is avoided, the phase compensation is realized, and the power test accuracy is improved.

The application also relates to a phase compensation system for a power test unit, comprising:

the clock source module is used for providing a clock source with preset frequency;

A mode control module for configuring a debug mode or a test mode;

The sampling frequency division module is used for dividing the clock source into a first clock signal and a second clock signal in the debugging mode, and the frequencies of the first clock signal and the second clock signal are equal;

a voltage ADC controller that processes the first clock signal into a voltage CNV signal in the debug mode;

A current ADC controller that processes the second clock signal into a current CNV signal in the test mode;

the voltage acquisition module is used for processing a standard source voltage signal into a voltage zero crossing point waveform by utilizing the voltage CNV signal in the debugging mode;

The current acquisition module is used for processing a standard source current signal into a current zero crossing point waveform by utilizing the current CNV signal in the debugging mode, wherein the standard source current signal and the standard source voltage signal have the same phase;

the zero acquisition module is used for receiving the current zero crossing point waveform and the voltage zero crossing point waveform and respectively extracting zero crossing information of current and voltage signals in the debugging mode;

the time delay calculation module is used for acquiring the time delay amount between the current and the voltage based on the extracted zero crossing information of the current and the voltage signals;

The time delay storage module is connected with the mode control module and is used for storing the time delay amount acquired by the time delay calculation module in the debugging mode;

in the test mode, the sampling frequency division module divides the clock source into a first test clock signal and a second test clock signal by using the time delay amount from the time delay storage module, wherein the frequencies of the first test clock signal and the second test clock signal are equal;

In the test mode, the voltage ADC controller processes the first test clock signal into a test voltage CNV signal, and the current ADC controller processes the second test clock signal into a test current CNV signal;

In the test mode, the voltage acquisition module samples a test voltage signal by using the test voltage CNV signal, and the current acquisition module samples a test current signal by using the current CNV signal;

And a data processing unit which performs power calculation based on the sampled test voltage signal and test current signal.

In some embodiments of the present application, in the debug mode, the mode control module configures the latency storage module to be a write mode, and issues a write address at the same time for storing the obtained latency amount;

The phase compensation system further includes:

The time delay reading module is respectively connected with the mode control module, the time delay storage module and the sampling frequency division module and is used for configuring a reading address when the mode control module controls the test module to enter, and the time delay reading module reads the corresponding time delay amount from the time delay storage module by utilizing the reading address and sends the corresponding time delay amount to the sampling frequency division module.

In some embodiments of the present application, the current zero crossing point waveform and the voltage zero crossing point waveform are received, and the current voltage signal zero crossing information is extracted respectively, specifically, a plurality of current zero crossing point moments and a plurality of corresponding voltage zero crossing point moments are obtained;

Calculating the average value of the number of a plurality of sampling points;

Other features and advantages of the present invention will become apparent upon review of the detailed description of the invention in conjunction with the drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart showing a phase compensation method for a power test unit according to an embodiment of the present invention in a debug mode;

FIG. 2 is a flow chart showing a phase compensation method for a power test unit according to an embodiment of the present invention in a test mode;

FIG. 3 is a block diagram of an embodiment of a phase compensation system for a power test unit according to the present invention;

FIG. 4 is a waveform diagram showing a voltage input signal and a current input signal related to an embodiment of a phase compensation method for a power test unit according to the present invention are a standard source voltage signal and a standard source current signal, respectively;

FIG. 5 shows the voltage and current waveforms after the offset is generated by the hardware circuit;

fig. 6 shows waveforms of the voltage CNV signal and the current CNV signal obtained before compensation;

FIG. 7 shows a plot of voltage CNV signal and current CNV signal versus offset voltage waveform and current waveform for an amount of applied time delay (i.e., after compensation);

fig. 8 shows voltage ADC sampling points and current ADC sampling points controlled according to the compensated CNV signal.

Reference numerals:

100. A clock source module; 200. a sampling frequency division module; 310. a voltage ADC controller; 320. a current ADC controller; 410. a voltage acquisition module; 420. a current collection module; 500. the zero acquisition module; 610. a time delay calculation module; 620. a time delay storage module; 630. a time delay reading module; 700. a data processing module; 800. and a mode control module.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.

All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. In the description of the present invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.

In the description of the present invention, it should be noted that the terms "mounted," "connected," and "coupled" are to be construed broadly, as well as, for example, fixedly coupled, detachably coupled, or integrally coupled, unless otherwise specifically indicated and defined. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art. In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the present application, in order to avoid the influence of the phase difference of the current sampling time and the voltage sampling time due to factors such as hardware on the power measurement, the present application solves the problem by phase compensation.

In some embodiments of the application, a phase compensation method and system for a power test unit is provided, the phase compensation method being implemented by means of a phase compensation system, and therefore, the phase compensation method will be described in connection with the phase compensation system as follows.

Wherein a power test unit refers to a unit, module or device that tests power, using the formulaThe test is performed, wherein n is the number of sampling points in unit time, u _i is the voltage instantaneous sampling value, and i _i is the current instantaneous sampling value.

In some embodiments of the present application, referring to fig. 3, the phase compensation system includes a clock source module 100, a sampling frequency division module 200, a mode control module 800, a delay storage module 620, a delay calculation module 610, a zero acquisition module 500, a voltage ADC controller 310, a current ADC controller 320, a voltage acquisition module 410, a current acquisition module 420, and a data processing module 700.

The phase compensation system includes a debug mode and a test mode.

The application adopts a time sequence preprocessing control mechanism, obtains the time delay amount of the current hardware system through a debugging mode, then in a test mode, invokes the corresponding time delay amount control sampling in the debugging mode, obtains phase compensated data through sampling and calculation, and improves the accuracy of power measurement.

A plurality of delay amounts may be acquired and stored in the debug mode, and correspondingly, the stored corresponding delay amounts are retrieved in the test mode.

One application scene (for example, different scenes of a hardware system, different scenes of a load, and the like) corresponds to one delay amount, and after a plurality of times of cyclic debugging modes, a plurality of groups of parameters can be debugged to adapt to different application scenes.

When the power test is performed under different application scenes, the phase compensation is performed by selecting different time delay amounts, the pertinence is strong, the compensation effect is good, the flexible use under multiple application scenes is satisfied, and the application range of the phase compensation system is improved.

In the debug mode, the phase compensation system includes a clock source module 100, a sampling frequency division module 200, a mode control module 800, a delay storage module 620, a delay calculation module 610, a zero acquisition module 500, a voltage ADC controller 310, a current ADC controller 320, a voltage acquisition module 410, and a current acquisition module 420.

In the test mode, the phase compensation system includes a clock source module 100, a sampling frequency division module 200, a mode control module 800, a delay storage module 620, a delay calculation module 610, a zero acquisition module 500, a voltage ADC controller 310, a current ADC controller 320, a voltage acquisition module 410, a current acquisition module 420, and a data processing module 700.

As follows, a phase compensation method will be described in detail with reference to the phase compensation system shown in fig. 3.

First, referring to fig. 1, a debug mode is described.

In debug mode, the following steps will be performed, respectively.

S11: a clock source having a predetermined frequency is divided into a first clock signal and a second clock signal.

The clock source module 100 provides a clock source of a predetermined frequency, which may be selected to be 100MHz in some embodiments of the application, alternatively, other frequencies may be selected, without limitation.

The sampling frequency division module 200 divides the frequency according to a clock source to generate two paths of clock signals: the clock signal comprises a first clock signal and a second clock signal, wherein the frequencies of the first clock signal and the second clock signal are equal.

In some embodiments of the present application, the frequency of the two clock signals may be selected to be 20MHz, alternatively, the frequency may be selected to be other frequencies, which is not limited herein.

S12: the first clock signal is processed as a voltage CNV (Conversion start) signal.

In the debug mode, the voltage ADC (analog-to-digital Conversion) controller 310 is configured to process the first clock signal into a voltage CNV (Conversion start) signal.

In some embodiments of the present application, the voltage ADC controller 310 is capable of tracking the first clock signal and converting to a voltage CNV signal for controlling the voltage ADC conversion timing.

S13: the second clock signal is processed into a current CNV signal.

In debug mode, current ADC controller 320 is configured to process the second clock signal into a current CNV signal.

In some embodiments of the present application, the current ADC controller 320 is capable of tracking the second clock signal and converting to a current CNV signal for controlling the current ADC conversion timing.

Referring to fig. 6, the pre-compensation voltage CNV signal and the pre-compensation current CNV signal are shown.

S14: and processing the standard source voltage signal into a voltage zero crossing waveform by using the voltage CNV signal.

In some embodiments of the present application, in order to accurately obtain the delay amount of the phase difference between the current and the voltage in the debug mode, the standard source voltage signal (see the voltage input signal shown in fig. 4) and the standard source current signal (see the current input signal shown in fig. 4) with the same phase are adopted to debug, so as to avoid the phase deviation caused by the difference between the voltage signal and the current signal.

In order to achieve the input of a standard source voltage signal, a voltage acquisition module 410 is provided.

The analog sample voltage terminal of the voltage acquisition module 410 receives the standard source voltage signal as a voltage input signal.

And the voltage CNV signal processed by the voltage ADC controller 310 is also sent to the voltage acquisition module 410, so as to control the voltage acquisition module 410 to sample the standard source voltage signal and provide a voltage zero-crossing waveform.

In some embodiments of the present application, the voltage acquisition module 410 includes an ADC, an op-amp, and a sampling device, and has two functions: (1) The ADC analog-to-digital conversion is controlled according to a voltage CNV signal issued by the voltage ADC controller 310; (2) The input signal is amplified and integrated to provide a voltage zero crossing waveform.

S15: the standard source current signal is processed into a current zero crossing waveform using the current CNV signal.

To enable the input of a standard source current signal, a current acquisition module 420 is provided.

The analog sample current terminal of the current acquisition module 420 receives the standard source current signal as a current input signal.

And the current CNV signal processed by the electric current ADC controller 320 is also sent to the current acquisition module 420, for controlling the current acquisition module 420 to sample the standard source current signal and provide a current zero crossing waveform.

In some embodiments of the present application, the current acquisition module 420 also includes an ADC, an op-amp, and a sampling device, which also has two functions: (1) The ADC analog-to-digital conversion is controlled according to a current CNV signal issued by the current ADC controller 320; (2) The input signal is amplified and integrated to provide a current zero crossing waveform.

A waveform diagram of the standard source voltage signal input by the voltage acquisition module 410 and the standard source current signal input by the current acquisition module 420 is shown in fig. 4; the waveforms shifted by the hardware circuit are shown in fig. 5, thus, it can be explained that the standard source voltage signal and the standard source current signal with the same phase should not have the voltage-current phase difference of zero, but the shifted waveforms shown in fig. 5 are generated due to the phase shift introduced by the hardware.

S16: and respectively extracting zero crossing information of the current and voltage signals based on the current zero crossing waveforms and the voltage zero crossing waveforms.

In some embodiments of the present application, zero point acquisition module 500 is used to extract zero crossing information of the current voltage signal based on the current zero crossing waveform and the voltage zero crossing waveform, respectively.

In some embodiments of the application, the zero crossing information comprises signal zero crossing times, and may comprise a plurality of consecutive zero crossing times.

For the voltage zero crossing waveforms, a plurality of continuous zero crossing moments can be obtained, for example, the first five zero crossing moments are obtained and recorded as: tu1 to Tu5.

For the current zero-crossing waveform, a plurality of continuous zero-crossing moments can be acquired, for example, the first five zero-crossing moments are acquired and recorded as: ti1 to Ti5.

Alternatively, other numbers of zero crossing times than five may be selected.

The first voltage zero crossing time corresponds to the first current zero crossing time, the second voltage zero crossing time corresponds to the second current zero crossing time, the third voltage zero crossing time corresponds to the third current zero crossing time, the fourth voltage zero crossing time corresponds to the fourth current zero crossing time, and the fifth voltage zero crossing time corresponds to the fifth current zero crossing time.

S17: and acquiring the time delay amount between the current and the voltage based on the extracted zero crossing information of the current and the voltage signals.

In some embodiments of the present application, the acquisition delay amount t is calculated using a delay calculation module 610.

In some embodiments of the present application, one of the voltage zero-crossing moments Tun and one of the current zero-crossing moments Tin corresponding to the voltage zero-crossing moment may be selected.

And obtaining the sampling point number N between the voltage zero crossing moment Tun and the current zero crossing moment Tin, wherein the time delay t is the product of the sampling point number N and the current sampling period.

To ensure data accuracy, the average value of the number of sampling points can be selected to calculate the time delay.

The method comprises the steps of recording the sampling point number between a first voltage zero crossing moment Tu1 and a first current zero crossing moment Ti1 as N1, the sampling point number between a second voltage zero crossing moment Tu2 and a second current zero crossing moment Ti2 as N2, the sampling point number between a third voltage zero crossing moment Tu3 and a third current zero crossing moment Ti3 as N3, the sampling point number between a fourth voltage zero crossing moment Tu4 and a fourth current zero crossing moment Ti4 as N4, and the sampling point number between a fifth voltage zero crossing moment Tu5 and a fifth current zero crossing moment Ti5 as N5.

Sampling point number n= (n1+n) 2+N3+N4 +n5)/5.

As described above, when dividing the 100MHz clock source into two 20MHz clock signals, the sampling period is 1/(20 x).

Therefore, the delay amount t is n×1/(20×10 ⁶), see fig. 7.

The delay amount t is the relative amount of the voltage signal and the current signal as described above, and the delay amount t is deduced backward in the case where the voltage signal is unchanged, and the delayed current signal is output.

S18: the amount of delay is stored.

In some embodiments of the present application, a latency storage module 620 is employed to store the amount of latency.

In order to facilitate the later invocation of the delay amount in the test mode, when the mode control module 800 is configured to enter the debug mode, a write address is further configured, and the delay amount is correspondingly written into the write address.

In some embodiments of the present application, for example, the write address is configured to waddr=0x0001, and when the delay amount is calculated, the delay amount is stored in the address Waddr.

So far, the debugging mode is finished, and the process of acquiring the time delay in the debugging process is completed.

And when another application scene in other hardware connection states is compensated, setting other Waddr to carry out debugging mode again.

Thus, the delay amount under multiple application scenes can be obtained.

After the time delay is obtained, the time delay is used in the test mode to generate a current CNV signal with time delay (the voltage CNV signal is unchanged) to change the sampling time of the current signal (the sampling time of the voltage signal is unchanged), so that the effect of phase compensation is achieved.

The test mode is described as follows with reference to fig. 2.

In the test mode, the following steps will be performed, respectively.

The test mode is performed on a test voltage signal and a test current signal.

S21: read latency.

In some embodiments of the application, to implement the invocation of the delay amount, referring to fig. 3, the phase compensation system further includes a delay reading module 630.

The delay reading module 630 is respectively connected to the mode control module 800, the delay storage module 620 and the sampling frequency division module 200.

As described above, there is one write address for each latency, so when the latency needs to be invoked, it is sufficient to read through that address.

In some embodiments of the present application, when the mode control module 800 controls entering the test mode, a read address is configured, and the delay reading module 630 reads the delay amount from the delay storage module 620 according to the read address and sends the delay amount to the sampling frequency division module 200.

In some embodiments of the present application, the read address is set to waddr=0x0001.

The latency reading module 630 reads the corresponding latency amount from the latency storage module 620 according to the read address set to Waddr.

S22: and dividing the clock source with the preset frequency into a first test clock signal and a second test clock signal by using the delay amount.

In some embodiments of the application, the preset frequency may be selected to be 100MHz.

The sampling frequency division module 200 divides frequencies according to a clock source to generate two paths of test clock signals: a first test clock signal and a second test clock signal.

The frequencies of the first test clock signal and the second test clock signal are equal.

In some embodiments of the present application, the frequency of the two test clock signals may be 1MHz, alternatively, other frequencies may be selected, which is not limited herein.

In some embodiments of the present application, the frequency of the frequency division of the clock source in the test mode is less than the frequency of the frequency division of the clock source in the debug mode, and higher frequency sampling can ensure higher delay amount accuracy for compensation, thus improving power measurement accuracy when applied.

S23: the first test clock signal is processed into a test voltage CNV signal.

In the test mode, the voltage ADC (analog-to-digital Conversion) controller 310 is configured to process the first test clock signal into a test voltage CNV (Conversion start) signal.

In some embodiments of the present application, the voltage ADC controller 310 is capable of tracking the first test clock signal and converting to a voltage CNV signal for controlling the voltage ADC conversion timing.

S24: the second test clock signal is processed into a test current CNV signal.

In the test mode, the current ADC controller 320 is configured to process the second test clock signal into a test current CNV signal.

In some embodiments of the present application, the current ADC controller 320 is capable of tracking the second test clock signal and converting to a test current CNV signal for controlling the current ADC conversion timing.

With the amount of delay, the compensated test voltage CNV signal and the compensated current CNV signal are shown in fig. 7.

Compared with fig. 6, the voltage CNV signal before compensation and the voltage CNV signal after compensation (i.e., the test voltage CNV signal) are the same, and the current CNV signal after compensation (i.e., the test current CNV signal) is delayed by a delay amount t with respect to the current CNV signal before compensation.

S25: and sampling the test voltage signal by using the test voltage CNV signal.

The test voltage CNV signal is used to control the sampling time of the test voltage signal.

S26: and sampling the test current signal by using the test current CNV signal.

The test current CNV signal is used to control the sampling instant of the test current signal.

Thus, referring to fig. 7 and 8, the sampling time of the test voltage signal and the sampling time of the test current signal are controlled by using the test voltage CNV signal and the test current CNV signal, respectively, so as to obtain the voltage ADC sampling point and the current ADC sampling point shown in fig. 8.

As can be seen from the waveforms shown in fig. 7, if the standard source voltage signal is used as the test voltage signal and the standard source current signal is used as the test current signal, the waveform (see fig. 8) sampled by the compensated ADC is restored to the original signal (see fig. 4) to the maximum extent, so that the problem of phase difference compensation caused by factors such as hardware is solved, and therefore, the collected voltage sampling point and current sampling point are accurate when power calculation is performed.

S27: based on the sampled test voltage signal and test current signal, a power calculation is performed.

In some embodiments of the application, the calculation of power includes calculating active power, calculating apparent power, calculating reactive power, and calculating power factor.

Voltage effective value: urms =Where N is the number of samples and u _n is the voltage sample value (n=1, 2, 3.. The term "N").

Current effective value: irms=Where N is the number of samples and i _n is the voltage sample value.

Active power p=。

Apparent power s= Urms ×irms.

Reactive power q=s×。

As described above, the voltage signal and the current signal can be accurately sampled by using the phase compensation method as described above, and thus, the accuracy of the obtained power is also improved.

In some embodiments of the present application, the clock source module 100, the sampling frequency division module 200, the voltage ADC controller 310, the current ADC controller 320, the zero acquisition module 500, the data processing module 700, the delay storage module 620, the delay reading module 630 and the mode control module 800 may be supported by FPGAs as hardware, in which a software function module is set, mainly responsible for obtaining the delay amount, and driving to generate a CNV signal with delay to change the voltage and current sampling time, so as to achieve the phase compensation effect.

As shown in fig. 3, the 100MHz clock source is matched with zero crossing point sampling number calculation, so that the compensation step is guaranteed to meet the compensation precision requirement of 1M sampling bandwidth equipment, and the maximum compensation can be performed for 10ns, and the high-precision compensation effect is realized.

Referring to fig. 3, the phase compensation system of the present application has high modularization degree, low coupling degree, clear interface and high portability degree, and is convenient for being applied to various test units.

The phase compensation system can support multiple application scenes, and different time delay amounts are called to realize the application of multiple scenes under different application scenes without changing a hardware structure.

The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be apparent to one skilled in the art that modifications may be made to the technical solutions described in the foregoing embodiments, or equivalents may be substituted for some of the technical features thereof; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.

Claims

1. The phase compensation method for the power test unit is characterized by comprising a debugging mode, a test mode and a switching mode for controlling the switching of the debugging mode and the test mode, wherein the debugging mode comprises the following steps of:

processing the first clock signal into a voltage CNV signal;

processing the second clock signal into a current CNV signal;

Acquiring a plurality of current zero crossing points and a plurality of corresponding voltage zero crossing points based on the current zero crossing point waveform and the voltage zero crossing point waveform;

Acquiring the number of sampling points between each current zero crossing point moment and the corresponding voltage zero crossing point moment, calculating the average value of the number of the plurality of sampling points, and taking the product of the average value and the current sampling period as the time delay amount between the current and the voltage;

Storing the delay amount; the test mode comprises the following steps:

reading the delay amount;

Processing the first test clock signal into a test voltage CNV signal;

processing the second test clock signal into a test current CNV signal;

sampling the test voltage signal by using the test voltage CNV signal;

sampling the test current signal by using the test current CNV signal;

Performing power calculation based on the sampled test voltage signal and test current signal;

Wherein the frequency division frequency of the clock source in the debug mode is greater than the frequency division frequency of the clock source in the test mode;

The switching mode includes: when switching to a debugging mode, configuring a write address for storing the delay amount; when switching to the test mode, a read address for reading the delay amount is configured.

2. The method for phase compensation for a power test unit according to claim 1, wherein,

In the debugging mode, all steps in the debugging mode are sequentially circulated, and a plurality of time delay amounts written in different addresses are obtained;

3. The phase compensation method for a power test unit according to claim 1, wherein the calculation of the power includes:

Calculating active power;

calculating apparent power;

calculating reactive power;

a power factor is calculated.

4. A phase compensation system for a power test unit, comprising:

a mode control module for configuring a debug mode, a test mode, and a switch mode for controlling switching of the debug mode and the test mode;

a current ADC controller that processes the second clock signal into a current CNV signal in the debug mode;

The zero acquisition module is used for receiving the current zero crossing point waveform and the voltage zero crossing point waveform in the debugging mode and acquiring a plurality of current zero crossing point moments and a plurality of corresponding voltage zero crossing point moments;

The time delay calculation module is used for obtaining the number of sampling points between each current zero crossing point moment and the corresponding voltage zero crossing point moment, calculating the average value of the number of the plurality of sampling points, and taking the product of the average value and the current sampling period as the time delay amount between the current and the voltage;

The time delay storage module is connected with the mode control module and is used for configuring the time delay storage module into a writing mode and simultaneously issuing a writing address in the debugging mode, and the time delay storage module is used for storing the time delay amount acquired by the time delay calculation module;

The time delay reading module is respectively connected with the mode control module, the time delay storage module and the sampling frequency division module and is used for configuring a reading address when the mode control module controls the test module to enter, and the time delay reading module reads the corresponding time delay amount from the time delay storage module by utilizing the reading address and sends the corresponding time delay amount to the sampling frequency division module;

a data processing unit that performs power calculation based on the sampled test voltage signal and test current signal;

wherein the frequency division frequency of the clock source in the debug mode is greater than the frequency division frequency of the clock source in the test mode.